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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-sparc/] [obio.h] - Blame information for rev 1275

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1 1275 phoenix 
/* $Id: obio.h,v 1.1.1.1 2004-04-15 02:40:31 phoenix Exp $
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 * obio.h:  Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
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 *
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 * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
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 */
6 
 
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#ifndef _SPARC_OBIO_H
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#define _SPARC_OBIO_H
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#include <asm/asi.h>
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/* This weird monster likes to use the very upper parts of
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   36bit PA for these things :) */
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/* CSR space (for each XDBUS)
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 *  ------------------------------------------------------------------------
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 *  |   0xFE  |   DEVID    |                | XDBUS ID |                   |
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 *  ------------------------------------------------------------------------
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 *  35      28 27        20 19            10 9        8 7                 0
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 */
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#define CSR_BASE_ADDR           0xe0000000
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#define CSR_CPU_SHIFT           (32 - 4 - 5)
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#define CSR_XDBUS_SHIFT         8
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#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
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/* ECSR space (not for each XDBUS)
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 *  ------------------------------------------------------------------------
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 *  |   0xF  | DEVID[7:1] |                                                |
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 *  ------------------------------------------------------------------------
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 *  35     32 31        25 24                                             0
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 */
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#define ECSR_BASE_ADDR          0x00000000
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#define ECSR_CPU_SHIFT          (32 - 5)
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#define ECSR_DEV_SHIFT          (32 - 8)
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#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
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#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
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/* Bus Watcher */
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#define BW_LOCAL_BASE           0xfff00000
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#define BW_CID                  0x00000000
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#define BW_DBUS_CTRL            0x00000008
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#define BW_DBUS_DATA            0x00000010
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#define BW_CTRL                 0x00001000
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#define BW_INTR_TABLE           0x00001040
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#define BW_INTR_TABLE_CLEAR     0x00001080
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#define BW_PRESCALER            0x000010c0
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#define BW_PTIMER_LIMIT         0x00002000
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#define BW_PTIMER_COUNTER2      0x00002004
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#define BW_PTIMER_NDLIMIT       0x00002008
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#define BW_PTIMER_CTRL          0x0000200c
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#define BW_PTIMER_COUNTER       0x00002010
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#define BW_TIMER_LIMIT          0x00003000
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#define BW_TIMER_COUNTER2       0x00003004
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#define BW_TIMER_NDLIMIT        0x00003008
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#define BW_TIMER_CTRL           0x0000300c
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#define BW_TIMER_COUNTER        0x00003010
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/* BW Control */
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#define BW_CTRL_USER_TIMER      0x00000004      /* Is User Timer Free run enabled */
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/* Boot Bus */
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#define BB_LOCAL_BASE           0xf0000000
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#define BB_STAT1                0x00100000
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#define BB_STAT2                0x00120000
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#define BB_STAT3                0x00140000
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#define BB_LEDS                 0x002e0000
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/* Bits in BB_STAT2 */
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#define BB_STAT2_AC_INTR        0x04    /* Aiee! 5ms and power is gone... */
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#define BB_STAT2_TMP_INTR       0x10    /* My Penguins are burning. Are you able to smell it? */
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#define BB_STAT2_FAN_INTR       0x20    /* My fan refuses to work */
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#define BB_STAT2_PWR_INTR       0x40    /* On SC2000, one of the two ACs died. Ok, we go on... */
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#define BB_STAT2_MASK           (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
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/* Cache Controller */
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#define CC_BASE         0x1F00000
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#define CC_DATSTREAM    0x1F00000  /* Data stream register */
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#define CC_DATSIZE      0x1F0003F  /* Size */
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#define CC_SRCSTREAM    0x1F00100  /* Source stream register */
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#define CC_DESSTREAM    0x1F00200  /* Destination stream register */
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#define CC_RMCOUNT      0x1F00300  /* Count of references and misses */
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#define CC_IPEN         0x1F00406  /* Pending Interrupts */
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#define CC_IMSK         0x1F00506  /* Interrupt Mask */
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#define CC_ICLR         0x1F00606  /* Clear pending Interrupts */
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#define CC_IGEN         0x1F00704  /* Generate Interrupt register */
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#define CC_STEST        0x1F00804  /* Internal self-test */
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#define CC_CREG         0x1F00A04  /* Control register */
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#define CC_SREG         0x1F00B00  /* Status register */
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#define CC_RREG         0x1F00C04  /* Reset register */
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#define CC_EREG         0x1F00E00  /* Error code register */
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#define CC_CID          0x1F00F04  /* Component ID */
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#ifndef __ASSEMBLY__
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extern __inline__ int bw_get_intr_mask(int sbus_level)
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{
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        int mask;
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        __asm__ __volatile__ ("lduha [%1] %2, %0" :
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                              "=r" (mask) :
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                              "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
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                              "i" (ASI_M_CTL));
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        return mask;
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}
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extern __inline__ void bw_clear_intr_mask(int sbus_level, int mask)
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{
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        __asm__ __volatile__ ("stha %0, [%1] %2" : :
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                              "r" (mask),
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                              "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
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                              "i" (ASI_M_CTL));
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}
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extern __inline__ unsigned bw_get_prof_limit(int cpu)
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{
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        unsigned limit;
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        __asm__ __volatile__ ("lda [%1] %2, %0" :
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                              "=r" (limit) :
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                              "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
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                              "i" (ASI_M_CTL));
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        return limit;
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}
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extern __inline__ void bw_set_prof_limit(int cpu, unsigned limit)
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{
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        __asm__ __volatile__ ("sta %0, [%1] %2" : :
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                              "r" (limit),
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                              "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
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                              "i" (ASI_M_CTL));
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}
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extern __inline__ unsigned bw_get_ctrl(int cpu)
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{
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        unsigned ctrl;
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        __asm__ __volatile__ ("lda [%1] %2, %0" :
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                              "=r" (ctrl) :
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                              "r" (CSR_BASE(cpu) + BW_CTRL),
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                              "i" (ASI_M_CTL));
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        return ctrl;
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}
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extern __inline__ void bw_set_ctrl(int cpu, unsigned ctrl)
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{
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        __asm__ __volatile__ ("sta %0, [%1] %2" : :
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                              "r" (ctrl),
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                              "r" (CSR_BASE(cpu) + BW_CTRL),
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                              "i" (ASI_M_CTL));
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}
157 
 
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extern unsigned char cpu_leds[32];
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extern __inline__ void show_leds(int cpuid)
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{
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        cpuid &= 0x1e;
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        __asm__ __volatile__ ("stba %0, [%1] %2" : :
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                              "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
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                              "r" (ECSR_BASE(cpuid) | BB_LEDS),
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                              "i" (ASI_M_CTL));
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}
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extern __inline__ unsigned cc_get_ipen(void)
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{
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        unsigned pending;
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173 
        __asm__ __volatile__ ("lduha [%1] %2, %0" :
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                              "=r" (pending) :
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                              "r" (CC_IPEN),
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                              "i" (ASI_M_MXCC));
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        return pending;
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}
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extern __inline__ void cc_set_iclr(unsigned clear)
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{
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        __asm__ __volatile__ ("stha %0, [%1] %2" : :
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                              "r" (clear),
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                              "r" (CC_ICLR),
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                              "i" (ASI_M_MXCC));
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}
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extern __inline__ unsigned cc_get_imsk(void)
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{
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        unsigned mask;
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        __asm__ __volatile__ ("lduha [%1] %2, %0" :
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                              "=r" (mask) :
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                              "r" (CC_IMSK),
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                              "i" (ASI_M_MXCC));
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        return mask;
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}
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extern __inline__ void cc_set_imsk(unsigned mask)
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{
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        __asm__ __volatile__ ("stha %0, [%1] %2" : :
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                              "r" (mask),
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                              "r" (CC_IMSK),
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                              "i" (ASI_M_MXCC));
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}
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extern __inline__ unsigned cc_get_imsk_other(int cpuid)
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{
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        unsigned mask;
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211 
        __asm__ __volatile__ ("lduha [%1] %2, %0" :
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                              "=r" (mask) :
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                              "r" (ECSR_BASE(cpuid) | CC_IMSK),
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                              "i" (ASI_M_CTL));
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        return mask;
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}
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218 
extern __inline__ void cc_set_imsk_other(int cpuid, unsigned mask)
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{
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        __asm__ __volatile__ ("stha %0, [%1] %2" : :
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                              "r" (mask),
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                              "r" (ECSR_BASE(cpuid) | CC_IMSK),
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                              "i" (ASI_M_CTL));
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}
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226 
extern __inline__ void cc_set_igen(unsigned gen)
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{
228 
        __asm__ __volatile__ ("sta %0, [%1] %2" : :
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                              "r" (gen),
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                              "r" (CC_IGEN),
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                              "i" (ASI_M_MXCC));
232 
}
233 
 
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/* +-------+-------------+-----------+------------------------------------+
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 * | bcast |  devid      |   sid     |              levels mask           |
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 * +-------+-------------+-----------+------------------------------------+
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 *  31      30         23 22       15 14                                 0
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 */
239 
#define IGEN_MESSAGE(bcast, devid, sid, levels) \
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        (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
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242 
extern __inline__ void sun4d_send_ipi(int cpu, int level)
243 
{
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        cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
245 
}
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247 
#endif /* !__ASSEMBLY__ */
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#endif /* !(_SPARC_OBIO_H) */

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