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/* $Id: asi.h,v 1.1.1.1 2004-04-15 03:00:55 phoenix Exp $ */
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#ifndef _SPARC64_ASI_H
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#define _SPARC64_ASI_H
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/* asi.h: Address Space Identifier values for the V9.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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/* V9 Architecture mandary ASIs. */
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#define ASI_N 0x04 /* Nucleus */
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#define ASI_NL 0x0c /* Nucleus, little endian */
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#define ASI_AIUP 0x10 /* Primary, user */
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#define ASI_AIUS 0x11 /* Secondary, user */
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#define ASI_AIUPL 0x18 /* Primary, user, little endian */
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#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
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#define ASI_P 0x80 /* Primary, implicit */
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#define ASI_S 0x81 /* Secondary, implicit */
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#define ASI_PNF 0x82 /* Primary, no fault */
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#define ASI_SNF 0x83 /* Secondary, no fault */
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#define ASI_PL 0x88 /* Primary, implicit, little endian */
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#define ASI_SL 0x89 /* Secondary, implicit, little endian */
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#define ASI_PNFL 0x8a /* Primary, no fault, little endian */
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#define ASI_SNFL 0x8b /* Secondary, no fault, little endian */
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/* SpitFire and later extended ASIs. The "(III)" marker designates
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* UltraSparc-III specific ASIs.
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*/
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#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
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#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
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#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian */
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#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
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#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
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#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, little endian */
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#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data status RAM diag */
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#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
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#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
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#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
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#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
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#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
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#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
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#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
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#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
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#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qword load, little endian */
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#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
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#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
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#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
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#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
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#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
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#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control Register */
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#define ASI_DCACHE_DATA 0x46 /* Data cache data-ram diag access */
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#define ASI_DCACHE_TAG 0x47 /* Data cache tag/valid ram diag access */
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#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
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#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
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#define ASI_UPA_CONFIG 0x4a /* UPA config space */
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#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
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#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
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#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
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#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
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#define ASI_AFSR 0x4c /* Async fault status register */
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#define ASI_AFAR 0x4d /* Async fault address register */
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#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag access */
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#define ASI_IMMU 0x50 /* Insn-MMU main register space */
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#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer register */
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#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer register */
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#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in register */
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#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access register */
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#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read register */
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#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
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#define ASI_DMMU 0x58 /* Data-MMU main register space */
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#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer register */
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#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer register */
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#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer register */
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#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in register */
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#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access register */
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#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read register */
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#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
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#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint register */
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#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag access */
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#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag access */
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#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram diag */
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#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag access */
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#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag access */
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#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag */
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#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
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#define ASI_BLK_AIUS 0x71 /* Secondary, user, block load/store */
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#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller registers */
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#define ASI_EC_DATA 0x74 /* (III) E-cache data staging register */
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#define ASI_EC_CTRL 0x75 /* (III) E-cache control register */
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#define ASI_EC_W 0x76 /* E-cache diag write access */
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#define ASI_UDB_ERROR_W 0x77 /* External UDB error registers write */
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#define ASI_UDB_CONTROL_W 0x77 /* External UDB control registers write */
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#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
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#define ASI_INTR_DATAN_W 0x77 /* (III) Outgoing irq vector data reg N */
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#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
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#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st */
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#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st */
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#define ASI_EC_R 0x7e /* E-cache diag read access */
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#define ASI_UDBH_ERROR_R 0x7f /* External UDB error registers read hi */
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#define ASI_UDBL_ERROR_R 0x7f /* External UDB error registers read low */
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#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control registers read hi */
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#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control registers read low */
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#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
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#define ASI_INTR_DATAN_R 0x7f /* (III) Incoming irq vector data reg N */
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#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
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#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
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#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
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#define ASI_PST16_S 0xc3 /* Seconary, 4 16-bit, partial */
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#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
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#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
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#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, little */
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#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, little */
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#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, little */
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#define ASI_PST16_SL 0xcb /* Seconary, 4 16-bit, partial, little */
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#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, little */
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#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, little */
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#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
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#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
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#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
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#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
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#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, little */
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#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, little */
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#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, little */
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#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st, little */
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#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
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#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
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#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
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#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
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#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
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#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
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#endif /* _SPARC64_ASI_H */
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