URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
1276 |
phoenix |
/* $Id: dcr.h,v 1.1.1.1 2004-04-15 03:00:56 phoenix Exp $ */
|
| 2 |
|
|
#ifndef _SPARC64_DCR_H
|
| 3 |
|
|
#define _SPARC64_DCR_H
|
| 4 |
|
|
|
| 5 |
|
|
/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
|
| 6 |
|
|
#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
|
| 7 |
|
|
#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */
|
| 8 |
|
|
#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */
|
| 9 |
|
|
#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */
|
| 10 |
|
|
#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */
|
| 11 |
|
|
#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
|
| 12 |
|
|
#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */
|
| 13 |
|
|
#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */
|
| 14 |
|
|
|
| 15 |
|
|
#endif /* _SPARC64_DCR_H */
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
