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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-sparc64/] [ide.h] - Blame information for rev 1765

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1 1276 phoenix 
/* $Id: ide.h,v 1.1.1.1 2004-04-15 03:00:56 phoenix Exp $
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 * ide.h: Ultra/PCI specific IDE glue.
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 *
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 * Copyright (C) 1997  David S. Miller (davem@caip.rutgers.edu)
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 * Copyright (C) 1998  Eddie C. Dost   (ecd@skynet.be)
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 */
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#ifndef _SPARC64_IDE_H
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#define _SPARC64_IDE_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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#include <asm/pgalloc.h>
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#include <asm/io.h>
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#include <asm/hdreg.h>
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#include <asm/page.h>
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#include <asm/spitfire.h>
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#ifndef MAX_HWIFS
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# ifdef CONFIG_BLK_DEV_IDEPCI
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#define MAX_HWIFS       10
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# else
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#define MAX_HWIFS       2
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# endif
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#endif
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static __inline__ int ide_default_irq(ide_ioreg_t base)
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{
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        return 0;
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}
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static __inline__ ide_ioreg_t ide_default_io_base(int index)
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{
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        return 0;
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}
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static __inline__ void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, ide_ioreg_t ctrl_port, int *irq)
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{
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        ide_ioreg_t reg =  data_port;
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        int i;
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        for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
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                hw->io_ports[i] = reg;
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                reg += 1;
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        }
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        if (ctrl_port) {
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                hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
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        } else {
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                hw->io_ports[IDE_CONTROL_OFFSET] = 0;
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        }
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        if (irq != NULL)
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                *irq = 0;
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        hw->io_ports[IDE_IRQ_OFFSET] = 0;
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}
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/*
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 * This registers the standard ports for this architecture with the IDE
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 * driver.
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 */
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static __inline__ void ide_init_default_hwifs(void)
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{
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#ifndef CONFIG_BLK_DEV_IDEPCI
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        hw_regs_t hw;
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        int index;
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        for (index = 0; index < MAX_HWIFS; index++) {
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                ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
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                hw.irq = ide_default_irq(ide_default_io_base(index));
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                ide_register_hw(&hw, NULL);
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        }
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#endif /* CONFIG_BLK_DEV_IDEPCI */
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}
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#undef  SUPPORT_SLOW_DATA_PORTS
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#define SUPPORT_SLOW_DATA_PORTS 0
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#undef  SUPPORT_VLB_SYNC
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#define SUPPORT_VLB_SYNC 0
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#undef  HD_DATA
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#define HD_DATA ((ide_ioreg_t)0)
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#define __ide_insl(data_reg, buffer, wcount) \
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        __ide_insw(data_reg, buffer, (wcount)<<1)
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#define __ide_outsl(data_reg, buffer, wcount) \
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        __ide_outsw(data_reg, buffer, (wcount)<<1)
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/* On sparc64, I/O ports and MMIO registers are accessed identically.  */
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#define __ide_mm_insw   __ide_insw
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#define __ide_mm_insl   __ide_insl
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#define __ide_mm_outsw  __ide_outsw
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#define __ide_mm_outsl  __ide_outsl
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static __inline__ unsigned int inw_be(unsigned long addr)
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{
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        unsigned int ret;
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        __asm__ __volatile__("lduha [%1] %2, %0"
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                             : "=r" (ret)
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                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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        return ret;
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}
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static __inline__ void __ide_insw(unsigned long port,
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                                  void *dst,
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                                  u32 count)
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{
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#if (L1DCACHE_SIZE > PAGE_SIZE)         /* is there D$ aliasing problem */
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        unsigned long end = (unsigned long)dst + (count << 1);
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#endif
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        u16 *ps = dst;
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        u32 *pi;
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        if(((u64)ps) & 0x2) {
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                *ps++ = inw_be(port);
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                count--;
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        }
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        pi = (u32 *)ps;
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        while(count >= 2) {
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                u32 w;
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                w  = inw_be(port) << 16;
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                w |= inw_be(port);
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                *pi++ = w;
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                count -= 2;
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        }
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        ps = (u16 *)pi;
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        if(count)
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                *ps++ = inw_be(port);
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#if (L1DCACHE_SIZE > PAGE_SIZE)         /* is there D$ aliasing problem */
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        __flush_dcache_range((unsigned long)dst, end);
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#endif
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}
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static __inline__ void outw_be(unsigned short w, unsigned long addr)
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{
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        __asm__ __volatile__("stha %0, [%1] %2"
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                             : /* no outputs */
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                             : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static __inline__ void __ide_outsw(unsigned long port,
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                                   void *src,
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                                   u32 count)
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{
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#if (L1DCACHE_SIZE > PAGE_SIZE)         /* is there D$ aliasing problem */
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        unsigned long end = (unsigned long)src + (count << 1);
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#endif
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        const u16 *ps = src;
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        const u32 *pi;
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        if(((u64)src) & 0x2) {
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                outw_be(*ps++, port);
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                count--;
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        }
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        pi = (const u32 *)ps;
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        while(count >= 2) {
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                u32 w;
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                w = *pi++;
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                outw_be((w >> 16), port);
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                outw_be(w, port);
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                count -= 2;
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        }
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        ps = (const u16 *)pi;
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        if(count)
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                outw_be(*ps, port);
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#if (L1DCACHE_SIZE > PAGE_SIZE)         /* is there D$ aliasing problem */
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        __flush_dcache_range((unsigned long)src, end);
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#endif
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}
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#endif /* __KERNEL__ */
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#endif /* _SPARC64_IDE_H */

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