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phoenix |
/* $Id: sab82532.h,v 1.1.1.1 2004-04-15 03:01:10 phoenix Exp $
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* sab82532.h: Register Definitions for the Siemens SAB82532 DUSCC
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*
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* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
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*/
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#ifndef _SPARC64_SAB82532_H
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#define _SPARC64_SAB82532_H
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <linux/circ_buf.h>
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struct sab82532_async_rd_regs {
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u8 rfifo[0x20]; /* Receive FIFO */
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u8 star; /* Status Register */
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u8 __pad1;
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u8 mode; /* Mode Register */
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u8 timr; /* Timer Register */
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u8 xon; /* XON Character */
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u8 xoff; /* XOFF Character */
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u8 tcr; /* Termination Character Register */
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u8 dafo; /* Data Format */
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u8 rfc; /* RFIFO Control Register */
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u8 __pad2;
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u8 rbcl; /* Receive Byte Count Low */
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u8 rbch; /* Receive Byte Count High */
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u8 ccr0; /* Channel Configuration Register 0 */
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u8 ccr1; /* Channel Configuration Register 1 */
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u8 ccr2; /* Channel Configuration Register 2 */
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u8 ccr3; /* Channel Configuration Register 3 */
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u8 __pad3[4];
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u8 vstr; /* Version Status Register */
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u8 __pad4[3];
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u8 gis; /* Global Interrupt Status */
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u8 ipc; /* Interrupt Port Configuration */
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u8 isr0; /* Interrupt Status 0 */
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u8 isr1; /* Interrupt Status 1 */
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u8 pvr; /* Port Value Register */
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u8 pis; /* Port Interrupt Status */
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u8 pcr; /* Port Configuration Register */
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u8 ccr4; /* Channel Configuration Register 4 */
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};
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struct sab82532_async_wr_regs {
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u8 xfifo[0x20]; /* Transmit FIFO */
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u8 cmdr; /* Command Register */
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u8 __pad1;
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u8 mode;
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u8 timr;
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u8 xon;
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u8 xoff;
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u8 tcr;
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u8 dafo;
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u8 rfc;
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u8 __pad2;
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u8 xbcl; /* Transmit Byte Count Low */
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u8 xbch; /* Transmit Byte Count High */
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u8 ccr0;
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u8 ccr1;
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u8 ccr2;
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u8 ccr3;
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u8 tsax; /* Time-Slot Assignment Reg. Transmit */
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u8 tsar; /* Time-Slot Assignment Reg. Receive */
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u8 xccr; /* Transmit Channel Capacity Register */
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u8 rccr; /* Receive Channel Capacity Register */
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u8 bgr; /* Baud Rate Generator Register */
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u8 tic; /* Transmit Immediate Character */
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u8 mxn; /* Mask XON Character */
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u8 mxf; /* Mask XOFF Character */
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u8 iva; /* Interrupt Vector Address */
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u8 ipc;
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u8 imr0; /* Interrupt Mask Register 0 */
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u8 imr1; /* Interrupt Mask Register 1 */
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u8 pvr;
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u8 pim; /* Port Interrupt Mask */
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u8 pcr;
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u8 ccr4;
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};
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struct sab82532_async_rw_regs { /* Read/Write registers */
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u8 __pad1[0x20];
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u8 __pad2;
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u8 __pad3;
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u8 mode;
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u8 timr;
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u8 xon;
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u8 xoff;
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u8 tcr;
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u8 dafo;
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u8 rfc;
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u8 __pad4;
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u8 __pad5;
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u8 __pad6;
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u8 ccr0;
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u8 ccr1;
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u8 ccr2;
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u8 ccr3;
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u8 __pad7;
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u8 __pad8;
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u8 __pad9;
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u8 __pad10;
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u8 __pad11;
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u8 __pad12;
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u8 __pad13;
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u8 __pad14;
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u8 __pad15;
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u8 ipc;
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u8 __pad16;
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u8 __pad17;
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u8 pvr;
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u8 __pad18;
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u8 pcr;
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u8 ccr4;
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};
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union sab82532_async_regs {
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__volatile__ struct sab82532_async_rd_regs r;
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__volatile__ struct sab82532_async_wr_regs w;
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__volatile__ struct sab82532_async_rw_regs rw;
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};
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#define NR_PORTS 2
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union sab82532_irq_status {
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unsigned short stat;
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struct {
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unsigned char isr0;
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unsigned char isr1;
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} sreg;
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};
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struct sab82532 {
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int magic;
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int baud_base;
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union sab82532_async_regs *regs;
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int irq;
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int flags; /* defined in tty.h */
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int type; /* SAB82532 version */
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struct tty_struct *tty;
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int read_status_mask;
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int ignore_status_mask;
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int timeout;
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int xmit_fifo_size;
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int recv_fifo_size;
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int custom_divisor;
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int baud;
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unsigned int cec_timeout;
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unsigned int tec_timeout;
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int x_char;
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int close_delay;
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unsigned short closing_wait;
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unsigned short closing_wait2;
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unsigned long irqflags;
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int is_console;
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unsigned char interrupt_mask0;
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unsigned char interrupt_mask1;
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unsigned char pvr_dtr_bit;
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unsigned char pvr_dsr_bit;
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unsigned char dcd;
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unsigned char cts;
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unsigned char dsr;
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unsigned long event;
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unsigned long last_active;
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int line;
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int count;
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int blocked_open;
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long session;
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long pgrp;
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struct circ_buf xmit;
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struct tq_struct tqueue;
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struct tq_struct tqueue_hangup;
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struct async_icount icount;
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struct termios normal_termios;
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struct termios callout_termios;
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wait_queue_head_t open_wait;
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wait_queue_head_t close_wait;
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wait_queue_head_t delta_msr_wait;
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struct sab82532 *next;
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struct sab82532 *prev;
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};
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/* irqflags bits */
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#define SAB82532_ALLS 0x00000001
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#define SAB82532_XPR 0x00000002
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/* RFIFO Status Byte */
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#define SAB82532_RSTAT_PE 0x80
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#define SAB82532_RSTAT_FE 0x40
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#define SAB82532_RSTAT_PARITY 0x01
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/* Status Register (STAR) */
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#define SAB82532_STAR_XDOV 0x80
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#define SAB82532_STAR_XFW 0x40
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#define SAB82532_STAR_RFNE 0x20
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#define SAB82532_STAR_FCS 0x10
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#define SAB82532_STAR_TEC 0x08
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#define SAB82532_STAR_CEC 0x04
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#define SAB82532_STAR_CTS 0x02
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/* Command Register (CMDR) */
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#define SAB82532_CMDR_RMC 0x80
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#define SAB82532_CMDR_RRES 0x40
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#define SAB82532_CMDR_RFRD 0x20
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#define SAB82532_CMDR_STI 0x10
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#define SAB82532_CMDR_XF 0x08
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#define SAB82532_CMDR_XRES 0x01
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/* Mode Register (MODE) */
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#define SAB82532_MODE_FRTS 0x40
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#define SAB82532_MODE_FCTS 0x20
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#define SAB82532_MODE_FLON 0x10
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#define SAB82532_MODE_RAC 0x08
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#define SAB82532_MODE_RTS 0x04
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#define SAB82532_MODE_TRS 0x02
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#define SAB82532_MODE_TLP 0x01
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/* Timer Register (TIMR) */
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#define SAB82532_TIMR_CNT_MASK 0xe0
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#define SAB82532_TIMR_VALUE_MASK 0x1f
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/* Data Format (DAFO) */
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#define SAB82532_DAFO_XBRK 0x40
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#define SAB82532_DAFO_STOP 0x20
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#define SAB82532_DAFO_PAR_SPACE 0x00
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#define SAB82532_DAFO_PAR_ODD 0x08
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#define SAB82532_DAFO_PAR_EVEN 0x10
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#define SAB82532_DAFO_PAR_MARK 0x18
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#define SAB82532_DAFO_PARE 0x04
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#define SAB82532_DAFO_CHL8 0x00
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#define SAB82532_DAFO_CHL7 0x01
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#define SAB82532_DAFO_CHL6 0x02
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#define SAB82532_DAFO_CHL5 0x03
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/* RFIFO Control Register (RFC) */
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#define SAB82532_RFC_DPS 0x40
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#define SAB82532_RFC_DXS 0x20
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#define SAB82532_RFC_RFDF 0x10
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#define SAB82532_RFC_RFTH_1 0x00
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#define SAB82532_RFC_RFTH_4 0x04
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#define SAB82532_RFC_RFTH_16 0x08
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#define SAB82532_RFC_RFTH_32 0x0c
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#define SAB82532_RFC_TCDE 0x01
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/* Received Byte Count High (RBCH) */
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#define SAB82532_RBCH_DMA 0x80
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#define SAB82532_RBCH_CAS 0x20
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/* Transmit Byte Count High (XBCH) */
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#define SAB82532_XBCH_DMA 0x80
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#define SAB82532_XBCH_CAS 0x20
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#define SAB82532_XBCH_XC 0x10
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/* Channel Configuration Register 0 (CCR0) */
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#define SAB82532_CCR0_PU 0x80
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#define SAB82532_CCR0_MCE 0x40
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#define SAB82532_CCR0_SC_NRZ 0x00
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#define SAB82532_CCR0_SC_NRZI 0x08
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#define SAB82532_CCR0_SC_FM0 0x10
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#define SAB82532_CCR0_SC_FM1 0x14
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#define SAB82532_CCR0_SC_MANCH 0x18
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#define SAB82532_CCR0_SM_HDLC 0x00
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#define SAB82532_CCR0_SM_SDLC_LOOP 0x01
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#define SAB82532_CCR0_SM_BISYNC 0x02
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#define SAB82532_CCR0_SM_ASYNC 0x03
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/* Channel Configuration Register 1 (CCR1) */
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#define SAB82532_CCR1_ODS 0x10
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#define SAB82532_CCR1_BCR 0x08
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#define SAB82532_CCR1_CM_MASK 0x07
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/* Channel Configuration Register 2 (CCR2) */
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#define SAB82532_CCR2_SOC1 0x80
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#define SAB82532_CCR2_SOC0 0x40
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#define SAB82532_CCR2_BR9 0x80
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#define SAB82532_CCR2_BR8 0x40
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#define SAB82532_CCR2_BDF 0x20
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#define SAB82532_CCR2_SSEL 0x10
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#define SAB82532_CCR2_XCS0 0x20
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#define SAB82532_CCR2_RCS0 0x10
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#define SAB82532_CCR2_TOE 0x08
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#define SAB82532_CCR2_RWX 0x04
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#define SAB82532_CCR2_DIV 0x01
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| 287 |
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/* Channel Configuration Register 3 (CCR3) */
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#define SAB82532_CCR3_PSD 0x01
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| 290 |
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/* Time Slot Assignment Register Transmit (TSAX) */
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#define SAB82532_TSAX_TSNX_MASK 0xfc
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#define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */
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#define SAB82532_TSAX_XCS1 0x01
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| 295 |
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/* Time Slot Assignment Register Receive (TSAR) */
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#define SAB82532_TSAR_TSNR_MASK 0xfc
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#define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */
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#define SAB82532_TSAR_RCS1 0x01
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/* Version Status Register (VSTR) */
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#define SAB82532_VSTR_CD 0x80
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#define SAB82532_VSTR_DPLA 0x40
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#define SAB82532_VSTR_VN_MASK 0x0f
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#define SAB82532_VSTR_VN_1 0x00
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#define SAB82532_VSTR_VN_2 0x01
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#define SAB82532_VSTR_VN_3_2 0x02
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/* Global Interrupt Status Register (GIS) */
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#define SAB82532_GIS_PI 0x80
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#define SAB82532_GIS_ISA1 0x08
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#define SAB82532_GIS_ISA0 0x04
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#define SAB82532_GIS_ISB1 0x02
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#define SAB82532_GIS_ISB0 0x01
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/* Interrupt Vector Address (IVA) */
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#define SAB82532_IVA_MASK 0xf1
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/* Interrupt Port Configuration (IPC) */
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#define SAB82532_IPC_VIS 0x80
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#define SAB82532_IPC_SLA1 0x10
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#define SAB82532_IPC_SLA0 0x08
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| 322 |
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#define SAB82532_IPC_CASM 0x04
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| 323 |
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#define SAB82532_IPC_IC_OPEN_DRAIN 0x00
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| 324 |
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#define SAB82532_IPC_IC_ACT_LOW 0x01
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| 325 |
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#define SAB82532_IPC_IC_ACT_HIGH 0x03
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| 326 |
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| 327 |
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/* Interrupt Status Register 0 (ISR0) */
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| 328 |
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#define SAB82532_ISR0_TCD 0x80
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| 329 |
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#define SAB82532_ISR0_TIME 0x40
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| 330 |
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#define SAB82532_ISR0_PERR 0x20
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| 331 |
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#define SAB82532_ISR0_FERR 0x10
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| 332 |
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#define SAB82532_ISR0_PLLA 0x08
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| 333 |
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#define SAB82532_ISR0_CDSC 0x04
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| 334 |
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#define SAB82532_ISR0_RFO 0x02
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| 335 |
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#define SAB82532_ISR0_RPF 0x01
|
| 336 |
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|
|
| 337 |
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/* Interrupt Status Register 1 (ISR1) */
|
| 338 |
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#define SAB82532_ISR1_BRK 0x80
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| 339 |
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#define SAB82532_ISR1_BRKT 0x40
|
| 340 |
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#define SAB82532_ISR1_ALLS 0x20
|
| 341 |
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#define SAB82532_ISR1_XOFF 0x10
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| 342 |
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#define SAB82532_ISR1_TIN 0x08
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| 343 |
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#define SAB82532_ISR1_CSC 0x04
|
| 344 |
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#define SAB82532_ISR1_XON 0x02
|
| 345 |
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#define SAB82532_ISR1_XPR 0x01
|
| 346 |
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|
|
| 347 |
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/* Interrupt Mask Register 0 (IMR0) */
|
| 348 |
|
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#define SAB82532_IMR0_TCD 0x80
|
| 349 |
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#define SAB82532_IMR0_TIME 0x40
|
| 350 |
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#define SAB82532_IMR0_PERR 0x20
|
| 351 |
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#define SAB82532_IMR0_FERR 0x10
|
| 352 |
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#define SAB82532_IMR0_PLLA 0x08
|
| 353 |
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#define SAB82532_IMR0_CDSC 0x04
|
| 354 |
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#define SAB82532_IMR0_RFO 0x02
|
| 355 |
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#define SAB82532_IMR0_RPF 0x01
|
| 356 |
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|
|
| 357 |
|
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/* Interrupt Mask Register 1 (IMR1) */
|
| 358 |
|
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#define SAB82532_IMR1_BRK 0x80
|
| 359 |
|
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#define SAB82532_IMR1_BRKT 0x40
|
| 360 |
|
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#define SAB82532_IMR1_ALLS 0x20
|
| 361 |
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#define SAB82532_IMR1_XOFF 0x10
|
| 362 |
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#define SAB82532_IMR1_TIN 0x08
|
| 363 |
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#define SAB82532_IMR1_CSC 0x04
|
| 364 |
|
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#define SAB82532_IMR1_XON 0x02
|
| 365 |
|
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#define SAB82532_IMR1_XPR 0x01
|
| 366 |
|
|
|
| 367 |
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/* Port Interrupt Status Register (PIS) */
|
| 368 |
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#define SAB82532_PIS_SYNC_B 0x08
|
| 369 |
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#define SAB82532_PIS_DTR_B 0x04
|
| 370 |
|
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#define SAB82532_PIS_DTR_A 0x02
|
| 371 |
|
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#define SAB82532_PIS_SYNC_A 0x01
|
| 372 |
|
|
|
| 373 |
|
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/* Channel Configuration Register 4 (CCR4) */
|
| 374 |
|
|
#define SAB82532_CCR4_MCK4 0x80
|
| 375 |
|
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#define SAB82532_CCR4_EBRG 0x40
|
| 376 |
|
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#define SAB82532_CCR4_TST1 0x20
|
| 377 |
|
|
#define SAB82532_CCR4_ICD 0x10
|
| 378 |
|
|
|
| 379 |
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|
|
| 380 |
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#endif /* !(_SPARC64_SAB82532_H) */
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