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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [include/] [asm-sparc64/] [system.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 1276 phoenix
/* $Id: system.h,v 1.1.1.1 2004-04-15 03:01:07 phoenix Exp $ */
2
#ifndef __SPARC64_SYSTEM_H
3
#define __SPARC64_SYSTEM_H
4
 
5
#include <linux/config.h>
6
#include <asm/ptrace.h>
7
#include <asm/processor.h>
8
#include <asm/asm_offsets.h>
9
#include <asm/visasm.h>
10
 
11
#ifndef __ASSEMBLY__
12
/*
13
 * Sparc (general) CPU types
14
 */
15
enum sparc_cpu {
16
  sun4        = 0x00,
17
  sun4c       = 0x01,
18
  sun4m       = 0x02,
19
  sun4d       = 0x03,
20
  sun4e       = 0x04,
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  sun4u       = 0x05, /* V8 ploos ploos */
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  sun_unknown = 0x06,
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  ap1000      = 0x07, /* almost a sun4m */
24
};
25
 
26
#define sparc_cpu_model sun4u
27
 
28
/* This cannot ever be a sun4c nor sun4 :) That's just history. */
29
#define ARCH_SUN4C_SUN4 0
30
#define ARCH_SUN4 0
31
 
32
#endif
33
 
34
#define setipl(__new_ipl) \
35
        __asm__ __volatile__("wrpr      %0, %%pil"  : : "r" (__new_ipl) : "memory")
36
 
37
#define __cli() \
38
        __asm__ __volatile__("wrpr      15, %%pil" : : : "memory")
39
 
40
#define __sti() \
41
        __asm__ __volatile__("wrpr      0, %%pil" : : : "memory")
42
 
43
#define getipl() \
44
({ unsigned long retval; __asm__ __volatile__("rdpr     %%pil, %0" : "=r" (retval)); retval; })
45
 
46
#define swap_pil(__new_pil) \
47
({      unsigned long retval; \
48
        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
49
                             "wrpr      %1, %%pil" \
50
                             : "=&r" (retval) \
51
                             : "r" (__new_pil) \
52
                             : "memory"); \
53
        retval; \
54
})
55
 
56
#define read_pil_and_cli() \
57
({      unsigned long retval; \
58
        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
59
                             "wrpr      15, %%pil" \
60
                             : "=r" (retval) \
61
                             : : "memory"); \
62
        retval; \
63
})
64
 
65
#define read_pil_and_sti() \
66
({      unsigned long retval; \
67
        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
68
                             "wrpr      0, %%pil" \
69
                             : "=r" (retval) \
70
                             : : "memory"); \
71
        retval; \
72
})
73
 
74
#define __save_flags(flags)             ((flags) = getipl())
75
#define __save_and_cli(flags)           ((flags) = read_pil_and_cli())
76
#define __save_and_sti(flags)           ((flags) = read_pil_and_sti())
77
#define __restore_flags(flags)          setipl((flags))
78
#define local_irq_disable()             __cli()
79
#define local_irq_enable()              __sti()
80
#define local_irq_save(flags)           __save_and_cli(flags)
81
#define local_irq_set(flags)            __save_and_sti(flags)
82
#define local_irq_restore(flags)        __restore_flags(flags)
83
 
84
#ifndef CONFIG_SMP
85
#define cli() __cli()
86
#define sti() __sti()
87
#define save_flags(x) __save_flags(x)
88
#define restore_flags(x) __restore_flags(x)
89
#define save_and_cli(x) __save_and_cli(x)
90
#else
91
 
92
#ifndef __ASSEMBLY__
93
extern void __global_cli(void);
94
extern void __global_sti(void);
95
extern unsigned long __global_save_flags(void);
96
extern void __global_restore_flags(unsigned long flags);
97
#endif
98
 
99
#define cli()                   __global_cli()
100
#define sti()                   __global_sti()
101
#define save_flags(x)           ((x) = __global_save_flags())
102
#define restore_flags(flags)    __global_restore_flags(flags)
103
#define save_and_cli(flags)     do { save_flags(flags); cli(); } while(0)
104
 
105
#endif
106
 
107
#define nop()           __asm__ __volatile__ ("nop")
108
 
109
#define membar(type)    __asm__ __volatile__ ("membar " type : : : "memory");
110
#define mb()            \
111
        membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad");
112
#define rmb()           membar("#LoadLoad")
113
#define wmb()           membar("#StoreStore")
114
#define set_mb(__var, __value) \
115
        do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0)
116
#define set_wmb(__var, __value) \
117
        do { __var = __value; membar("#StoreStore"); } while(0)
118
 
119
#ifdef CONFIG_SMP
120
#define smp_mb()        mb()
121
#define smp_rmb()       rmb()
122
#define smp_wmb()       wmb()
123
#else
124
#define smp_mb()        __asm__ __volatile__("":::"memory");
125
#define smp_rmb()       __asm__ __volatile__("":::"memory");
126
#define smp_wmb()       __asm__ __volatile__("":::"memory");
127
#endif
128
 
129
#define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
130
 
131
#define flushw_all()    __asm__ __volatile__("flushw")
132
 
133
/* Performance counter register access. */
134
#define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
135
#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p));
136
#define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
137
 
138
/* Blackbird errata workaround.  See commentary in
139
 * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
140
 * for more information.
141
 */
142
#define reset_pic()                                             \
143
        __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
144
                             ".align    64\n"                   \
145
                          "99:wr        %g0, 0x0, %pic\n\t"     \
146
                             "rd        %pic, %g0")
147
 
148
#ifndef __ASSEMBLY__
149
 
150
extern void synchronize_user_stack(void);
151
 
152
extern void __flushw_user(void);
153
#define flushw_user() __flushw_user()
154
 
155
#define flush_user_windows flushw_user
156
#define flush_register_windows flushw_all
157
#define prepare_to_switch flushw_all
158
 
159
#ifndef CONFIG_DEBUG_SPINLOCK
160
#define CHECK_LOCKS(PREV)       do { } while(0)
161
#else /* CONFIG_DEBUG_SPINLOCK */
162
#define CHECK_LOCKS(PREV)                                               \
163
if ((PREV)->thread.smp_lock_count) {                                    \
164
        unsigned long rpc;                                              \
165
        __asm__ __volatile__("mov %%i7, %0" : "=r" (rpc));              \
166
        printk(KERN_CRIT "(%s)[%d]: Sleeping with %d locks held!\n",    \
167
               (PREV)->comm, (PREV)->pid,                               \
168
               (PREV)->thread.smp_lock_count);                          \
169
        printk(KERN_CRIT "(%s)[%d]: Last lock at %08x\n",               \
170
               (PREV)->comm, (PREV)->pid,                               \
171
               (PREV)->thread.smp_lock_pc);                             \
172
        printk(KERN_CRIT "(%s)[%d]: Sched caller %016lx\n",             \
173
               (PREV)->comm, (PREV)->pid, rpc);                         \
174
}
175
#endif /* !(CONFIG_DEBUG_SPINLOCK) */
176
 
177
        /* See what happens when you design the chip correctly?
178
         *
179
         * We tell gcc we clobber all non-fixed-usage registers except
180
         * for l0/l1.  It will use one for 'next' and the other to hold
181
         * the output value of 'last'.  'next' is not referenced again
182
         * past the invocation of switch_to in the scheduler, so we need
183
         * not preserve it's value.  Hairy, but it lets us remove 2 loads
184
         * and 2 stores in this critical code path.  -DaveM
185
         */
186
#define switch_to(prev, next, last)                                             \
187
do {    CHECK_LOCKS(prev);                                                      \
188
        if (current->thread.flags & SPARC_FLAG_PERFCTR) {                       \
189
                unsigned long __tmp;                                            \
190
                read_pcr(__tmp);                                                \
191
                current->thread.pcr_reg = __tmp;                                \
192
                read_pic(__tmp);                                                \
193
                current->thread.kernel_cntd0 += (unsigned int)(__tmp);          \
194
                current->thread.kernel_cntd1 += ((__tmp) >> 32);                \
195
        }                                                                       \
196
        save_and_clear_fpu();                                                   \
197
        /* If you are tempted to conditionalize the following */                \
198
        /* so that ASI is only written if it changes, think again. */           \
199
        __asm__ __volatile__("wr %%g0, %0, %%asi"                               \
200
                             : : "r" (next->thread.current_ds.seg));            \
201
        __asm__ __volatile__(                                                   \
202
        "mov    %%g6, %%g5\n\t"                                                 \
203
        "wrpr   %%g0, 0x95, %%pstate\n\t"                                       \
204
        "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                                 \
205
        "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                                 \
206
        "rdpr   %%wstate, %%o5\n\t"                                             \
207
        "stx    %%o6, [%%g6 + %3]\n\t"                                          \
208
        "stb    %%o5, [%%g6 + %2]\n\t"                                          \
209
        "rdpr   %%cwp, %%o5\n\t"                                                \
210
        "stb    %%o5, [%%g6 + %5]\n\t"                                          \
211
        "mov    %1, %%g6\n\t"                                                   \
212
        "ldub   [%1 + %5], %%g1\n\t"                                            \
213
        "wrpr   %%g1, %%cwp\n\t"                                                \
214
        "ldx    [%%g6 + %3], %%o6\n\t"                                          \
215
        "ldub   [%%g6 + %2], %%o5\n\t"                                          \
216
        "ldub   [%%g6 + %4], %%o7\n\t"                                          \
217
        "mov    %%g6, %%l2\n\t"                                                 \
218
        "wrpr   %%o5, 0x0, %%wstate\n\t"                                        \
219
        "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                                 \
220
        "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                                 \
221
        "wrpr   %%g0, 0x94, %%pstate\n\t"                                       \
222
        "mov    %%l2, %%g6\n\t"                                                 \
223
        "wrpr   %%g0, 0x96, %%pstate\n\t"                                       \
224
        "andcc  %%o7, %6, %%g0\n\t"                                             \
225
        "bne,pn %%icc, ret_from_syscall\n\t"                                    \
226
        " mov   %%g5, %0\n\t"                                                   \
227
        : "=&r" (last)                                                          \
228
        : "r" (next),                                                           \
229
          "i" ((const unsigned long)(&((struct task_struct *)0)->thread.wstate)),\
230
          "i" ((const unsigned long)(&((struct task_struct *)0)->thread.ksp)),   \
231
          "i" ((const unsigned long)(&((struct task_struct *)0)->thread.flags)),\
232
          "i" ((const unsigned long)(&((struct task_struct *)0)->thread.cwp)),   \
233
          "i" (SPARC_FLAG_NEWCHILD)                                             \
234
        : "cc",                                                                 \
235
                "g1", "g2", "g3",       "g5",       "g7",                       \
236
                      "l2", "l3", "l4", "l5", "l6", "l7",                       \
237
          "i0", "i1", "i2", "i3", "i4", "i5",                                   \
238
          "o0", "o1", "o2", "o3", "o4", "o5",       "o7");                      \
239
        /* If you fuck with this, update ret_from_syscall code too. */          \
240
        if (current->thread.flags & SPARC_FLAG_PERFCTR) {                       \
241
                write_pcr(current->thread.pcr_reg);                             \
242
                reset_pic();                                                    \
243
        }                                                                       \
244
} while(0)
245
 
246
extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
247
{
248
        __asm__ __volatile__(
249
"       mov             %0, %%g5\n"
250
"1:     lduw            [%2], %%g7\n"
251
"       cas             [%2], %%g7, %0\n"
252
"       cmp             %%g7, %0\n"
253
"       bne,a,pn        %%icc, 1b\n"
254
"        mov            %%g5, %0\n"
255
"       membar          #StoreLoad | #StoreStore\n"
256
        : "=&r" (val)
257
        : "0" (val), "r" (m)
258
        : "g5", "g7", "cc", "memory");
259
        return val;
260
}
261
 
262
extern __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
263
{
264
        __asm__ __volatile__(
265
"       mov             %0, %%g5\n"
266
"1:     ldx             [%2], %%g7\n"
267
"       casx            [%2], %%g7, %0\n"
268
"       cmp             %%g7, %0\n"
269
"       bne,a,pn        %%xcc, 1b\n"
270
"        mov            %%g5, %0\n"
271
"       membar          #StoreLoad | #StoreStore\n"
272
        : "=&r" (val)
273
        : "0" (val), "r" (m)
274
        : "g5", "g7", "cc", "memory");
275
        return val;
276
}
277
 
278
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
279
#define tas(ptr) (xchg((ptr),1))
280
 
281
extern void __xchg_called_with_bad_pointer(void);
282
 
283
static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
284
                                       int size)
285
{
286
        switch (size) {
287
        case 4:
288
                return xchg32(ptr, x);
289
        case 8:
290
                return xchg64(ptr, x);
291
        };
292
        __xchg_called_with_bad_pointer();
293
        return x;
294
}
295
 
296
extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
297
 
298
/*
299
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
300
 * store NEW in MEM.  Return the initial value in MEM.  Success is
301
 * indicated by comparing RETURN with OLD.
302
 */
303
 
304
#define __HAVE_ARCH_CMPXCHG 1
305
 
306
extern __inline__ unsigned long
307
__cmpxchg_u32(volatile int *m, int old, int new)
308
{
309
        __asm__ __volatile__("cas [%2], %3, %0\n\t"
310
                             "membar #StoreLoad | #StoreStore"
311
                             : "=&r" (new)
312
                             : "0" (new), "r" (m), "r" (old)
313
                             : "memory");
314
 
315
        return new;
316
}
317
 
318
extern __inline__ unsigned long
319
__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
320
{
321
        __asm__ __volatile__("casx [%2], %3, %0\n\t"
322
                             "membar #StoreLoad | #StoreStore"
323
                             : "=&r" (new)
324
                             : "0" (new), "r" (m), "r" (old)
325
                             : "memory");
326
 
327
        return new;
328
}
329
 
330
/* This function doesn't exist, so you'll get a linker error
331
   if something tries to do an invalid cmpxchg().  */
332
extern void __cmpxchg_called_with_bad_pointer(void);
333
 
334
static __inline__ unsigned long
335
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
336
{
337
        switch (size) {
338
                case 4:
339
                        return __cmpxchg_u32(ptr, old, new);
340
                case 8:
341
                        return __cmpxchg_u64(ptr, old, new);
342
        }
343
        __cmpxchg_called_with_bad_pointer();
344
        return old;
345
}
346
 
347
#define cmpxchg(ptr,o,n)                                                 \
348
  ({                                                                     \
349
     __typeof__(*(ptr)) _o_ = (o);                                       \
350
     __typeof__(*(ptr)) _n_ = (n);                                       \
351
     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
352
                                    (unsigned long)_n_, sizeof(*(ptr))); \
353
  })
354
 
355
#endif /* !(__ASSEMBLY__) */
356
 
357
#endif /* !(__SPARC64_SYSTEM_H) */

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