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1325 |
phoenix |
/* This file is lisenced under LGPL.
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* Copyright (C) 2002-2003, George Thanos <george.thanos@gdt.gr>
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* Yannis Mitsos <yannis.mitsos@gdt.gr>
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*/
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#ifndef _BITS_UNISTD_H_
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#define _BITS_UNISTD_H_
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#include <bits/proto.h>
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#include <errno.h>
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#define __E1_COFF_GCC__
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/* The following macros have been provided by C.Baumhof
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* They can be inlined in contrast to the previous ones*/
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#define _syscall0(type, name) \
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type name(void) \
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{ \
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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par1 = -1; \
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par2 = __NR_##name; \
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__asm__ __volatile__( \
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"trap 47" \
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:"=l"(par1) \
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:"0"(par1), "l"(par2) \
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:"memory","L14","L15"); \
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\
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if( par1 < 0 ) { \
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__set_errno( -par1 ); \
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return -1; \
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} else \
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return (type)(par1); \
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}
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#define _syscall1(type, name,atype, a) \
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type name(atype a) \
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{ \
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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register int par3 __asm__("L13"); \
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par1 = -1; \
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par2 = __NR_##name; \
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par3 = (int)a; \
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__asm__ __volatile__( \
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"trap 47" \
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:"=l"(par1) \
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:"0"(par1), "l"(par2), "l"(par3) \
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:"memory","L13","L14","L15"); \
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\
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if( par1 < 0 ) { \
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__set_errno( -par1 ); \
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return -1; \
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} else \
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return (type)(par1); \
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}
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#define _syscall2(type, name,atype, a, btype, b) \
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type name(atype a, btype b) \
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{ \
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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register int par3 __asm__("L13"); \
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register int par4 __asm__("L12"); \
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par1 = -1; \
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par2 = __NR_##name; \
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par3 = (int)a; \
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par4 = (int)b; \
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__asm__ __volatile__( \
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"trap 47" \
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:"=l"(par1) \
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:"0"(par1), "l"(par2), "l"(par3), "l"(par4) \
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:"memory","L12","L13","L14","L15"); \
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\
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if( par1 < 0 ) { \
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__set_errno( -par1 ); \
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return -1; \
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} else \
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return (type)(par1); \
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}
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#define _syscall3(type, name,atype, a, btype, b, ctype, c) \
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type name(atype a, btype b, ctype c) \
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{ \
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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register int par3 __asm__("L13"); \
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register int par4 __asm__("L12"); \
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register int par5 __asm__("L11"); \
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par1 = -1; \
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par2 = __NR_##name; \
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par3 = (int)a; \
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par4 = (int)b; \
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par5 = (int)c; \
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__asm__ __volatile__( \
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"trap 47" \
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:"=l"(par1) \
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:"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
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:"memory","L11","L12","L13","L14","L15"); \
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\
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if( par1 < 0 ) { \
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__set_errno( -par1 ); \
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return -1; \
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} else \
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return (type)(par1); \
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}
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#define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
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type name(atype a, btype b, ctype c,dtype d) \
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{ \
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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register int par3 __asm__("L13"); \
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register int par4 __asm__("L12"); \
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register int par5 __asm__("L11"); \
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register int par6 __asm__("L10"); \
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par1 = -1; \
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par2 = __NR_##name; \
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par3 = (int)a; \
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par4 = (int)b; \
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par5 = (int)c; \
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par6 = (int)d; \
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__asm__ __volatile__( \
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"trap 47" \
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:"=l"(par1) \
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:"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
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:"memory","L10","L11","L12","L13","L14","L15"); \
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\
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if( par1 < 0 ) { \
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__set_errno( -par1 ); \
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return -1; \
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} else \
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return (type)(par1); \
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}
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#define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
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type name(atype a, btype b, ctype c,dtype d, etype e) \
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{ \
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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register int par3 __asm__("L13"); \
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register int par4 __asm__("L12"); \
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register int par5 __asm__("L11"); \
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register int par6 __asm__("L10"); \
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register int par7 __asm__("L9"); \
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par1 = -1; \
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par2 = __NR_##name; \
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par3 = (int)a; \
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par4 = (int)b; \
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par5 = (int)c; \
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par6 = (int)d; \
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par7 = (int)e; \
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__asm__ __volatile__( \
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"trap 47" \
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:"=l"(par1) \
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:"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
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:"memory","L9","L10","L11","L12","L13","L14","L15"); \
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\
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if( par1 < 0 ) { \
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__set_errno( -par1 ); \
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return -1; \
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} else \
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return (type)(par1); \
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return (type)(par1); \
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}
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| 166 |
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#define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
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type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
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{ \
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| 169 |
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register int par1 __asm__("L15"); \
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register int par2 __asm__("L14"); \
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register int par3 __asm__("L13"); \
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register int par4 __asm__("L12"); \
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register int par5 __asm__("L11"); \
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register int par6 __asm__("L10"); \
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register int par7 __asm__("L9"); \
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| 176 |
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register int par8 __asm__("L8"); \
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int sys_retval; \
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par1 = -1; \
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par2 = __NR_##name; \
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par3 = (int)a; \
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par4 = (int)b; \
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| 182 |
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par5 = (int)c; \
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| 183 |
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par6 = (int)d; \
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| 184 |
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par7 = (int)e; \
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| 185 |
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par7 = (int)f; \
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| 186 |
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__asm__ __volatile__( \
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| 187 |
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"trap 47" \
|
| 188 |
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:"=l"(par1) \
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| 189 |
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:"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
|
| 190 |
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:"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
|
| 191 |
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\
|
| 192 |
|
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if( par1 < 0 ) { \
|
| 193 |
|
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__set_errno( -par1 ); \
|
| 194 |
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return -1; \
|
| 195 |
|
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} else \
|
| 196 |
|
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return (type)(par1); \
|
| 197 |
|
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}
|
| 198 |
|
|
|
| 199 |
|
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#define __syscall0(type, name) \
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| 200 |
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type name(...) \
|
| 201 |
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{ \
|
| 202 |
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register int par1 __asm__("L15"); \
|
| 203 |
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register int par2 __asm__("L14"); \
|
| 204 |
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par1 = -1; \
|
| 205 |
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par2 = __NR_##name; \
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| 206 |
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__asm__ __volatile__( \
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| 207 |
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"trap 47" \
|
| 208 |
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:"=l"(par1) \
|
| 209 |
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:"0"(par1), "l"(par2)\
|
| 210 |
|
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:"memory","L14","L15"); \
|
| 211 |
|
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\
|
| 212 |
|
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if( par1 < 0 ) { \
|
| 213 |
|
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__set_errno( -par1 ); \
|
| 214 |
|
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return -1; \
|
| 215 |
|
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} else \
|
| 216 |
|
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return (type)(par1); \
|
| 217 |
|
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}
|
| 218 |
|
|
|
| 219 |
|
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#define __syscall1(type, name, atype, a) \
|
| 220 |
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type name(atype a, ...) \
|
| 221 |
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{ \
|
| 222 |
|
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register int par1 __asm__("L15"); \
|
| 223 |
|
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register int par2 __asm__("L14"); \
|
| 224 |
|
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register int par3 __asm__("L13"); \
|
| 225 |
|
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par1 = -1; \
|
| 226 |
|
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par2 = __NR_##name; \
|
| 227 |
|
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par3 = (int)a; \
|
| 228 |
|
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__asm__ __volatile__( \
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| 229 |
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"trap 47" \
|
| 230 |
|
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:"=l"(par1) \
|
| 231 |
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:"0"(par1), "l"(par2), "l"(par3)\
|
| 232 |
|
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:"memory","L13","L14","L15"); \
|
| 233 |
|
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\
|
| 234 |
|
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if( par1 < 0 ) { \
|
| 235 |
|
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__set_errno( -par1 ); \
|
| 236 |
|
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return -1; \
|
| 237 |
|
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} else \
|
| 238 |
|
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return (type)(par1); \
|
| 239 |
|
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}
|
| 240 |
|
|
|
| 241 |
|
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#define __syscall2(type, name,atype, a, btype, b) \
|
| 242 |
|
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type name(atype a, btype b, ...) \
|
| 243 |
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{ \
|
| 244 |
|
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register int par1 __asm__("L15"); \
|
| 245 |
|
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register int par2 __asm__("L14"); \
|
| 246 |
|
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register int par3 __asm__("L13"); \
|
| 247 |
|
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register int par4 __asm__("L12"); \
|
| 248 |
|
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par1 = -1; \
|
| 249 |
|
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par2 = __NR_##name; \
|
| 250 |
|
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par3 = (int)a; \
|
| 251 |
|
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par4 = (int)b; \
|
| 252 |
|
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__asm__ __volatile__( \
|
| 253 |
|
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"trap 47" \
|
| 254 |
|
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:"=l"(par1) \
|
| 255 |
|
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:"0"(par1), "l"(par2), "l"(par3), "l"(par4)\
|
| 256 |
|
|
:"memory","L12","L13","L14","L15"); \
|
| 257 |
|
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\
|
| 258 |
|
|
if( par1 < 0 ) { \
|
| 259 |
|
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__set_errno( -par1 ); \
|
| 260 |
|
|
return -1; \
|
| 261 |
|
|
} else \
|
| 262 |
|
|
return (type)(par1); \
|
| 263 |
|
|
}
|
| 264 |
|
|
|
| 265 |
|
|
#define __syscall3(type, name,atype, a, btype, b, ctype, c) \
|
| 266 |
|
|
type name(atype a, btype b, ctype c, ...) \
|
| 267 |
|
|
{ \
|
| 268 |
|
|
register int par1 __asm__("L15"); \
|
| 269 |
|
|
register int par2 __asm__("L14"); \
|
| 270 |
|
|
register int par3 __asm__("L13"); \
|
| 271 |
|
|
register int par4 __asm__("L12"); \
|
| 272 |
|
|
register int par5 __asm__("L11"); \
|
| 273 |
|
|
par1 = -1; \
|
| 274 |
|
|
par2 = __NR_##name; \
|
| 275 |
|
|
par3 = (int)a; \
|
| 276 |
|
|
par4 = (int)b; \
|
| 277 |
|
|
par5 = (int)c; \
|
| 278 |
|
|
__asm__ __volatile__( \
|
| 279 |
|
|
"trap 47" \
|
| 280 |
|
|
:"=l"(par1) \
|
| 281 |
|
|
:"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
|
| 282 |
|
|
:"memory","L11","L12","L13","L14","L15"); \
|
| 283 |
|
|
\
|
| 284 |
|
|
if( par1 < 0 ) { \
|
| 285 |
|
|
__set_errno( -par1 ); \
|
| 286 |
|
|
return -1; \
|
| 287 |
|
|
} else \
|
| 288 |
|
|
return (type)(par1); \
|
| 289 |
|
|
}
|
| 290 |
|
|
|
| 291 |
|
|
#define __syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
|
| 292 |
|
|
type name(atype a, btype b, ctype c,dtype d, ...) \
|
| 293 |
|
|
{ \
|
| 294 |
|
|
register int par1 __asm__("L15"); \
|
| 295 |
|
|
register int par2 __asm__("L14"); \
|
| 296 |
|
|
register int par3 __asm__("L13"); \
|
| 297 |
|
|
register int par4 __asm__("L12"); \
|
| 298 |
|
|
register int par5 __asm__("L11"); \
|
| 299 |
|
|
register int par6 __asm__("L10"); \
|
| 300 |
|
|
par1 = -1; \
|
| 301 |
|
|
par2 = __NR_##name; \
|
| 302 |
|
|
par3 = (int)a; \
|
| 303 |
|
|
par4 = (int)b; \
|
| 304 |
|
|
par5 = (int)c; \
|
| 305 |
|
|
par6 = (int)d; \
|
| 306 |
|
|
__asm__ __volatile__( \
|
| 307 |
|
|
"trap 47" \
|
| 308 |
|
|
:"=l"(par1) \
|
| 309 |
|
|
:"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
|
| 310 |
|
|
:"memory","L10","L11","L12","L13","L14","L15"); \
|
| 311 |
|
|
\
|
| 312 |
|
|
if( par1 < 0 ) { \
|
| 313 |
|
|
__set_errno( -par1 ); \
|
| 314 |
|
|
return -1; \
|
| 315 |
|
|
} else \
|
| 316 |
|
|
return (type)(par1); \
|
| 317 |
|
|
}
|
| 318 |
|
|
|
| 319 |
|
|
#define __syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
|
| 320 |
|
|
type name(atype a, btype b, ctype c,dtype d, etype e, ...) \
|
| 321 |
|
|
{ \
|
| 322 |
|
|
register int par1 __asm__("L15"); \
|
| 323 |
|
|
register int par2 __asm__("L14"); \
|
| 324 |
|
|
register int par3 __asm__("L13"); \
|
| 325 |
|
|
register int par4 __asm__("L12"); \
|
| 326 |
|
|
register int par5 __asm__("L11"); \
|
| 327 |
|
|
register int par6 __asm__("L10"); \
|
| 328 |
|
|
register int par7 __asm__("L9"); \
|
| 329 |
|
|
par1 = -1; \
|
| 330 |
|
|
par2 = __NR_##name; \
|
| 331 |
|
|
par3 = (int)a; \
|
| 332 |
|
|
par4 = (int)b; \
|
| 333 |
|
|
par5 = (int)c; \
|
| 334 |
|
|
par6 = (int)d; \
|
| 335 |
|
|
par7 = (int)e; \
|
| 336 |
|
|
__asm__ __volatile__( \
|
| 337 |
|
|
"trap 47" \
|
| 338 |
|
|
:"=l"(par1) \
|
| 339 |
|
|
:"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
|
| 340 |
|
|
:"memory","L9","L10","L11","L12","L13","L14","L15"); \
|
| 341 |
|
|
\
|
| 342 |
|
|
if( par1 < 0 ) { \
|
| 343 |
|
|
__set_errno( -par1 ); \
|
| 344 |
|
|
return -1; \
|
| 345 |
|
|
} else \
|
| 346 |
|
|
return (type)(par1); \
|
| 347 |
|
|
}
|
| 348 |
|
|
|
| 349 |
|
|
#define __syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
|
| 350 |
|
|
type name(atype a, btype b, ctype c,dtype d, etype e, ftype f, ...) \
|
| 351 |
|
|
{ \
|
| 352 |
|
|
register int par1 __asm__("L15"); \
|
| 353 |
|
|
register int par2 __asm__("L14"); \
|
| 354 |
|
|
register int par3 __asm__("L13"); \
|
| 355 |
|
|
register int par4 __asm__("L12"); \
|
| 356 |
|
|
register int par5 __asm__("L11"); \
|
| 357 |
|
|
register int par6 __asm__("L10"); \
|
| 358 |
|
|
register int par7 __asm__("L9"); \
|
| 359 |
|
|
register int par8 __asm__("L8"); \
|
| 360 |
|
|
par1 = -1; \
|
| 361 |
|
|
par2 = __NR_##name; \
|
| 362 |
|
|
par3 = (int)a; \
|
| 363 |
|
|
par4 = (int)b; \
|
| 364 |
|
|
par5 = (int)c; \
|
| 365 |
|
|
par6 = (int)d; \
|
| 366 |
|
|
par7 = (int)e; \
|
| 367 |
|
|
par7 = (int)f; \
|
| 368 |
|
|
__asm__ __volatile__( \
|
| 369 |
|
|
"trap 47" \
|
| 370 |
|
|
:"=l"(par1) \
|
| 371 |
|
|
:"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
|
| 372 |
|
|
:"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
|
| 373 |
|
|
\
|
| 374 |
|
|
if( par1 < 0 ) { \
|
| 375 |
|
|
__set_errno( -par1 ); \
|
| 376 |
|
|
return -1; \
|
| 377 |
|
|
} else \
|
| 378 |
|
|
return (type)(par1); \
|
| 379 |
|
|
}
|
| 380 |
|
|
|
| 381 |
|
|
#include <sys/types.h>
|
| 382 |
|
|
/* Taken from <bits/errno.h> */
|
| 383 |
|
|
#ifndef _LIBC
|
| 384 |
|
|
/* We don't support pthreads for the moment*/
|
| 385 |
|
|
#define __set_errno(val) ((errno) = (val))
|
| 386 |
|
|
#endif
|
| 387 |
|
|
|
| 388 |
|
|
#if 0
|
| 389 |
|
|
#define _syscall3(type, name,atype, a , btype, b, ctype, c) \
|
| 390 |
|
|
type name(atype a, btype b, ctype c,) \
|
| 391 |
|
|
{ \
|
| 392 |
|
|
__asm__ __volatile__( \
|
| 393 |
|
|
"movi L9, -1\n\t" \
|
| 394 |
|
|
"movi L8, %0\n\t" \
|
| 395 |
|
|
"ldw.d G3, L7, 0\n\t" \
|
| 396 |
|
|
"ldw.d G3, L6, 4\n\t" \
|
| 397 |
|
|
"ldw.d G3, L5, 8\n\t" \
|
| 398 |
|
|
:/* no output */ \
|
| 399 |
|
|
:"i"(__NR_##name) \
|
| 400 |
|
|
:"cc","memory","%L5","L6","L7","L8","L9");\
|
| 401 |
|
|
__asm__ __volatile__( \
|
| 402 |
|
|
"trap 47\n\t" \
|
| 403 |
|
|
"mov L2, L9\n\t"); \
|
| 404 |
|
|
}
|
| 405 |
|
|
|
| 406 |
|
|
#define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
|
| 407 |
|
|
type name(atype a, btype b, ctype c,dtype d) \
|
| 408 |
|
|
{ \
|
| 409 |
|
|
__asm__ __volatile__( \
|
| 410 |
|
|
"movi L11, -1\n\t" \
|
| 411 |
|
|
"movi L10, %0\n\t" \
|
| 412 |
|
|
"ldw.d G3, L9, 0\n\t" \
|
| 413 |
|
|
"ldw.d G3, L8, 4\n\t" \
|
| 414 |
|
|
"ldw.d G3, L7, 8\n\t" \
|
| 415 |
|
|
"ldw.d G3, L6, 12\n\t" \
|
| 416 |
|
|
:/* no output */ \
|
| 417 |
|
|
:"i"(__NR_##name) \
|
| 418 |
|
|
:"cc","memory","L6","L7","L8","L9","L10","L11");\
|
| 419 |
|
|
__asm__ __volatile__( \
|
| 420 |
|
|
"trap 47\n\t" \
|
| 421 |
|
|
"mov L2, L11\n\t"); \
|
| 422 |
|
|
}
|
| 423 |
|
|
|
| 424 |
|
|
#define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
|
| 425 |
|
|
type name(atype a, btype b, ctype c,dtype d, etype e) \
|
| 426 |
|
|
{ \
|
| 427 |
|
|
__asm__ __volatile__( \
|
| 428 |
|
|
"movi L13, -1\n\t" \
|
| 429 |
|
|
"movi L12, %0\n\t" \
|
| 430 |
|
|
"ldw.d G3, L11, 0\n\t" \
|
| 431 |
|
|
"ldw.d G3, L10, 4\n\t" \
|
| 432 |
|
|
"ldw.d G3, L9, 8\n\t" \
|
| 433 |
|
|
"ldw.d G3, L8, 12\n\t" \
|
| 434 |
|
|
"ldw.d G3, L7, 16\n\t" \
|
| 435 |
|
|
:/* no output */ \
|
| 436 |
|
|
:"i"(__NR_##name) \
|
| 437 |
|
|
:"cc","memory","L7","L8","L9","L10","L11","L12","L13");\
|
| 438 |
|
|
__asm__ __volatile__( \
|
| 439 |
|
|
"trap 47\n\t" \
|
| 440 |
|
|
"mov L2, L13\n\t"); \
|
| 441 |
|
|
}
|
| 442 |
|
|
|
| 443 |
|
|
#define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
|
| 444 |
|
|
type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
|
| 445 |
|
|
{ \
|
| 446 |
|
|
__asm__ __volatile__( \
|
| 447 |
|
|
"movi L15, -1\n\t" \
|
| 448 |
|
|
"movi L14, %0\n\t" \
|
| 449 |
|
|
"ldw.d G3, L13, 0\n\t" \
|
| 450 |
|
|
"ldw.d G3, L12, 4\n\t" \
|
| 451 |
|
|
"ldw.d G3, L11, 8\n\t" \
|
| 452 |
|
|
"ldw.d G3, L10, 12\n\t" \
|
| 453 |
|
|
"ldw.d G3, L9, 16\n\t" \
|
| 454 |
|
|
"ldw.d G3, L8, 20\n\t" \
|
| 455 |
|
|
:/* no output */ \
|
| 456 |
|
|
:"i"(__NR_##name) \
|
| 457 |
|
|
:"cc","memory","L8","L9","L10","L11","L12","L13","L14","L15");\
|
| 458 |
|
|
__asm__ __volatile__( \
|
| 459 |
|
|
"trap 47\n\t" \
|
| 460 |
|
|
"mov L2, L15\n\t"); \
|
| 461 |
|
|
}
|
| 462 |
|
|
#endif
|
| 463 |
|
|
|
| 464 |
|
|
#endif /* !_HYPERSTONE_NOMMU_UNISTD_H_ */
|
