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[/] [or1k/] [trunk/] [mp3/] [bench/] [verilog/] [dbg_if_model.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_if_model.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC test bench.               ////
////  http://www.opencores.org/                                   ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Damjan Lampret                                         ////
////       lampret@opencores.org                                  ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/14 06:19:35  lampret
// Added debug model for testing du. Updated or1200_monitor.
//
//
//
 
`include "dbg_defines.v"
 
// Top module
module dbg_if_model(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
 
                // Boundary Scan signals
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i,
 
                // RISC signals
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
 
 
              );
 
parameter Tp = 1;
 
// JTAG pins
input         tms_pad_i;                  // JTAG test mode select pad
input         tck_pad_i;                  // JTAG test clock pad
input         trst_pad_i;                 // JTAG test reset pad
input         tdi_pad_i;                  // JTAG test data input pad
output        tdo_pad_o;                  // JTAG test data output pad
 
 
// Boundary Scan signals
output capture_dr_o;
output shift_dr_o;
output update_dr_o;
output extest_selected_o;
input  bs_chain_i;
 
 
// RISC signals
input         risc_clk_i;                 // Master clock (RISC clock)
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
input  [10:0] wp_i;                       // Watchpoint inputs
input         bp_i;                       // Breakpoint input
input  [3:0]  lsstatus_i;                 // Load/store status inputs
input  [1:0]  istatus_i;                  // Instruction status inputs
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
output                      risc_stall_o; // Stalls the RISC
output                      reset_o;      // Resets the RISC
 
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
 
reg     [31:0]   risc_addr_o;
reg     [31:0]   risc_data_o;
reg     [`OPSELECTWIDTH-1:0] opselect_o;
reg             risc_stall_a;
reg             risc_stall_r;
integer         i, npc, ppc, r1, insn, result;
 
assign tdo_pad_o = 1'b0;
assign capture_dr_o = 1'b0;
assign shift_dr_o = 1'b0;
assign update_dr_o = 1'b0;
assign extest_selected_o = 1'b0;
assign reset_o = 1'b0;
assign risc_stall_o = risc_stall_r | risc_stall_a;
assign wb_cab_o = 1'b0;
 
always @(posedge wb_rst_i or posedge bp_i)
        if (wb_rst_i)
                risc_stall_r <= #1 1'b0;
        else if (bp_i)
                risc_stall_r <= #1 1'b1;
initial begin
        risc_addr_o = 0;
        risc_data_o = 0;
        opselect_o = 0;
        risc_stall_a = 1'b0;
        #100;
        while (!bp_i) @(posedge risc_clk_i);
        stall;
        wb_master.wr(32'h8000_0004, 32'h9c200000, 4'b1111);     /* l.addi  r1,r0,0x0       */
        wb_master.wr(32'h8000_0008, 32'h18408008, 4'b1111);     /* l.movhi r2,0x8008       */
        wb_master.wr(32'h8000_000c, 32'h9c210001, 4'b1111);     /* l.addi  r1,r1,1         */
        wb_master.wr(32'h8000_0010, 32'h9c210001, 4'b1111);     /* l.addi  r1,r1,1         */
        wb_master.wr(32'h8000_0014, 32'hd4020800, 4'b1111);     /* l.sw    0(r2),r1        */
        wb_master.wr(32'h8000_0018, 32'h9c210001, 4'b1111);     /* l.addi  r1,r1,1         */
        wb_master.wr(32'h8000_001c, 32'h84620000, 4'b1111);     /* l.lwz   r3,0(r2)        */
        wb_master.wr(32'h8000_0020, 32'h03fffffb, 4'b1111);     /* l.j     loop2           */
        wb_master.wr(32'h8000_0024, 32'he0211800, 4'b1111);     /* l.add   r1,r1,r3        */
        wb_master.wr(32'h8000_0028, 32'he0211800, 4'b1111);     /* l.add   r1,r1,r3        */
 
        // Enable exceptions in SR
        wr_reg(17, 3);
 
        // Set trap bit in DSR
        wr_reg((6 << 11) + 20, 32'h2000);
 
        // Set NPC
        wr_npc(32'h8000_0004);
 
        // Set step-bit (DMR1[ST])
        wr_reg((6 << 11) + 16, 1 << 22);
 
        // Single-step
        for (i = 1; i < 10; i = i + 1)
                unstall;
 
        // Read NPC
        rd_reg((0 << 11) + 16, npc);
 
        // Read PPC
        rd_reg((0 << 11) + 18, ppc);
 
        // Read R1
        rd_reg(32'h401, r1);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 5);
        result = npc + ppc + r1;
 
 
        /* Reset step bit */
        wr_reg ((6 << 11) + 16, 0);
 
        /* Set trap insn in delay slot */
        wb_master.rd (32'h8000_0024, insn);
        wb_master.wr (32'h8000_0024, 32'h21000001, 4'b1111);
 
        /* Unstall */
        unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        /* Set back original insn */
        wb_master.wr (32'h8000_0024, insn, 4'b1111);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 8);
        result = npc + ppc + r1 + result;
 
 
        /* Set trap insn in place of branch insn */
        wb_master.rd (32'h8000_0020, insn);
        wb_master.wr (32'h8000_0020, 32'h21000001, 4'b1111);
 
        /* Set PC */
        wr_npc(32'h8000_000c);
 
        /* Unstall */
        unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        /* Set back original insn */
        wb_master.wr (32'h8000_0020, insn, 4'b1111);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h80000024, 32'h80000020, 11);
        result = npc + ppc + r1 + result;
 
        /* Set trap insn before branch insn */
        wb_master.rd (32'h8000_001c, insn);
        wb_master.wr (32'h8000_001c, 32'h21000001, 4'b1111);
 
        /* Set PC */
        wr_npc(32'h8000_0020);
 
        /* Unstall */
        unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        /* Set back original insn */
        wb_master.wr (32'h8000_001c, insn, 4'b1111);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h80000020, 32'h8000001c, 24);
        result = npc + ppc + r1 + result;
 
 
        /* Set trap insn behind lsu insn */
        wb_master.rd (32'h8000_0018, insn);
        wb_master.wr (32'h8000_0018, 32'h21000001, 4'b1111);
 
        /* Set PC */
        wr_npc(32'h8000_001c);
 
        /* Unstall */
        unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        /* Set back original insn */
        wb_master.wr (32'h8000_0018, insn, 4'b1111);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h8000001c, 32'h80000018, 49);
        result = npc + ppc + r1 + result;
 
        /* Set trap insn very near previous one */
        wb_master.rd (32'h8000_001c, insn);
        wb_master.wr (32'h8000_001c, 32'h21000001, 4'b1111);
 
        /* Set PC */
        wr_npc(32'h8000_0018);
 
        /* Unstall */
        unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        /* Set back original insn */
        wb_master.wr (32'h8000_001c, insn, 4'b1111);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h80000020, 32'h8000001c, 50);
        result = npc + ppc + r1 + result;
 
        /* Set trap insn to the start */
        wb_master.rd (32'h8000_000c, insn);
        wb_master.wr (32'h8000_000c, 32'h21000001, 4'b1111);
 
        /* Set PC */
        wr_npc(32'h8000_001c);
 
        /* Unstall */
        unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        /* Set back original insn */
        wb_master.wr (32'h8000_000c, insn, 4'b1111);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h80000010, 32'h8000000c, 99);
        result = npc + ppc + r1 + result;
 
        // Set step-bit (DMR1[ST])
        wr_reg((6 << 11) + 16, 1 << 22);
 
        // Single-step
        for (i = 0; i < 5; i = i + 1)
                unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h80000024, 32'h80000020, 101);
        result = npc + ppc + r1 + result;
 
        /* Set PC */
        wr_npc(32'h8000_0020);
 
        // Single-step
        for (i = 0; i < 2; i = i + 1)
                unstall;
 
        /* Read NPC */
        rd_reg((0 << 11) + 16, npc);
 
        /* Read PPC */
        rd_reg((0 << 11) + 18, ppc);
 
        /* Read R1 */
        rd_reg(32'h401, r1);
 
        $display("Read      npc = %h ppc = %h r1 = %h", npc, ppc, r1);
        $display("Expected  npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 201);
        result = npc + ppc + r1 + result;
 
        $display("result = %h\n", result + 32'h5eaddaa9);
 
        #100 $finish;
end
 
task stall;
begin
        risc_stall_r = 1'b1;
        @(posedge risc_clk_i);
        @(posedge risc_clk_i);
end
endtask
 
task unstall;
begin
        risc_stall_r = 1'b0;
        @(posedge risc_clk_i);
        while (!bp_i) @(posedge risc_clk_i);
end
endtask
 
task wr_npc;
input   [31:0]   npc;
begin
        npc = npc - 0;
        wr_reg((0 << 11) + 16, npc);
end
endtask
 
task wr_reg;
input   [31:0]   addr;
input   [31:0]   data;
begin
        risc_stall_a = 1'b1;
        @(posedge risc_clk_i);
        risc_addr_o = addr;
        risc_data_o = data;
        opselect_o = 5;
        @(posedge risc_clk_i);
        risc_addr_o = 0;
        risc_data_o = 0;
        opselect_o = 0;
        @(posedge risc_clk_i);
        @(posedge risc_clk_i);
        @(posedge risc_clk_i);
        risc_stall_a = 1'b0;
end
endtask
 
task rd_reg;
input   [31:0]   addr;
output  [31:0]   data;
begin
        risc_stall_a = 1'b1;
        @(posedge risc_clk_i);
        risc_addr_o = addr;
        opselect_o = 4;
        @(posedge risc_clk_i);
        @(posedge risc_clk_i);
        data = risc_data_i;
        @(posedge risc_clk_i);
        risc_addr_o = 0;
        risc_data_o = 0;
        opselect_o = 0;
        @(posedge risc_clk_i);
        @(posedge risc_clk_i);
        @(posedge risc_clk_i);
        risc_stall_a = 1'b0;
end
endtask
 
//
// Instantiation of Master WISHBONE BFM
//
wb_master wb_master(
        // WISHBONE Interface
        .CLK_I(wb_clk_i),
        .RST_I(wb_rst_i),
        .CYC_O(wb_cyc_o),
        .ADR_O(wb_adr_o),
        .DAT_O(wb_dat_o),
        .SEL_O(wb_sel_o),
        .WE_O(wb_we_o),
        .STB_O(wb_stb_o),
        .DAT_I(wb_dat_i),
        .ACK_I(wb_ack_i),
        .ERR_I(wb_err_i),
        .RTY_I(0),
        .TAG_I(4'b0)
);
 
endmodule

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[/] [or1k/] [trunk/] [mp3/] [bench/] [verilog/] [dbg_if_model.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	563	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_if_model.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC test bench. ////`
7			`//// http://www.opencores.org/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Damjan Lampret ////`
12			`//// lampret@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	590	lampret	`// Revision 1.1 2002/01/14 06:19:35 lampret`
49			`// Added debug model for testing du. Updated or1200_monitor.`
50	563	lampret	`//`
51			`//`
52	590	lampret	`//`
53	563	lampret
54			`include "dbg_defines.v"
55
56			`// Top module`
57			`module dbg_if_model(`
58			`// JTAG pins`
59			`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,`
60
61			`// Boundary Scan signals`
62			`capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i,`
63
64			`// RISC signals`
65			`risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,`
66			`bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,`
67
68			`// WISHBONE common signals`
69			`wb_rst_i, wb_clk_i,`
70
71			`// WISHBONE master interface`
72			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
73			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i`
74
75
76			`);`
77
78			`parameter Tp = 1;`
79
80			`// JTAG pins`
81			`input tms_pad_i; // JTAG test mode select pad`
82			`input tck_pad_i; // JTAG test clock pad`
83			`input trst_pad_i; // JTAG test reset pad`
84			`input tdi_pad_i; // JTAG test data input pad`
85			`output tdo_pad_o; // JTAG test data output pad`
86
87
88			`// Boundary Scan signals`
89			`output capture_dr_o;`
90			`output shift_dr_o;`
91			`output update_dr_o;`
92			`output extest_selected_o;`
93			`input bs_chain_i;`
94
95
96			`// RISC signals`
97			`input risc_clk_i; // Master clock (RISC clock)`
98			`input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)`
99			`input [10:0] wp_i; // Watchpoint inputs`
100			`input bp_i; // Breakpoint input`
101			`input [3:0] lsstatus_i; // Load/store status inputs`
102			`input [1:0] istatus_i; // Instruction status inputs`
103			`output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)`
104			`output [31:0] risc_data_o; // RISC data output (data read from risc registers)`
105			output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
106			`output risc_stall_o; // Stalls the RISC`
107			`output reset_o; // Resets the RISC`
108
109
110			`// WISHBONE common signals`
111			`input wb_rst_i; // WISHBONE reset`
112			`input wb_clk_i; // WISHBONE clock`
113
114			`// WISHBONE master interface`
115			`output [31:0] wb_adr_o;`
116			`output [31:0] wb_dat_o;`
117			`input [31:0] wb_dat_i;`
118			`output wb_cyc_o;`
119			`output wb_stb_o;`
120			`output [3:0] wb_sel_o;`
121			`output wb_we_o;`
122			`input wb_ack_i;`
123			`output wb_cab_o;`
124			`input wb_err_i;`
125
126			`reg [31:0] risc_addr_o;`
127			`reg [31:0] risc_data_o;`
128			reg [`OPSELECTWIDTH-1:0] opselect_o;
129			`reg risc_stall_a;`
130			`reg risc_stall_r;`
131			`integer i, npc, ppc, r1, insn, result;`
132
133			`assign tdo_pad_o = 1'b0;`
134			`assign capture_dr_o = 1'b0;`
135			`assign shift_dr_o = 1'b0;`
136			`assign update_dr_o = 1'b0;`
137			`assign extest_selected_o = 1'b0;`
138			`assign reset_o = 1'b0;`
139			`assign risc_stall_o = risc_stall_r \| risc_stall_a;`
140			`assign wb_cab_o = 1'b0;`
141
142			`always @(posedge wb_rst_i or posedge bp_i)`
143			`if (wb_rst_i)`
144			`risc_stall_r <= #1 1'b0;`
145			`else if (bp_i)`
146			`risc_stall_r <= #1 1'b1;`
147			`initial begin`
148			`risc_addr_o = 0;`
149			`risc_data_o = 0;`
150			`opselect_o = 0;`
151			`risc_stall_a = 1'b0;`
152			`#100;`
153			`while (!bp_i) @(posedge risc_clk_i);`
154			`stall;`
155			`wb_master.wr(32'h8000_0004, 32'h9c200000, 4'b1111); /* l.addi r1,r0,0x0 */`
156			`wb_master.wr(32'h8000_0008, 32'h18408008, 4'b1111); /* l.movhi r2,0x8008 */`
157			`wb_master.wr(32'h8000_000c, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */`
158			`wb_master.wr(32'h8000_0010, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */`
159			`wb_master.wr(32'h8000_0014, 32'hd4020800, 4'b1111); /* l.sw 0(r2),r1 */`
160			`wb_master.wr(32'h8000_0018, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */`
161			`wb_master.wr(32'h8000_001c, 32'h84620000, 4'b1111); /* l.lwz r3,0(r2) */`
162			`wb_master.wr(32'h8000_0020, 32'h03fffffb, 4'b1111); /* l.j loop2 */`
163			`wb_master.wr(32'h8000_0024, 32'he0211800, 4'b1111); /* l.add r1,r1,r3 */`
164			`wb_master.wr(32'h8000_0028, 32'he0211800, 4'b1111); /* l.add r1,r1,r3 */`
165
166			`// Enable exceptions in SR`
167			`wr_reg(17, 3);`
168
169			`// Set trap bit in DSR`
170			`wr_reg((6 << 11) + 20, 32'h2000);`
171
172			`// Set NPC`
173			`wr_npc(32'h8000_0004);`
174
175	590	lampret	`// Set step-bit (DMR1[ST])`
176	563	lampret	`wr_reg((6 << 11) + 16, 1 << 22);`
177
178			`// Single-step`
179			`for (i = 1; i < 10; i = i + 1)`
180			`unstall;`
181
182			`// Read NPC`
183			`rd_reg((0 << 11) + 16, npc);`
184
185			`// Read PPC`
186			`rd_reg((0 << 11) + 18, ppc);`
187
188			`// Read R1`
189			`rd_reg(32'h401, r1);`
190
191			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
192			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 5);`
193			`result = npc + ppc + r1;`
194
195
196			`/* Reset step bit */`
197			`wr_reg ((6 << 11) + 16, 0);`
198
199			`/* Set trap insn in delay slot */`
200			`wb_master.rd (32'h8000_0024, insn);`
201			`wb_master.wr (32'h8000_0024, 32'h21000001, 4'b1111);`
202
203			`/* Unstall */`
204			`unstall;`
205
206			`/* Read NPC */`
207			`rd_reg((0 << 11) + 16, npc);`
208
209			`/* Read PPC */`
210			`rd_reg((0 << 11) + 18, ppc);`
211
212			`/* Read R1 */`
213			`rd_reg(32'h401, r1);`
214
215			`/* Set back original insn */`
216			`wb_master.wr (32'h8000_0024, insn, 4'b1111);`
217
218			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
219			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 8);`
220			`result = npc + ppc + r1 + result;`
221
222
223			`/* Set trap insn in place of branch insn */`
224			`wb_master.rd (32'h8000_0020, insn);`
225			`wb_master.wr (32'h8000_0020, 32'h21000001, 4'b1111);`
226
227			`/* Set PC */`
228			`wr_npc(32'h8000_000c);`
229
230			`/* Unstall */`
231			`unstall;`
232
233			`/* Read NPC */`
234			`rd_reg((0 << 11) + 16, npc);`
235
236			`/* Read PPC */`
237			`rd_reg((0 << 11) + 18, ppc);`
238
239			`/* Read R1 */`
240			`rd_reg(32'h401, r1);`
241
242			`/* Set back original insn */`
243			`wb_master.wr (32'h8000_0020, insn, 4'b1111);`
244
245			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
246			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000024, 32'h80000020, 11);`
247			`result = npc + ppc + r1 + result;`
248
249			`/* Set trap insn before branch insn */`
250			`wb_master.rd (32'h8000_001c, insn);`
251			`wb_master.wr (32'h8000_001c, 32'h21000001, 4'b1111);`
252
253			`/* Set PC */`
254			`wr_npc(32'h8000_0020);`
255
256			`/* Unstall */`
257			`unstall;`
258
259			`/* Read NPC */`
260			`rd_reg((0 << 11) + 16, npc);`
261
262			`/* Read PPC */`
263			`rd_reg((0 << 11) + 18, ppc);`
264
265			`/* Read R1 */`
266			`rd_reg(32'h401, r1);`
267
268			`/* Set back original insn */`
269			`wb_master.wr (32'h8000_001c, insn, 4'b1111);`
270
271			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
272			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000020, 32'h8000001c, 24);`
273			`result = npc + ppc + r1 + result;`
274
275
276			`/* Set trap insn behind lsu insn */`
277			`wb_master.rd (32'h8000_0018, insn);`
278			`wb_master.wr (32'h8000_0018, 32'h21000001, 4'b1111);`
279
280			`/* Set PC */`
281			`wr_npc(32'h8000_001c);`
282
283			`/* Unstall */`
284			`unstall;`
285
286			`/* Read NPC */`
287			`rd_reg((0 << 11) + 16, npc);`
288
289			`/* Read PPC */`
290			`rd_reg((0 << 11) + 18, ppc);`
291
292			`/* Read R1 */`
293			`rd_reg(32'h401, r1);`
294
295			`/* Set back original insn */`
296			`wb_master.wr (32'h8000_0018, insn, 4'b1111);`
297
298			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
299			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000001c, 32'h80000018, 49);`
300			`result = npc + ppc + r1 + result;`
301
302			`/* Set trap insn very near previous one */`
303			`wb_master.rd (32'h8000_001c, insn);`
304			`wb_master.wr (32'h8000_001c, 32'h21000001, 4'b1111);`
305
306			`/* Set PC */`
307			`wr_npc(32'h8000_0018);`
308
309			`/* Unstall */`
310			`unstall;`
311
312			`/* Read NPC */`
313			`rd_reg((0 << 11) + 16, npc);`
314
315			`/* Read PPC */`
316			`rd_reg((0 << 11) + 18, ppc);`
317
318			`/* Read R1 */`
319			`rd_reg(32'h401, r1);`
320
321			`/* Set back original insn */`
322			`wb_master.wr (32'h8000_001c, insn, 4'b1111);`
323
324			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
325			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000020, 32'h8000001c, 50);`
326			`result = npc + ppc + r1 + result;`
327
328			`/* Set trap insn to the start */`
329			`wb_master.rd (32'h8000_000c, insn);`
330			`wb_master.wr (32'h8000_000c, 32'h21000001, 4'b1111);`
331
332			`/* Set PC */`
333			`wr_npc(32'h8000_001c);`
334
335			`/* Unstall */`
336			`unstall;`
337
338			`/* Read NPC */`
339			`rd_reg((0 << 11) + 16, npc);`
340
341			`/* Read PPC */`
342			`rd_reg((0 << 11) + 18, ppc);`
343
344			`/* Read R1 */`
345			`rd_reg(32'h401, r1);`
346
347			`/* Set back original insn */`
348			`wb_master.wr (32'h8000_000c, insn, 4'b1111);`
349
350			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
351			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000010, 32'h8000000c, 99);`
352			`result = npc + ppc + r1 + result;`
353
354	590	lampret	`// Set step-bit (DMR1[ST])`
355			`wr_reg((6 << 11) + 16, 1 << 22);`
356	563	lampret
357	590	lampret	`// Single-step`
358			`for (i = 0; i < 5; i = i + 1)`
359			`unstall;`
360
361			`/* Read NPC */`
362			`rd_reg((0 << 11) + 16, npc);`
363
364			`/* Read PPC */`
365			`rd_reg((0 << 11) + 18, ppc);`
366
367			`/* Read R1 */`
368			`rd_reg(32'h401, r1);`
369
370			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
371			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000024, 32'h80000020, 101);`
372			`result = npc + ppc + r1 + result;`
373
374			`/* Set PC */`
375			`wr_npc(32'h8000_0020);`
376
377			`// Single-step`
378			`for (i = 0; i < 2; i = i + 1)`
379			`unstall;`
380
381			`/* Read NPC */`
382			`rd_reg((0 << 11) + 16, npc);`
383
384			`/* Read PPC */`
385			`rd_reg((0 << 11) + 18, ppc);`
386
387			`/* Read R1 */`
388			`rd_reg(32'h401, r1);`
389
390			`$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);`
391			`$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 201);`
392			`result = npc + ppc + r1 + result;`
393
394			`$display("result = %h\n", result + 32'h5eaddaa9);`
395
396	563	lampret	`#100 $finish;`
397			`end`
398
399			`task stall;`
400			`begin`
401			`risc_stall_r = 1'b1;`
402			`@(posedge risc_clk_i);`
403			`@(posedge risc_clk_i);`
404			`end`
405			`endtask`
406
407			`task unstall;`
408			`begin`
409			`risc_stall_r = 1'b0;`
410			`@(posedge risc_clk_i);`
411			`while (!bp_i) @(posedge risc_clk_i);`
412			`end`
413			`endtask`
414
415			`task wr_npc;`
416			`input [31:0] npc;`
417			`begin`
418			`npc = npc - 0;`
419			`wr_reg((0 << 11) + 16, npc);`
420			`end`
421			`endtask`
422
423			`task wr_reg;`
424			`input [31:0] addr;`
425			`input [31:0] data;`
426			`begin`
427			`risc_stall_a = 1'b1;`
428			`@(posedge risc_clk_i);`
429			`risc_addr_o = addr;`
430			`risc_data_o = data;`
431			`opselect_o = 5;`
432			`@(posedge risc_clk_i);`
433			`risc_addr_o = 0;`
434			`risc_data_o = 0;`
435			`opselect_o = 0;`
436			`@(posedge risc_clk_i);`
437			`@(posedge risc_clk_i);`
438			`@(posedge risc_clk_i);`
439			`risc_stall_a = 1'b0;`
440			`end`
441			`endtask`
442
443			`task rd_reg;`
444			`input [31:0] addr;`
445			`output [31:0] data;`
446			`begin`
447			`risc_stall_a = 1'b1;`
448			`@(posedge risc_clk_i);`
449			`risc_addr_o = addr;`
450			`opselect_o = 4;`
451			`@(posedge risc_clk_i);`
452			`@(posedge risc_clk_i);`
453			`data = risc_data_i;`
454			`@(posedge risc_clk_i);`
455			`risc_addr_o = 0;`
456			`risc_data_o = 0;`
457			`opselect_o = 0;`
458			`@(posedge risc_clk_i);`
459			`@(posedge risc_clk_i);`
460			`@(posedge risc_clk_i);`
461			`risc_stall_a = 1'b0;`
462			`end`
463			`endtask`
464
465			`//`
466			`// Instantiation of Master WISHBONE BFM`
467			`//`
468			`wb_master wb_master(`
469			`// WISHBONE Interface`
470			`.CLK_I(wb_clk_i),`
471			`.RST_I(wb_rst_i),`
472			`.CYC_O(wb_cyc_o),`
473			`.ADR_O(wb_adr_o),`
474			`.DAT_O(wb_dat_o),`
475			`.SEL_O(wb_sel_o),`
476			`.WE_O(wb_we_o),`
477			`.STB_O(wb_stb_o),`
478			`.DAT_I(wb_dat_i),`
479			`.ACK_I(wb_ack_i),`
480			`.ERR_I(wb_err_i),`
481			`.RTY_I(0),`
482			`.TAG_I(4'b0)`
483			`);`
484
485			`endmodule`