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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's simulation monitor                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Simulation monitor                                          ////
////                                                              ////
////  To Do:                                                      ////
////   - move it to bench                                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2002/01/28 01:25:22  lampret
// Fixed display of new 'void' nop insns.
//
// Revision 1.7  2002/01/19 14:10:39  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.6  2002/01/18 07:57:56  lampret
// Added support for reading XILINX_RAM32X1D register file.
//
// Revision 1.5  2002/01/14 06:19:35  lampret
// Added debug model for testing du. Updated or1200_monitor.
//
// Revision 1.4  2002/01/03 08:40:15  lampret
// Added second clock as RISC main clock. Updated or120_monitor.
//
// Revision 1.3  2001/11/23 08:50:35  lampret
// Typos.
//
// Revision 1.2  2001/11/10 04:22:55  lampret
// Modified monitor tu support exceptions.
//
// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
// First import.
//
// Revision 1.1  2001/08/20 18:17:52  damjan
// Initial revision
//
// Revision 1.1  2001/08/13 03:37:07  lampret
// Added monitor.v and timescale.v
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "or1200_defines.v"
 
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP xess_top.i_xess_fpga.risc
 
//
// Enable display_arch_state task
//
`define OR1200_DISPLAY_ARCH_STATE
 
module or1200_monitor;
 
integer fexe;
reg [23:0]  ref;
integer fspr;
integer fnop;
integer r3;
 
//
// Initialization
//
initial begin
        ref = 0;
        fexe = $fopen("executed.log");
        $timeformat (-9, 2, " ns", 12);
        fspr = $fopen("sprs.log");
        fnop = $fopen("nop.log");
end
 
//
// Get GPR
//
task get_gpr;
input   [4:0]    gpr_no;
output  [31:0]   gpr;
integer j;
begin
`ifdef OR1200_XILINX_RAM32X1D
                gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
                gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
                gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
                gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
                gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
                gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
                gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
                gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
                gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
                gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
                gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
                gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
                gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
                gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
                gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
                gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
                gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
                gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
                gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
                gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
                gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
                gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
                gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
                gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
                gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
                gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
                gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
                gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
                gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
                gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
                gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
                gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
`else
`ifdef OR1200_XILINX_RAMB4
        for(j = 0; j < 16; j = j + 1) begin
                gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
        end
        for(j = 0; j < 16; j = j + 1) begin
                gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
        end
`else
`ifdef OR1200_ARTISAN_SDP
`else
        gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
`endif
`endif
`endif
end
endtask
 
//
// Write state of the OR1200 registers into a file
//
// Limitation: only a small subset of register file RAMs
// are supported
//
task display_arch_state;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef OR1200_DISPLAY_ARCH_STATE
        ref = ref + 1;
        $fwrite(fexe, "\nEXECUTED(): %h:  %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
        for(i = 0; i < 32; i = i + 1) begin
                if (i % 4 == 0)
                        $fdisplay(fexe);
                get_gpr(i, r);
                $fwrite(fexe, "GPR%d: %h  ", i, r);
        end
        $fdisplay(fexe);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
        $fwrite(fexe, "SR   : %h  ", r);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
        $fwrite(fexe, "EPCR0: %h  ", r);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
        $fwrite(fexe, "EEAR0: %h  ", r);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
        $fdisplay(fexe, "ESR0 : %h", r);
`endif
end
endtask
 
//
// Hooks for:
// - displaying registers
// - end of simulation
// - access to SPRs
//
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
        if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
                #2;
                if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
                        && !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
                        display_arch_state;
                if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
                        get_gpr(3, r3);
                        $fdisplay(fnop, "%t: l.nop exit (%h)", $time, r3);
                        $finish;
                end
                if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
                        get_gpr(3, r3);
                        $fdisplay(fnop, "%t: l.nop report (%h)", $time, r3);
                end
                if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
                        get_gpr(3, r3);
                        $fdisplay(fnop, "%t: l.nop printf (%h)", $time, r3);
                end
                if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR)  // l.mtspr
                        $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
                        `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
                if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR)  // l.mfspr
                        $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
                        `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
        end
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's simulation monitor ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Simulation monitor ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - move it to bench ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	636	lampret	`// Revision 1.8 2002/01/28 01:25:22 lampret`
48			`// Fixed display of new 'void' nop insns.`
49			`//`
50	618	lampret	`// Revision 1.7 2002/01/19 14:10:39 lampret`
51			`// Fixed OR1200_XILINX_RAM32X1D.`
52			`//`
53	597	lampret	`// Revision 1.6 2002/01/18 07:57:56 lampret`
54			`// Added support for reading XILINX_RAM32X1D register file.`
55			`//`
56	591	lampret	`// Revision 1.5 2002/01/14 06:19:35 lampret`
57			`// Added debug model for testing du. Updated or1200_monitor.`
58			`//`
59	563	lampret	`// Revision 1.4 2002/01/03 08:40:15 lampret`
60			`// Added second clock as RISC main clock. Updated or120_monitor.`
61			`//`
62	506	lampret	`// Revision 1.3 2001/11/23 08:50:35 lampret`
63			`// Typos.`
64			`//`
65	368	lampret	`// Revision 1.2 2001/11/10 04:22:55 lampret`
66			`// Modified monitor tu support exceptions.`
67			`//`
68	318	lampret	`// Revision 1.1.1.1 2001/11/04 18:51:07 lampret`
69			`// First import.`
70			`//`
71	266	lampret	`// Revision 1.1 2001/08/20 18:17:52 damjan`
72			`// Initial revision`
73			`//`
74			`// Revision 1.1 2001/08/13 03:37:07 lampret`
75			`// Added monitor.v and timescale.v`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:03 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82	506	lampret	`include "or1200_defines.v"
83	266	lampret
84	506	lampret	`//`
85			`// Top of OR1200 inside test bench`
86			`//`
87			`define OR1200_TOP xess_top.i_xess_fpga.risc
88	368	lampret
89	506	lampret	`//`
90			`// Enable display_arch_state task`
91			`//`
92			`define OR1200_DISPLAY_ARCH_STATE
93	266	lampret
94			`module or1200_monitor;`
95
96			`integer fexe;`
97			`reg [23:0] ref;`
98	506	lampret	`integer fspr;`
99	563	lampret	`integer fnop;`
100			`integer r3;`
101	266	lampret
102	506	lampret	`//`
103			`// Initialization`
104			`//`
105	266	lampret	`initial begin`
106			`ref = 0;`
107			`fexe = $fopen("executed.log");`
108			`$timeformat (-9, 2, " ns", 12);`
109	506	lampret	`fspr = $fopen("sprs.log");`
110	563	lampret	`fnop = $fopen("nop.log");`
111	266	lampret	`end`
112
113	506	lampret	`//`
114	563	lampret	`// Get GPR`
115			`//`
116			`task get_gpr;`
117			`input [4:0] gpr_no;`
118			`output [31:0] gpr;`
119			`integer j;`
120			`begin`
121	591	lampret	`ifdef OR1200_XILINX_RAM32X1D
122	597	lampret	gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
123			gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
124			gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
125			gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
126			gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
127			gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
128			gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
129			gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
130			gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
131			gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
132			gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
133			gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
134			gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
135			gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
136			gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
137			gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
138			gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
139			gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
140			gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
141			gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
142			gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
143			gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
144			gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
145			gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
146			gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
147			gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
148			gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
149			gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
150			gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
151			gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
152			gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
153			gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
154	591	lampret	`else
155	563	lampret	`ifdef OR1200_XILINX_RAMB4
156			`for(j = 0; j < 16; j = j + 1) begin`
157			gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
158			`end`
159			`for(j = 0; j < 16; j = j + 1) begin`
160			gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
161			`end`
162			`else
163			`ifdef OR1200_ARTISAN_SDP
164			`else
165	597	lampret	gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
166	563	lampret	`endif
167			`endif
168			`endif
169			`end`
170			`endtask`
171
172			`//`
173	506	lampret	`// Write state of the OR1200 registers into a file`
174			`//`
175			`// Limitation: only a small subset of register file RAMs`
176			`// are supported`
177			`//`
178	266	lampret	`task display_arch_state;`
179			`reg [5:0] i;`
180			`reg [31:0] r;`
181			`integer j;`
182			`begin`
183	506	lampret	`ifdef OR1200_DISPLAY_ARCH_STATE
184	266	lampret	`ref = ref + 1;`
185	506	lampret	$fwrite(fexe, "\nEXECUTED(): %h: %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
186	266	lampret	`for(i = 0; i < 32; i = i + 1) begin`
187			`if (i % 4 == 0)`
188			`$fdisplay(fexe);`
189	563	lampret	`get_gpr(i, r);`
190	266	lampret	`$fwrite(fexe, "GPR%d: %h ", i, r);`
191			`end`
192			`$fdisplay(fexe);`
193	506	lampret	r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
194	266	lampret	`$fwrite(fexe, "SR : %h ", r);`
195	506	lampret	r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
196	266	lampret	`$fwrite(fexe, "EPCR0: %h ", r);`
197	506	lampret	r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
198	266	lampret	`$fwrite(fexe, "EEAR0: %h ", r);`
199	506	lampret	r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
200	266	lampret	`$fdisplay(fexe, "ESR0 : %h", r);`
201			`endif
202			`end`
203			`endtask`
204
205	506	lampret	`//`
206			`// Hooks for:`
207			`// - displaying registers`
208			`// - end of simulation`
209			`// - access to SPRs`
210			`//`
211			always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
212			if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
213	266	lampret	`#2;`
214	618	lampret	if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) \|\| !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
215	506	lampret	&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
216	266	lampret	`display_arch_state;`
217	563	lampret	if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
218			`get_gpr(3, r3);`
219			`$fdisplay(fnop, "%t: l.nop exit (%h)", $time, r3);`
220	368	lampret	`$finish;`
221	563	lampret	`end`
222			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
223			`get_gpr(3, r3);`
224			`$fdisplay(fnop, "%t: l.nop report (%h)", $time, r3);`
225			`end`
226			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
227			`get_gpr(3, r3);`
228			`$fdisplay(fnop, "%t: l.nop printf (%h)", $time, r3);`
229			`end`
230	506	lampret	if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
231			`$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,`
232	636	lampret	`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
233	506	lampret	if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
234			`$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,`
235			`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
236	266	lampret	`end`
237
238			`endmodule`

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