OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [mp3/] [bench/] [verilog/] [sram_init.v] - Blame information for rev 1773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 266 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  MP3 demo SRAM init                                          ////
4
////                                                              ////
5
////  This file is part of the MP3 demo application               ////
6
////  http://www.opencores.org/cores/or1k/mp3/                    ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Optional SRAM content initialization (for debugging         ////
10
////  purposes)                                                   ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - nothing really                                           ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2001 Authors                                   ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
//
49
`ifdef SRAM_INIT
50
 
51
module sram_init;
52
 
53
reg [7:0] mem [135005:0];
54
reg [31:0] tmp;
55
 
56
task init_sram;
57
integer i;
58
begin
59
        #1;
60
 
61
        $display("Initializing SRAM ...");
62
        $readmemh("../src/flash.in", mem);
63
        for (i=0; i < 135000; i=i+4) begin
64
                xess_top.Sram_r1.mem_array[i/4] = mem[i];
65
                xess_top.Sram_r0.mem_array[i/4] = mem[i+1];
66
                xess_top.Sram_l1.mem_array[i/4] = mem[i+2];
67
                xess_top.Sram_l0.mem_array[i/4] = mem[i+3];
68
        end
69
 
70
`ifdef UNUSED
71
 
72
        for (i=0; i < 135000; i=i+4) begin
73
                tmp[31:24] = xess_top.Sram_r1.temp_array[i/4];
74
                tmp[23:16] = xess_top.Sram_r0.temp_array[i/4];
75
                tmp[15:8] = xess_top.Sram_l1.temp_array[i/4];
76
                tmp[7:0] = xess_top.Sram_l0.temp_array[i/4];
77
                $display("%h %h", i, tmp);
78
                tmp[31:24] = xess_top.Sram_r1.mem_array[i/4];
79
                tmp[23:16] = xess_top.Sram_r0.mem_array[i/4];
80
                tmp[15:8] = xess_top.Sram_l1.mem_array[i/4];
81
                tmp[7:0] = xess_top.Sram_l0.mem_array[i/4];
82
                $display("%h %h", i, tmp);
83
        end
84
 
85
`endif
86
 
87
end
88
endtask
89
 
90
endmodule
91
 
92
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.