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lampret |
/* $Id: C_COUNTER_BINARY_V3_0.v,v 1.1.1.1 2001-11-04 19:00:05 lampret Exp $
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--
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-- Filename - C_COUNTER_BINARY_V3_0.v
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-- Author - Xilinx
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-- Creation -14 July 1999
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--
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-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V3_0 module
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*/
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`ifdef C_COUNTER_BINARY_V3_0_DEF
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`else
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`define C_COUNTER_BINARY_V3_0_DEF
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`ifdef C_ADDSUB_V3_0_DEF
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`else
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`include "XilinxCoreLib/C_ADDSUB_V3_0.v"
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`endif
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`ifdef C_COMPARE_V3_0_DEF
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`else
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`include "XilinxCoreLib/C_COMPARE_V3_0.v"
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`endif
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`ifdef C_MUX_BUS_V3_0_DEF
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`else
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`include "XilinxCoreLib/C_MUX_BUS_V3_0.v"
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`endif
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`define c_set 0
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`define c_clear 1
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`define c_override 0
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`define c_no_override 1
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`define c_signed 0
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`define c_unsigned 1
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`define c_pin 2
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`define c_up 0
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`define c_down 1
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`define c_updown 2
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`define allXs {C_WIDTH{1'bx}}
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module C_COUNTER_BINARY_V3_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
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parameter C_AINIT_VAL = "0";
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parameter C_COUNT_BY = "";
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parameter C_COUNT_MODE = `c_up;
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parameter C_COUNT_TO = "1111111111111111";
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parameter C_ENABLE_RLOCS = 1;
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parameter C_HAS_ACLR = 0;
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parameter C_HAS_AINIT = 0;
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parameter C_HAS_ASET = 0;
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parameter C_HAS_CE = 0;
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parameter C_HAS_IV = 0;
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parameter C_HAS_L = 0;
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parameter C_HAS_LOAD = 0;
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parameter C_HAS_Q_THRESH0 = 0;
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parameter C_HAS_Q_THRESH1 = 0;
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parameter C_HAS_SCLR = 0;
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parameter C_HAS_SINIT = 0;
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parameter C_HAS_SSET = 0;
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parameter C_HAS_THRESH0 = 0;
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parameter C_HAS_THRESH1 = 0;
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parameter C_HAS_UP = 0;
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parameter C_LOAD_ENABLE = `c_no_override;
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parameter C_LOAD_LOW = 0;
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parameter C_PIPE_STAGES = 0;
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parameter C_RESTRICT_COUNT = 0;
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parameter C_SINIT_VAL = "0";
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parameter C_SYNC_ENABLE = `c_override;
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parameter C_SYNC_PRIORITY = `c_clear;
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parameter C_THRESH0_VALUE = "1111111111111111";
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parameter C_THRESH1_VALUE = "1111111111111111";
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parameter C_THRESH_EARLY = 1;
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parameter C_WIDTH = 16;
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parameter C_OUT_TYPE = `c_signed;
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parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
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parameter iaxero = {62{"0"}};
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parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
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parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
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parameter iazero = {64{"0"}};
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parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ?
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(iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ?
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(iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ?
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(iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ?
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(iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ?
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(iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ?
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(iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ?
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(iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ?
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(iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ?
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(iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ?
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(iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ?
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(iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ?
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(iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ?
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(iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ?
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(iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ?
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(iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ?
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(iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ?
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(iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ?
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(iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ?
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(iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ?
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(iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ?
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(iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ?
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(iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ?
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(iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ?
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(iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ?
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(iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ?
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(iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ?
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(iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ?
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(iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ?
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(iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ?
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(iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ?
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(iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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119 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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120 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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121 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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122 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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126 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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127 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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128 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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129 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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130 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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131 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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132 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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133 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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134 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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: (C_HAS_SCLR == 1 ? 1 : 0));
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parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ?
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(iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ?
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138 |
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(iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ?
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139 |
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(iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ?
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140 |
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(iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ?
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141 |
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(iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ?
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142 |
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(iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ?
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143 |
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(iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ?
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144 |
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(iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ?
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145 |
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(iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ?
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146 |
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(iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ?
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147 |
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(iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ?
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148 |
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(iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ?
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149 |
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(iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ?
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150 |
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(iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ?
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151 |
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(iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ?
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152 |
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(iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ?
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153 |
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(iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ?
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154 |
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(iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ?
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155 |
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(iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ?
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156 |
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(iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ?
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157 |
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(iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ?
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158 |
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(iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ?
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159 |
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(iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ?
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160 |
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(iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ?
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161 |
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(iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ?
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162 |
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(iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ?
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163 |
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(iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ?
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164 |
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(iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ?
|
165 |
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(iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ?
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166 |
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(iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ?
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167 |
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(iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0
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168 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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169 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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170 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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171 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
172 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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173 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
174 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
175 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
176 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
177 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
178 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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179 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
180 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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181 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
182 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
183 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
184 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
185 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
186 |
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: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
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187 |
|
|
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
188 |
|
|
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
|
189 |
|
|
: (C_HAS_SCLR == 1 ? 1 : 0));
|
190 |
|
|
|
191 |
|
|
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
|
195 |
|
|
input CLK;
|
196 |
|
|
input UP;
|
197 |
|
|
input CE;
|
198 |
|
|
input LOAD;
|
199 |
|
|
input [C_WIDTH-1 : 0] L;
|
200 |
|
|
input [C_WIDTH-1 : 0] IV;
|
201 |
|
|
input ACLR;
|
202 |
|
|
input ASET;
|
203 |
|
|
input AINIT;
|
204 |
|
|
input SCLR;
|
205 |
|
|
input SSET;
|
206 |
|
|
input SINIT;
|
207 |
|
|
output THRESH0;
|
208 |
|
|
output Q_THRESH0;
|
209 |
|
|
output THRESH1;
|
210 |
|
|
output Q_THRESH1;
|
211 |
|
|
output [C_WIDTH-1 : 0] Q;
|
212 |
|
|
|
213 |
|
|
// Internal values to drive signals when input is missing
|
214 |
|
|
wire intUP;
|
215 |
|
|
wire intUPbar = ~intUP;
|
216 |
|
|
wire intCE;
|
217 |
|
|
wire intLOAD;
|
218 |
|
|
wire [C_WIDTH-1 : 0] intL;
|
219 |
|
|
wire [C_WIDTH-1 : 0] intB;
|
220 |
|
|
wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
|
221 |
|
|
wire intSCLR;
|
222 |
|
|
wire intCount_to_reached;
|
223 |
|
|
reg intTHRESH0;
|
224 |
|
|
reg intTHRESH1;
|
225 |
|
|
wire intQ_THRESH0;
|
226 |
|
|
wire intQ_THRESH1;
|
227 |
|
|
wire [C_WIDTH-1 : 0] intFBq;
|
228 |
|
|
wire [C_WIDTH-1 : 0] intFBs;
|
229 |
|
|
wire [C_WIDTH-1 : 0] intQ = intFBq;
|
230 |
|
|
wire [C_WIDTH-1 : 0] intFBq_or_zero;
|
231 |
|
|
wire [C_WIDTH-1 : 0] intFBs_or_q;
|
232 |
|
|
wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
|
233 |
|
|
wire [C_WIDTH-1 : 0] intB_or_load;
|
234 |
|
|
wire [C_WIDTH-1 : 0] tmpintB_or_load;
|
235 |
|
|
|
236 |
|
|
wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
|
237 |
|
|
wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
|
238 |
|
|
wire [C_WIDTH-1 : 0] Q = intQ;
|
239 |
|
|
|
240 |
|
|
wire [C_WIDTH-1 : 0] intXLOADMUX;
|
241 |
|
|
wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
|
242 |
|
|
wire [C_WIDTH-1 : 0] intXL;
|
243 |
|
|
wire intXLOAD;
|
244 |
|
|
wire intXXLOAD;
|
245 |
|
|
wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
|
246 |
|
|
|
247 |
|
|
// Sort out default values for missing ports
|
248 |
|
|
|
249 |
|
|
assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
|
250 |
|
|
assign intCE = defval(CE, C_HAS_CE, 1);
|
251 |
|
|
assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
|
252 |
|
|
assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
|
253 |
|
|
assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
|
254 |
|
|
assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
|
255 |
|
|
assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
|
256 |
|
|
assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
|
257 |
|
|
assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
|
258 |
|
|
assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
|
259 |
|
|
assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
|
260 |
|
|
|
261 |
|
|
|
262 |
|
|
// The addsub on which this is based...
|
263 |
|
|
|
264 |
|
|
C_ADDSUB_V3_0 #(C_COUNT_MODE,
|
265 |
|
|
C_AINIT_VAL,
|
266 |
|
|
C_OUT_TYPE,
|
267 |
|
|
C_WIDTH,
|
268 |
|
|
(((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
|
269 |
|
|
C_LOAD_LOW, // DLUNN CHANGED FROM 0,
|
270 |
|
|
0,
|
271 |
|
|
C_OUT_TYPE,
|
272 |
|
|
"",
|
273 |
|
|
C_WIDTH,
|
274 |
|
|
C_ENABLE_RLOCS,
|
275 |
|
|
C_HAS_ACLR,
|
276 |
|
|
C_HAS_UP,
|
277 |
|
|
C_HAS_AINIT,
|
278 |
|
|
C_HAS_ASET,
|
279 |
|
|
0,
|
280 |
|
|
C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1,
|
281 |
|
|
0,
|
282 |
|
|
0,
|
283 |
|
|
0,
|
284 |
|
|
C_HAS_CE,
|
285 |
|
|
1,
|
286 |
|
|
0,
|
287 |
|
|
0,
|
288 |
|
|
1,
|
289 |
|
|
0,
|
290 |
|
|
0,
|
291 |
|
|
0,
|
292 |
|
|
1,
|
293 |
|
|
adder_HAS_SCLR,
|
294 |
|
|
C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1),
|
295 |
|
|
C_HAS_SSET,
|
296 |
|
|
C_WIDTH-1,
|
297 |
|
|
1,
|
298 |
|
|
0,
|
299 |
|
|
C_WIDTH,
|
300 |
|
|
C_PIPE_STAGES,
|
301 |
|
|
C_SINIT_VAL,
|
302 |
|
|
C_SYNC_ENABLE,
|
303 |
|
|
C_SYNC_PRIORITY)
|
304 |
|
|
the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
|
305 |
|
|
.CE(CE), .C_IN(intUPbar), .ACLR(ACLR), .ASET(ASET),
|
306 |
|
|
.AINIT(AINIT), .SCLR(intSCLR_RESET), .SSET(SSET),
|
307 |
|
|
.SINIT(SINIT), .BYPASS(intXLOAD), .S(intFBs), .Q(intFBq));
|
308 |
|
|
|
309 |
|
|
// The Restrict Count/Sinit LOAD mux
|
310 |
|
|
|
311 |
|
|
C_MUX_BUS_V3_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
|
312 |
|
|
0, 0, 1, "", 0, 0, C_WIDTH)
|
313 |
|
|
mxRCSL(.MA(intSINITVAL), .MB(intL), .S(intLOAD), .O(intXLOADMUX));
|
314 |
|
|
|
315 |
|
|
// The feedback mux
|
316 |
|
|
|
317 |
|
|
C_MUX_BUS_V3_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
|
318 |
|
|
0, 0, 1, "", 0, 0, C_WIDTH)
|
319 |
|
|
mxfb(.MA(intFBq), .MB(all_zeros), .S(intXXLOAD), .O(intFBq_or_zero));
|
320 |
|
|
|
321 |
|
|
// The LOAD mux
|
322 |
|
|
|
323 |
|
|
C_MUX_BUS_V3_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
|
324 |
|
|
0, 0, 1, "", 0, 0, C_WIDTH)
|
325 |
|
|
mx1(.MA(intB), .MB(intXL), .S(intXXLOAD), .O(tmpintB_or_load));
|
326 |
|
|
|
327 |
|
|
// The Threshhold comparators
|
328 |
|
|
|
329 |
|
|
C_COMPARE_V3_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
|
330 |
|
|
C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
|
331 |
|
|
0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH)
|
332 |
|
|
th0(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH0), .QA_EQ_B(Q_THRESH0));
|
333 |
|
|
|
334 |
|
|
C_COMPARE_V3_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
|
335 |
|
|
C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
|
336 |
|
|
0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH)
|
337 |
|
|
th1(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH1), .QA_EQ_B(Q_THRESH1));
|
338 |
|
|
|
339 |
|
|
C_COMPARE_V3_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
|
340 |
|
|
0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
|
341 |
|
|
0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH)
|
342 |
|
|
th_to(.A(intFBs), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(SCLR), .QA_EQ_B(intCount_to_reached));
|
343 |
|
|
|
344 |
|
|
initial
|
345 |
|
|
begin
|
346 |
|
|
|
347 |
|
|
#1;
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
end
|
351 |
|
|
|
352 |
|
|
function defval;
|
353 |
|
|
input i;
|
354 |
|
|
input hassig;
|
355 |
|
|
input val;
|
356 |
|
|
begin
|
357 |
|
|
if(hassig == 1)
|
358 |
|
|
defval = i;
|
359 |
|
|
else
|
360 |
|
|
defval = val;
|
361 |
|
|
end
|
362 |
|
|
endfunction
|
363 |
|
|
|
364 |
|
|
function [C_WIDTH - 1 : 0] to_bits;
|
365 |
|
|
input [C_WIDTH*8 : 1] instring;
|
366 |
|
|
integer i;
|
367 |
|
|
begin
|
368 |
|
|
for(i = C_WIDTH; i > 0; i = i - 1)
|
369 |
|
|
begin // Is this character a '0'? (ASCII = 48 = 00110000)
|
370 |
|
|
if(instring[(i*8)] == 0 &&
|
371 |
|
|
instring[(i*8)-1] == 0 &&
|
372 |
|
|
instring[(i*8)-2] == 1 &&
|
373 |
|
|
instring[(i*8)-3] == 1 &&
|
374 |
|
|
instring[(i*8)-4] == 0 &&
|
375 |
|
|
instring[(i*8)-5] == 0 &&
|
376 |
|
|
instring[(i*8)-6] == 0 &&
|
377 |
|
|
instring[(i*8)-7] == 0)
|
378 |
|
|
to_bits[i-1] = 0;
|
379 |
|
|
// Or is it a '1'?
|
380 |
|
|
else if(instring[(i*8)] == 0 &&
|
381 |
|
|
instring[(i*8)-1] == 0 &&
|
382 |
|
|
instring[(i*8)-2] == 1 &&
|
383 |
|
|
instring[(i*8)-3] == 1 &&
|
384 |
|
|
instring[(i*8)-4] == 0 &&
|
385 |
|
|
instring[(i*8)-5] == 0 &&
|
386 |
|
|
instring[(i*8)-6] == 0 &&
|
387 |
|
|
instring[(i*8)-7] == 1)
|
388 |
|
|
|
389 |
|
|
to_bits[i-1] = 1;
|
390 |
|
|
// Or is it a ' '? (a null char - in which case insert a '0')
|
391 |
|
|
else if(instring[(i*8)] == 0 &&
|
392 |
|
|
instring[(i*8)-1] == 0 &&
|
393 |
|
|
instring[(i*8)-2] == 0 &&
|
394 |
|
|
instring[(i*8)-3] == 0 &&
|
395 |
|
|
instring[(i*8)-4] == 0 &&
|
396 |
|
|
instring[(i*8)-5] == 0 &&
|
397 |
|
|
instring[(i*8)-6] == 0 &&
|
398 |
|
|
instring[(i*8)-7] == 0)
|
399 |
|
|
to_bits[i-1] = 0;
|
400 |
|
|
else
|
401 |
|
|
begin
|
402 |
|
|
$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
|
403 |
|
|
$finish;
|
404 |
|
|
end
|
405 |
|
|
end
|
406 |
|
|
end
|
407 |
|
|
endfunction
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
endmodule
|
412 |
|
|
|
413 |
|
|
`undef c_set
|
414 |
|
|
`undef c_clear
|
415 |
|
|
`undef c_override
|
416 |
|
|
`undef c_no_override
|
417 |
|
|
`undef c_signed
|
418 |
|
|
`undef c_unsigned
|
419 |
|
|
`undef c_pin
|
420 |
|
|
`undef c_up
|
421 |
|
|
`undef c_down
|
422 |
|
|
`undef c_updown
|
423 |
|
|
`undef allXs
|
424 |
|
|
|
425 |
|
|
`endif
|