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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [AND12.v] - Blame information for rev 1767

Line No.	Rev	Author	Line
1	266	lampret	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/AND12.v,v 1.1.1.1 2001-11-04 18:59:46 lampret Exp $`
2
3			`/*`
4
5			`FUNCTION : 12-INPUT AND GATE`
6
7			`*/`
8
9			`timescale 100 ps / 10 ps
10
11			`celldefine
12
13			`module AND12 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11);`
14
15			`parameter cds_action = "ignore";`
16
17			`output O;`
18
19			`input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11;`
20
21			`and O1 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11);`
22
23			`specify`
24			`(I0 *> O) = (1, 1);`
25			`(I1 *> O) = (1, 1);`
26			`(I2 *> O) = (1, 1);`
27			`(I3 *> O) = (1, 1);`
28			`(I4 *> O) = (1, 1);`
29			`(I5 *> O) = (1, 1);`
30			`(I6 *> O) = (1, 1);`
31			`(I7 *> O) = (1, 1);`
32			`(I8 *> O) = (1, 1);`
33			`(I9 *> O) = (1, 1);`
34			`(I10 *> O) = (1, 1);`
35			`(I11 *> O) = (1, 1);`
36			`endspecify`
37
38			`endmodule`
39
40			`endcelldefine