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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [FDDRCPE.v] - Blame information for rev 1767

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1 266 lampret
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/FDDRCPE.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $
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/*
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FUNCTION        : Dual Data Rate MUX
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*/
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`timescale  100 ps / 10 ps
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`celldefine
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module FDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE);
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    parameter cds_action = "ignore";
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    parameter INIT = 1'h0;
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    output Q;
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    reg    q_out;
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    input  C0, C1, CE, CLR, D0, D1, PRE;
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    tri0 GSR = glbl.GSR;
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    buf B1 (Q, q_out);
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        always @(GSR or CLR or PRE)
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            if (GSR)
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                assign q_out = INIT;
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            else if (CLR)
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                assign q_out = 0;
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            else if (PRE)
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                assign q_out = 1;
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            else
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                deassign q_out;
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        always @(posedge C0)
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            if (CE)
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                q_out <= D0;
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        always @(posedge C1)
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            if (CE)
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                q_out <= D1;
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    specify
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        (posedge CLR => (Q +: 1'b0)) = (1, 1);
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        if (!CLR)
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            (posedge PRE => (Q +: 1'b1)) = (1, 1);
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        if (!CLR && !PRE && CE)
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            (posedge C0 => (Q +: D0)) = (1, 1);
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        if (!CLR && !PRE && CE)
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            (posedge C1 => (Q +: D1)) = (1, 1);
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    endspecify
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endmodule
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`endcelldefine

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