Subversion Repositories or1k

// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/FDRSE_1.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $

/*

FUNCTION        : D-FLIP-FLOP with sync reset, sync set and clock enable

*/

`timescale  100 ps / 10 ps

`celldefine

module FDRSE_1 (Q, C, CE, D, R, S);

    parameter cds_action = "ignore";

    parameter INIT = 1'b0;

    output Q;

    reg    q_out;

    input  C, CE, D, R, S;

    tri0 GSR = glbl.GSR;

    buf B1 (Q, q_out);

        always @(GSR)

            if (GSR)

                assign q_out = INIT;

            else

                deassign q_out;

        always @(negedge C)

            if (R)

                q_out <= 0;

            else if (S)

                q_out <= 1;

            else if (CE)

                q_out <= D;

    specify

        if (R)

            (negedge C => (Q +: 1'b0)) = (1, 1);

        if (!R && S)

            (negedge C => (Q +: 1'b1)) = (1, 1);

        if (!R && !S && CE)

            (negedge C => (Q +: D)) = (1, 1);

    endspecify

endmodule

`endcelldefine