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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/FDR_1.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $

/*

FUNCTION        : D-FLIP-FLOP with sync reset

*/

`timescale  100 ps / 10 ps

`celldefine

module FDR_1 (Q, C, D, R);

    parameter cds_action = "ignore";

    parameter INIT = 1'b0;

    output Q;

    reg    q_out;

    input  C, D, R;

    tri0 GSR = glbl.GSR;

    buf B1 (Q, q_out);

        always @(GSR)

            if (GSR)

                assign q_out = INIT;

            else

                deassign q_out;

        always @(negedge C)

            if (R)

                q_out <= 0;

            else

                q_out <= D;

    specify

        if (R)

            (negedge C => (Q +: 1'b0)) = (1, 1);

        if (!R)

            (negedge C => (Q +: D)) = (1, 1);

    endspecify

endmodule

`endcelldefine