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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [LDCE_1.v] - Blame information for rev 1765

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1 266 lampret
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/LDCE_1.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $
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/*
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FUNCTION        : D-LATCH with async clear and gate enable
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*/
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`timescale  100 ps / 10 ps
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`celldefine
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module LDCE_1 (Q, CLR, D, G, GE);
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    parameter cds_action = "ignore";
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    parameter INIT = 1'b0;
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    output Q;
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    reg    q_out;
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    input  CLR, D, G, GE;
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    tri0 GSR = glbl.GSR;
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    buf B1 (Q, q_out);
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        always @(GSR or CLR or D or G or GE)
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            if (GSR)
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                q_out <= INIT;
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            else if (CLR)
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                q_out <= 0;
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            else if (!G && GE)
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                q_out <= D;
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    specify
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        if (!CLR && !G && GE)
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            (D +=> Q) = (1, 1);
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        if (!CLR && GE)
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            (negedge G => (Q +: D)) = (1, 1);
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        if (!CLR && !G)
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            (posedge GE => (Q +: D)) = (1, 1);
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        (posedge CLR => (Q +: 1'b0)) = (1, 1);
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    endspecify
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endmodule
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`endcelldefine

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