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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S18_S36.v] - Blame information for rev 1767

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S18_S36.v,v 1.1.1.1 2001-11-04 18:59:52 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x18x36 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S18_S36 (DOA, DOPA, DOB, DOPB, ADDRA, CLKA, DIA, DIPA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, DIPB, ENB, SSRB, WEB);
14 
    parameter cds_action = "ignore";
15 
    parameter INIT_A = 18'h0;
16 
    parameter INIT_B = 36'h0;
17 
    parameter SRVAL_A = 18'h0;
18 
    parameter SRVAL_B = 36'h0;
19 
    parameter WRITE_MODE_A = "WRITE_FIRST";
20 
    parameter WRITE_MODE_B = "WRITE_FIRST";
21 
 
22 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
34 
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
35 
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
36 
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37 
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38 
    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39 
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40 
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42 
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45 
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63 
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65 
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66 
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77 
    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86 
    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94 
 
95 
    output [15:0] DOA;
96 
    output [1:0] DOPA;
97 
    reg [15:0] doa_out;
98 
    reg [1:0] dopa_out;
99 
    wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15;
100 
    wire dopa0_out, dopa1_out;
101 
 
102 
    input [9:0] ADDRA;
103 
    input [15:0] DIA;
104 
    input [1:0] DIPA;
105 
    input ENA, CLKA, WEA, SSRA;
106 
 
107 
    output [31:0] DOB;
108 
    output [3:0] DOPB;
109 
    reg [31:0] dob_out;
110 
    reg [3:0] dopb_out;
111 
    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31;
112 
    wire dopb0_out, dopb1_out, dopb2_out, dopb3_out;
113 
 
114 
    input [8:0] ADDRB;
115 
    input [31:0] DIB;
116 
    input [3:0] DIPB;
117 
    input ENB, CLKB, WEB, SSRB;
118 
 
119 
    reg [18431:0] mem;
120 
    reg [8:0] count;
121 
    reg [1:0] wr_mode_a, wr_mode_b;
122 
 
123 
    reg [5:0] ci, cj;
124 
    reg [5:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
125 
    reg [5:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
126 
 
127 
    wire [9:0] addra_int;
128 
    wire [15:0] dia_int;
129 
    wire [1:0] dipa_int;
130 
    wire ena_int, clka_int, wea_int, ssra_int;
131 
    wire [8:0] addrb_int;
132 
    wire [31:0] dib_int;
133 
    wire [3:0] dipb_int;
134 
    wire enb_int, clkb_int, web_int, ssrb_int;
135 
 
136 
    reg recovery_a, recovery_b;
137 
    reg address_collision;
138 
 
139 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
140 
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
141 
    wire collision = clka_enable || clkb_enable;
142 
 
143 
    tri0 GSR = glbl.GSR;
144 
 
145 
    always @(GSR)
146 
        if (GSR) begin
147 
            assign doa_out = INIT_A[15:0];
148 
            assign dopa_out = INIT_A[17:16];
149 
            assign dob_out = INIT_B[31:0];
150 
            assign dopb_out = INIT_B[35:32];
151 
        end
152 
        else begin
153 
            deassign doa_out;
154 
            deassign dopa_out;
155 
            deassign dob_out;
156 
            deassign dopb_out;
157 
        end
158 
 
159 
    buf b_doa_out0 (doa_out0, doa_out[0]);
160 
    buf b_doa_out1 (doa_out1, doa_out[1]);
161 
    buf b_doa_out2 (doa_out2, doa_out[2]);
162 
    buf b_doa_out3 (doa_out3, doa_out[3]);
163 
    buf b_doa_out4 (doa_out4, doa_out[4]);
164 
    buf b_doa_out5 (doa_out5, doa_out[5]);
165 
    buf b_doa_out6 (doa_out6, doa_out[6]);
166 
    buf b_doa_out7 (doa_out7, doa_out[7]);
167 
    buf b_doa_out8 (doa_out8, doa_out[8]);
168 
    buf b_doa_out9 (doa_out9, doa_out[9]);
169 
    buf b_doa_out10 (doa_out10, doa_out[10]);
170 
    buf b_doa_out11 (doa_out11, doa_out[11]);
171 
    buf b_doa_out12 (doa_out12, doa_out[12]);
172 
    buf b_doa_out13 (doa_out13, doa_out[13]);
173 
    buf b_doa_out14 (doa_out14, doa_out[14]);
174 
    buf b_doa_out15 (doa_out15, doa_out[15]);
175 
    buf b_dopa_out0 (dopa_out0, dopa_out[0]);
176 
    buf b_dopa_out1 (dopa_out1, dopa_out[1]);
177 
    buf b_dob_out0 (dob_out0, dob_out[0]);
178 
    buf b_dob_out1 (dob_out1, dob_out[1]);
179 
    buf b_dob_out2 (dob_out2, dob_out[2]);
180 
    buf b_dob_out3 (dob_out3, dob_out[3]);
181 
    buf b_dob_out4 (dob_out4, dob_out[4]);
182 
    buf b_dob_out5 (dob_out5, dob_out[5]);
183 
    buf b_dob_out6 (dob_out6, dob_out[6]);
184 
    buf b_dob_out7 (dob_out7, dob_out[7]);
185 
    buf b_dob_out8 (dob_out8, dob_out[8]);
186 
    buf b_dob_out9 (dob_out9, dob_out[9]);
187 
    buf b_dob_out10 (dob_out10, dob_out[10]);
188 
    buf b_dob_out11 (dob_out11, dob_out[11]);
189 
    buf b_dob_out12 (dob_out12, dob_out[12]);
190 
    buf b_dob_out13 (dob_out13, dob_out[13]);
191 
    buf b_dob_out14 (dob_out14, dob_out[14]);
192 
    buf b_dob_out15 (dob_out15, dob_out[15]);
193 
    buf b_dob_out16 (dob_out16, dob_out[16]);
194 
    buf b_dob_out17 (dob_out17, dob_out[17]);
195 
    buf b_dob_out18 (dob_out18, dob_out[18]);
196 
    buf b_dob_out19 (dob_out19, dob_out[19]);
197 
    buf b_dob_out20 (dob_out20, dob_out[20]);
198 
    buf b_dob_out21 (dob_out21, dob_out[21]);
199 
    buf b_dob_out22 (dob_out22, dob_out[22]);
200 
    buf b_dob_out23 (dob_out23, dob_out[23]);
201 
    buf b_dob_out24 (dob_out24, dob_out[24]);
202 
    buf b_dob_out25 (dob_out25, dob_out[25]);
203 
    buf b_dob_out26 (dob_out26, dob_out[26]);
204 
    buf b_dob_out27 (dob_out27, dob_out[27]);
205 
    buf b_dob_out28 (dob_out28, dob_out[28]);
206 
    buf b_dob_out29 (dob_out29, dob_out[29]);
207 
    buf b_dob_out30 (dob_out30, dob_out[30]);
208 
    buf b_dob_out31 (dob_out31, dob_out[31]);
209 
    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
210 
    buf b_dopb_out1 (dopb_out1, dopb_out[1]);
211 
    buf b_dopb_out2 (dopb_out2, dopb_out[2]);
212 
    buf b_dopb_out3 (dopb_out3, dopb_out[3]);
213 
 
214 
    buf b_doa0 (DOA[0], doa_out0);
215 
    buf b_doa1 (DOA[1], doa_out1);
216 
    buf b_doa2 (DOA[2], doa_out2);
217 
    buf b_doa3 (DOA[3], doa_out3);
218 
    buf b_doa4 (DOA[4], doa_out4);
219 
    buf b_doa5 (DOA[5], doa_out5);
220 
    buf b_doa6 (DOA[6], doa_out6);
221 
    buf b_doa7 (DOA[7], doa_out7);
222 
    buf b_doa8 (DOA[8], doa_out8);
223 
    buf b_doa9 (DOA[9], doa_out9);
224 
    buf b_doa10 (DOA[10], doa_out10);
225 
    buf b_doa11 (DOA[11], doa_out11);
226 
    buf b_doa12 (DOA[12], doa_out12);
227 
    buf b_doa13 (DOA[13], doa_out13);
228 
    buf b_doa14 (DOA[14], doa_out14);
229 
    buf b_doa15 (DOA[15], doa_out15);
230 
    buf b_dopa0 (DOPA[0], dopa_out0);
231 
    buf b_dopa1 (DOPA[1], dopa_out1);
232 
    buf b_dob0 (DOB[0], dob_out0);
233 
    buf b_dob1 (DOB[1], dob_out1);
234 
    buf b_dob2 (DOB[2], dob_out2);
235 
    buf b_dob3 (DOB[3], dob_out3);
236 
    buf b_dob4 (DOB[4], dob_out4);
237 
    buf b_dob5 (DOB[5], dob_out5);
238 
    buf b_dob6 (DOB[6], dob_out6);
239 
    buf b_dob7 (DOB[7], dob_out7);
240 
    buf b_dob8 (DOB[8], dob_out8);
241 
    buf b_dob9 (DOB[9], dob_out9);
242 
    buf b_dob10 (DOB[10], dob_out10);
243 
    buf b_dob11 (DOB[11], dob_out11);
244 
    buf b_dob12 (DOB[12], dob_out12);
245 
    buf b_dob13 (DOB[13], dob_out13);
246 
    buf b_dob14 (DOB[14], dob_out14);
247 
    buf b_dob15 (DOB[15], dob_out15);
248 
    buf b_dob16 (DOB[16], dob_out16);
249 
    buf b_dob17 (DOB[17], dob_out17);
250 
    buf b_dob18 (DOB[18], dob_out18);
251 
    buf b_dob19 (DOB[19], dob_out19);
252 
    buf b_dob20 (DOB[20], dob_out20);
253 
    buf b_dob21 (DOB[21], dob_out21);
254 
    buf b_dob22 (DOB[22], dob_out22);
255 
    buf b_dob23 (DOB[23], dob_out23);
256 
    buf b_dob24 (DOB[24], dob_out24);
257 
    buf b_dob25 (DOB[25], dob_out25);
258 
    buf b_dob26 (DOB[26], dob_out26);
259 
    buf b_dob27 (DOB[27], dob_out27);
260 
    buf b_dob28 (DOB[28], dob_out28);
261 
    buf b_dob29 (DOB[29], dob_out29);
262 
    buf b_dob30 (DOB[30], dob_out30);
263 
    buf b_dob31 (DOB[31], dob_out31);
264 
    buf b_dopb0 (DOPB[0], dopb_out0);
265 
    buf b_dopb1 (DOPB[1], dopb_out1);
266 
    buf b_dopb2 (DOPB[2], dopb_out2);
267 
    buf b_dopb3 (DOPB[3], dopb_out3);
268 
 
269 
    buf b_addra_0 (addra_int[0], ADDRA[0]);
270 
    buf b_addra_1 (addra_int[1], ADDRA[1]);
271 
    buf b_addra_2 (addra_int[2], ADDRA[2]);
272 
    buf b_addra_3 (addra_int[3], ADDRA[3]);
273 
    buf b_addra_4 (addra_int[4], ADDRA[4]);
274 
    buf b_addra_5 (addra_int[5], ADDRA[5]);
275 
    buf b_addra_6 (addra_int[6], ADDRA[6]);
276 
    buf b_addra_7 (addra_int[7], ADDRA[7]);
277 
    buf b_addra_8 (addra_int[8], ADDRA[8]);
278 
    buf b_addra_9 (addra_int[9], ADDRA[9]);
279 
    buf b_dia_0 (dia_int[0], DIA[0]);
280 
    buf b_dia_1 (dia_int[1], DIA[1]);
281 
    buf b_dia_2 (dia_int[2], DIA[2]);
282 
    buf b_dia_3 (dia_int[3], DIA[3]);
283 
    buf b_dia_4 (dia_int[4], DIA[4]);
284 
    buf b_dia_5 (dia_int[5], DIA[5]);
285 
    buf b_dia_6 (dia_int[6], DIA[6]);
286 
    buf b_dia_7 (dia_int[7], DIA[7]);
287 
    buf b_dia_8 (dia_int[8], DIA[8]);
288 
    buf b_dia_9 (dia_int[9], DIA[9]);
289 
    buf b_dia_10 (dia_int[10], DIA[10]);
290 
    buf b_dia_11 (dia_int[11], DIA[11]);
291 
    buf b_dia_12 (dia_int[12], DIA[12]);
292 
    buf b_dia_13 (dia_int[13], DIA[13]);
293 
    buf b_dia_14 (dia_int[14], DIA[14]);
294 
    buf b_dia_15 (dia_int[15], DIA[15]);
295 
    buf b_dipa_0 (dipa_int[0], DIPA[0]);
296 
    buf b_dipa_1 (dipa_int[1], DIPA[1]);
297 
    buf b_ena (ena_int, ENA);
298 
    buf b_clka (clka_int, CLKA);
299 
    buf b_ssra (ssra_int, SSRA);
300 
    buf b_wea (wea_int, WEA);
301 
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
302 
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
303 
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
304 
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
305 
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
306 
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
307 
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
308 
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
309 
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
310 
    buf b_dib_0 (dib_int[0], DIB[0]);
311 
    buf b_dib_1 (dib_int[1], DIB[1]);
312 
    buf b_dib_2 (dib_int[2], DIB[2]);
313 
    buf b_dib_3 (dib_int[3], DIB[3]);
314 
    buf b_dib_4 (dib_int[4], DIB[4]);
315 
    buf b_dib_5 (dib_int[5], DIB[5]);
316 
    buf b_dib_6 (dib_int[6], DIB[6]);
317 
    buf b_dib_7 (dib_int[7], DIB[7]);
318 
    buf b_dib_8 (dib_int[8], DIB[8]);
319 
    buf b_dib_9 (dib_int[9], DIB[9]);
320 
    buf b_dib_10 (dib_int[10], DIB[10]);
321 
    buf b_dib_11 (dib_int[11], DIB[11]);
322 
    buf b_dib_12 (dib_int[12], DIB[12]);
323 
    buf b_dib_13 (dib_int[13], DIB[13]);
324 
    buf b_dib_14 (dib_int[14], DIB[14]);
325 
    buf b_dib_15 (dib_int[15], DIB[15]);
326 
    buf b_dib_16 (dib_int[16], DIB[16]);
327 
    buf b_dib_17 (dib_int[17], DIB[17]);
328 
    buf b_dib_18 (dib_int[18], DIB[18]);
329 
    buf b_dib_19 (dib_int[19], DIB[19]);
330 
    buf b_dib_20 (dib_int[20], DIB[20]);
331 
    buf b_dib_21 (dib_int[21], DIB[21]);
332 
    buf b_dib_22 (dib_int[22], DIB[22]);
333 
    buf b_dib_23 (dib_int[23], DIB[23]);
334 
    buf b_dib_24 (dib_int[24], DIB[24]);
335 
    buf b_dib_25 (dib_int[25], DIB[25]);
336 
    buf b_dib_26 (dib_int[26], DIB[26]);
337 
    buf b_dib_27 (dib_int[27], DIB[27]);
338 
    buf b_dib_28 (dib_int[28], DIB[28]);
339 
    buf b_dib_29 (dib_int[29], DIB[29]);
340 
    buf b_dib_30 (dib_int[30], DIB[30]);
341 
    buf b_dib_31 (dib_int[31], DIB[31]);
342 
    buf b_dipb_0 (dipb_int[0], DIPB[0]);
343 
    buf b_dipb_1 (dipb_int[1], DIPB[1]);
344 
    buf b_dipb_2 (dipb_int[2], DIPB[2]);
345 
    buf b_dipb_3 (dipb_int[3], DIPB[3]);
346 
    buf b_enb (enb_int, ENB);
347 
    buf b_clkb (clkb_int, CLKB);
348 
    buf b_ssrb (ssrb_int, SSRB);
349 
    buf b_web (web_int, WEB);
350 
 
351 
    initial begin
352 
        for (count = 0; count < 256; count = count + 1) begin
353 
            mem[count]            <= INIT_00[count];
354 
            mem[256 * 1 + count]  <= INIT_01[count];
355 
            mem[256 * 2 + count]  <= INIT_02[count];
356 
            mem[256 * 3 + count]  <= INIT_03[count];
357 
            mem[256 * 4 + count]  <= INIT_04[count];
358 
            mem[256 * 5 + count]  <= INIT_05[count];
359 
            mem[256 * 6 + count]  <= INIT_06[count];
360 
            mem[256 * 7 + count]  <= INIT_07[count];
361 
            mem[256 * 8 + count]  <= INIT_08[count];
362 
            mem[256 * 9 + count]  <= INIT_09[count];
363 
            mem[256 * 10 + count] <= INIT_0A[count];
364 
            mem[256 * 11 + count] <= INIT_0B[count];
365 
            mem[256 * 12 + count] <= INIT_0C[count];
366 
            mem[256 * 13 + count] <= INIT_0D[count];
367 
            mem[256 * 14 + count] <= INIT_0E[count];
368 
            mem[256 * 15 + count] <= INIT_0F[count];
369 
            mem[256 * 16 + count] <= INIT_10[count];
370 
            mem[256 * 17 + count] <= INIT_11[count];
371 
            mem[256 * 18 + count] <= INIT_12[count];
372 
            mem[256 * 19 + count] <= INIT_13[count];
373 
            mem[256 * 20 + count] <= INIT_14[count];
374 
            mem[256 * 21 + count] <= INIT_15[count];
375 
            mem[256 * 22 + count] <= INIT_16[count];
376 
            mem[256 * 23 + count] <= INIT_17[count];
377 
            mem[256 * 24 + count] <= INIT_18[count];
378 
            mem[256 * 25 + count] <= INIT_19[count];
379 
            mem[256 * 26 + count] <= INIT_1A[count];
380 
            mem[256 * 27 + count] <= INIT_1B[count];
381 
            mem[256 * 28 + count] <= INIT_1C[count];
382 
            mem[256 * 29 + count] <= INIT_1D[count];
383 
            mem[256 * 30 + count] <= INIT_1E[count];
384 
            mem[256 * 31 + count] <= INIT_1F[count];
385 
            mem[256 * 32 + count] <= INIT_20[count];
386 
            mem[256 * 33 + count] <= INIT_21[count];
387 
            mem[256 * 34 + count] <= INIT_22[count];
388 
            mem[256 * 35 + count] <= INIT_23[count];
389 
            mem[256 * 36 + count] <= INIT_24[count];
390 
            mem[256 * 37 + count] <= INIT_25[count];
391 
            mem[256 * 38 + count] <= INIT_26[count];
392 
            mem[256 * 39 + count] <= INIT_27[count];
393 
            mem[256 * 40 + count] <= INIT_28[count];
394 
            mem[256 * 41 + count] <= INIT_29[count];
395 
            mem[256 * 42 + count] <= INIT_2A[count];
396 
            mem[256 * 43 + count] <= INIT_2B[count];
397 
            mem[256 * 44 + count] <= INIT_2C[count];
398 
            mem[256 * 45 + count] <= INIT_2D[count];
399 
            mem[256 * 46 + count] <= INIT_2E[count];
400 
            mem[256 * 47 + count] <= INIT_2F[count];
401 
            mem[256 * 48 + count] <= INIT_30[count];
402 
            mem[256 * 49 + count] <= INIT_31[count];
403 
            mem[256 * 50 + count] <= INIT_32[count];
404 
            mem[256 * 51 + count] <= INIT_33[count];
405 
            mem[256 * 52 + count] <= INIT_34[count];
406 
            mem[256 * 53 + count] <= INIT_35[count];
407 
            mem[256 * 54 + count] <= INIT_36[count];
408 
            mem[256 * 55 + count] <= INIT_37[count];
409 
            mem[256 * 56 + count] <= INIT_38[count];
410 
            mem[256 * 57 + count] <= INIT_39[count];
411 
            mem[256 * 58 + count] <= INIT_3A[count];
412 
            mem[256 * 59 + count] <= INIT_3B[count];
413 
            mem[256 * 60 + count] <= INIT_3C[count];
414 
            mem[256 * 61 + count] <= INIT_3D[count];
415 
            mem[256 * 62 + count] <= INIT_3E[count];
416 
            mem[256 * 63 + count] <= INIT_3F[count];
417 
            mem[256 * 64 + count] <= INITP_00[count];
418 
            mem[256 * 65 + count] <= INITP_01[count];
419 
            mem[256 * 66 + count] <= INITP_02[count];
420 
            mem[256 * 67 + count] <= INITP_03[count];
421 
            mem[256 * 68 + count] <= INITP_04[count];
422 
            mem[256 * 69 + count] <= INITP_05[count];
423 
            mem[256 * 70 + count] <= INITP_06[count];
424 
            mem[256 * 71 + count] <= INITP_07[count];
425 
        end
426 
    end
427 
 
428 
    always @(addra_int or addrb_int) begin
429 
        address_collision <= 1'b0;
430 
        for (ci = 0; ci < 16; ci = ci + 1) begin
431 
            for (cj = 0; cj < 32; cj = cj + 1) begin
432 
                if ((addra_int * 16 + ci) == (addrb_int * 32 + cj)) begin
433 
                    address_collision <= 1'b1;
434 
                end
435 
            end
436 
        end
437 
    end
438 
 
439 
    // Data
440 
    always @(posedge recovery_a or posedge recovery_b) begin
441 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
442 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
443 
            if (wea_int == 1 && web_int == 1) begin
444 
                for (dmi = 0; dmi < 16; dmi = dmi + 1) begin
445 
                    for (dmj = 0; dmj < 32; dmj = dmj + 1) begin
446 
                        if ((addra_int * 16 + dmi) == (addrb_int * 32 + dmj)) begin
447 
                            mem[addra_int * 16 + dmi] <= 1'bX;
448 
                        end
449 
                    end
450 
                end
451 
            end
452 
        end
453 
        recovery_a <= 0;
454 
        recovery_b <= 0;
455 
    end
456 
 
457 
    always @(posedge recovery_a or posedge recovery_b) begin
458 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
459 
            if (wea_int == 1 && web_int == 1) begin
460 
                for (dni = 0; dni < 16; dni = dni + 1) begin
461 
                    for (dnj = 0; dnj < 32; dnj = dnj + 1) begin
462 
                        if ((addra_int * 16 + dni) == (addrb_int * 32 + dnj)) begin
463 
                            mem[addra_int * 16 + dni] <= dia_int[dni];
464 
                        end
465 
                    end
466 
                end
467 
            end
468 
        end
469 
    end
470 
 
471 
    always @(posedge recovery_a or posedge recovery_b) begin
472 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
473 
            if (wea_int == 1 && web_int == 1) begin
474 
                for (doi = 0; doi < 16; doi = doi + 1) begin
475 
                    for (doj = 0; doj < 32; doj = doj + 1) begin
476 
                        if ((addra_int * 16 + doi) == (addrb_int * 32 + doj)) begin
477 
                            mem[addrb_int * 32 + doj] <= dib_int[doj];
478 
                        end
479 
                    end
480 
                end
481 
            end
482 
        end
483 
    end
484 
 
485 
    always @(posedge recovery_a or posedge recovery_b) begin
486 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
487 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
488 
                for (dai = 0; dai < 16; dai = dai + 1) begin
489 
                    for (daj = 0; daj < 32; daj = daj + 1) begin
490 
                        if ((addra_int * 16 + dai) == (addrb_int * 32 + daj)) begin
491 
                            doa_out[dai] <= 1'bX;
492 
                        end
493 
                    end
494 
                end
495 
            end
496 
        end
497 
    end
498 
 
499 
    always @(posedge recovery_a or posedge recovery_b) begin
500 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
501 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
502 
                for (dbi = 0; dbi < 16; dbi = dbi + 1) begin
503 
                    for (dbj = 0; dbj < 32; dbj = dbj + 1) begin
504 
                        if ((addra_int * 16 + dbi) == (addrb_int * 32 + dbj)) begin
505 
                            dob_out[dbj] <= 1'bX;
506 
                        end
507 
                    end
508 
                end
509 
            end
510 
        end
511 
    end
512 
 
513 
    always @(posedge recovery_a or posedge recovery_b) begin
514 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
515 
            (wr_mode_b == 2'b10) ||
516 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
517 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
518 
                for (dci = 0; dci < 16; dci = dci + 1) begin
519 
                    for (dcj = 0; dcj < 32; dcj = dcj + 1) begin
520 
                        if ((addra_int * 16 + dci) == (addrb_int * 32 + dcj)) begin
521 
                            doa_out[dci] <= 1'bX;
522 
                        end
523 
                    end
524 
                end
525 
            end
526 
        end
527 
    end
528 
 
529 
    always @(posedge recovery_a or posedge recovery_b) begin
530 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
531 
            (wr_mode_a == 2'b10) ||
532 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
533 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
534 
                for (ddi = 0; ddi < 16; ddi = ddi + 1) begin
535 
                    for (ddj = 0; ddj < 32; ddj = ddj + 1) begin
536 
                        if ((addra_int * 16 + ddi) == (addrb_int * 32 + ddj)) begin
537 
                            dob_out[ddj] <= 1'bX;
538 
                        end
539 
                    end
540 
                end
541 
            end
542 
        end
543 
    end
544 
 
545 
    // Parity
546 
    always @(posedge recovery_a or posedge recovery_b) begin
547 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
548 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
549 
            if (wea_int == 1 && web_int == 1) begin
550 
                for (pmi = 0; pmi < 2; pmi = pmi + 1) begin
551 
                    for (pmj = 0; pmj < 4; pmj = pmj + 1) begin
552 
                        if ((addra_int * 2 + pmi) == (addrb_int * 4 + pmj)) begin
553 
                            mem[16384 + addra_int * 2 + pmi] <= 1'bX;
554 
                        end
555 
                    end
556 
                end
557 
            end
558 
        end
559 
        recovery_a <= 0;
560 
        recovery_b <= 0;
561 
    end
562 
 
563 
    always @(posedge recovery_a or posedge recovery_b) begin
564 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
565 
            if (wea_int == 1 && web_int == 1) begin
566 
                for (pni = 0; pni < 2; pni = pni + 1) begin
567 
                    for (pnj = 0; pnj < 4; pnj = pnj + 1) begin
568 
                        if ((addra_int * 2 + pni) == (addrb_int * 4 + pnj)) begin
569 
                            mem[16384 + addra_int * 2 + pni] <= dipa_int[pni];
570 
                        end
571 
                    end
572 
                end
573 
            end
574 
        end
575 
    end
576 
 
577 
    always @(posedge recovery_a or posedge recovery_b) begin
578 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
579 
            if (wea_int == 1 && web_int == 1) begin
580 
                for (poi = 0; poi < 2; poi = poi + 1) begin
581 
                    for (poj = 0; poj < 4; poj = poj + 1) begin
582 
                        if ((addra_int * 2 + poi) == (addrb_int * 4 + poj)) begin
583 
                            mem[16384 + addrb_int * 4 + poj] <= dipb_int[poj];
584 
                        end
585 
                    end
586 
                end
587 
            end
588 
        end
589 
    end
590 
 
591 
    always @(posedge recovery_a or posedge recovery_b) begin
592 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
593 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
594 
                for (pai = 0; pai < 2; pai = pai + 1) begin
595 
                    for (paj = 0; paj < 4; paj = paj + 1) begin
596 
                        if ((addra_int * 2 + pai) == (addrb_int * 4 + paj)) begin
597 
                            dopa_out[pai] <= 1'bX;
598 
                        end
599 
                    end
600 
                end
601 
            end
602 
        end
603 
    end
604 
 
605 
    always @(posedge recovery_a or posedge recovery_b) begin
606 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
607 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
608 
                for (pbi = 0; pbi < 2; pbi = pbi + 1) begin
609 
                    for (pbj = 0; pbj < 4; pbj = pbj + 1) begin
610 
                        if ((addra_int * 2 + pbi) == (addrb_int * 4 + pbj)) begin
611 
                            dopb_out[pbj] <= 1'bX;
612 
                        end
613 
                    end
614 
                end
615 
            end
616 
        end
617 
    end
618 
 
619 
    always @(posedge recovery_a or posedge recovery_b) begin
620 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
621 
            (wr_mode_b == 2'b10) ||
622 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
623 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
624 
                for (pci = 0; pci < 2; pci = pci + 1) begin
625 
                    for (pcj = 0; pcj < 4; pcj = pcj + 1) begin
626 
                        if ((addra_int * 2 + pci) == (addrb_int * 4 + pcj)) begin
627 
                            dopa_out[pci] <= 1'bX;
628 
                        end
629 
                    end
630 
                end
631 
            end
632 
        end
633 
    end
634 
 
635 
    always @(posedge recovery_a or posedge recovery_b) begin
636 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
637 
            (wr_mode_a == 2'b10) ||
638 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
639 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
640 
                for (pdi = 0; pdi < 2; pdi = pdi + 1) begin
641 
                    for (pdj = 0; pdj < 4; pdj = pdj + 1) begin
642 
                        if ((addra_int * 2 + pdi) == (addrb_int * 4 + pdj)) begin
643 
                            dopb_out[pdj] <= 1'bX;
644 
                        end
645 
                    end
646 
                end
647 
            end
648 
        end
649 
    end
650 
 
651 
    initial begin
652 
        case (WRITE_MODE_A)
653 
            "WRITE_FIRST" : wr_mode_a <= 2'b00;
654 
            "READ_FIRST"  : wr_mode_a <= 2'b01;
655 
            "NO_CHANGE"   : wr_mode_a <= 2'b10;
656 
            default       : begin
657 
                                $display("Error : WRITE_MODE_A = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
658 
                                $finish;
659 
                            end
660 
        endcase
661 
    end
662 
 
663 
    initial begin
664 
        case (WRITE_MODE_B)
665 
            "WRITE_FIRST" : wr_mode_b <= 2'b00;
666 
            "READ_FIRST"  : wr_mode_b <= 2'b01;
667 
            "NO_CHANGE"   : wr_mode_b <= 2'b10;
668 
            default       : begin
669 
                                $display("Error : WRITE_MODE_B = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
670 
                                $finish;
671 
                            end
672 
        endcase
673 
    end
674 
 
675 
    // Port A
676 
    always @(posedge clka_int) begin
677 
        if (ena_int == 1'b1) begin
678 
            if (ssra_int == 1'b1) begin
679 
                doa_out[0] <= SRVAL_A[0];
680 
                doa_out[1] <= SRVAL_A[1];
681 
                doa_out[2] <= SRVAL_A[2];
682 
                doa_out[3] <= SRVAL_A[3];
683 
                doa_out[4] <= SRVAL_A[4];
684 
                doa_out[5] <= SRVAL_A[5];
685 
                doa_out[6] <= SRVAL_A[6];
686 
                doa_out[7] <= SRVAL_A[7];
687 
                doa_out[8] <= SRVAL_A[8];
688 
                doa_out[9] <= SRVAL_A[9];
689 
                doa_out[10] <= SRVAL_A[10];
690 
                doa_out[11] <= SRVAL_A[11];
691 
                doa_out[12] <= SRVAL_A[12];
692 
                doa_out[13] <= SRVAL_A[13];
693 
                doa_out[14] <= SRVAL_A[14];
694 
                doa_out[15] <= SRVAL_A[15];
695 
                dopa_out[0] <= SRVAL_A[16];
696 
                dopa_out[1] <= SRVAL_A[17];
697 
            end
698 
            else begin
699 
                if (wea_int == 1'b1) begin
700 
                    if (wr_mode_a == 2'b00) begin
701 
                        doa_out[0] <= dia_int[0];
702 
                        doa_out[1] <= dia_int[1];
703 
                        doa_out[2] <= dia_int[2];
704 
                        doa_out[3] <= dia_int[3];
705 
                        doa_out[4] <= dia_int[4];
706 
                        doa_out[5] <= dia_int[5];
707 
                        doa_out[6] <= dia_int[6];
708 
                        doa_out[7] <= dia_int[7];
709 
                        doa_out[8] <= dia_int[8];
710 
                        doa_out[9] <= dia_int[9];
711 
                        doa_out[10] <= dia_int[10];
712 
                        doa_out[11] <= dia_int[11];
713 
                        doa_out[12] <= dia_int[12];
714 
                        doa_out[13] <= dia_int[13];
715 
                        doa_out[14] <= dia_int[14];
716 
                        doa_out[15] <= dia_int[15];
717 
                        dopa_out[0] <= dipa_int[0];
718 
                        dopa_out[1] <= dipa_int[1];
719 
                    end
720 
                    else if (wr_mode_a == 2'b01) begin
721 
                        doa_out[0] <= mem[addra_int * 16 + 0];
722 
                        doa_out[1] <= mem[addra_int * 16 + 1];
723 
                        doa_out[2] <= mem[addra_int * 16 + 2];
724 
                        doa_out[3] <= mem[addra_int * 16 + 3];
725 
                        doa_out[4] <= mem[addra_int * 16 + 4];
726 
                        doa_out[5] <= mem[addra_int * 16 + 5];
727 
                        doa_out[6] <= mem[addra_int * 16 + 6];
728 
                        doa_out[7] <= mem[addra_int * 16 + 7];
729 
                        doa_out[8] <= mem[addra_int * 16 + 8];
730 
                        doa_out[9] <= mem[addra_int * 16 + 9];
731 
                        doa_out[10] <= mem[addra_int * 16 + 10];
732 
                        doa_out[11] <= mem[addra_int * 16 + 11];
733 
                        doa_out[12] <= mem[addra_int * 16 + 12];
734 
                        doa_out[13] <= mem[addra_int * 16 + 13];
735 
                        doa_out[14] <= mem[addra_int * 16 + 14];
736 
                        doa_out[15] <= mem[addra_int * 16 + 15];
737 
                        dopa_out[0] <= mem[16384 + addra_int * 2 + 0];
738 
                        dopa_out[1] <= mem[16384 + addra_int * 2 + 1];
739 
                    end
740 
                    else begin
741 
                        doa_out[0] <= doa_out[0];
742 
                        doa_out[1] <= doa_out[1];
743 
                        doa_out[2] <= doa_out[2];
744 
                        doa_out[3] <= doa_out[3];
745 
                        doa_out[4] <= doa_out[4];
746 
                        doa_out[5] <= doa_out[5];
747 
                        doa_out[6] <= doa_out[6];
748 
                        doa_out[7] <= doa_out[7];
749 
                        doa_out[8] <= doa_out[8];
750 
                        doa_out[9] <= doa_out[9];
751 
                        doa_out[10] <= doa_out[10];
752 
                        doa_out[11] <= doa_out[11];
753 
                        doa_out[12] <= doa_out[12];
754 
                        doa_out[13] <= doa_out[13];
755 
                        doa_out[14] <= doa_out[14];
756 
                        doa_out[15] <= doa_out[15];
757 
                        dopa_out[0] <= dopa_out[0];
758 
                        dopa_out[1] <= dopa_out[1];
759 
                    end
760 
                end
761 
                else begin
762 
                    doa_out[0] <= mem[addra_int * 16 + 0];
763 
                    doa_out[1] <= mem[addra_int * 16 + 1];
764 
                    doa_out[2] <= mem[addra_int * 16 + 2];
765 
                    doa_out[3] <= mem[addra_int * 16 + 3];
766 
                    doa_out[4] <= mem[addra_int * 16 + 4];
767 
                    doa_out[5] <= mem[addra_int * 16 + 5];
768 
                    doa_out[6] <= mem[addra_int * 16 + 6];
769 
                    doa_out[7] <= mem[addra_int * 16 + 7];
770 
                    doa_out[8] <= mem[addra_int * 16 + 8];
771 
                    doa_out[9] <= mem[addra_int * 16 + 9];
772 
                    doa_out[10] <= mem[addra_int * 16 + 10];
773 
                    doa_out[11] <= mem[addra_int * 16 + 11];
774 
                    doa_out[12] <= mem[addra_int * 16 + 12];
775 
                    doa_out[13] <= mem[addra_int * 16 + 13];
776 
                    doa_out[14] <= mem[addra_int * 16 + 14];
777 
                    doa_out[15] <= mem[addra_int * 16 + 15];
778 
                    dopa_out[0] <= mem[16384 + addra_int * 2 + 0];
779 
                    dopa_out[1] <= mem[16384 + addra_int * 2 + 1];
780 
                end
781 
            end
782 
        end
783 
    end
784 
 
785 
    always @(posedge clka_int) begin
786 
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
787 
            mem[addra_int * 16 + 0] <= dia_int[0];
788 
            mem[addra_int * 16 + 1] <= dia_int[1];
789 
            mem[addra_int * 16 + 2] <= dia_int[2];
790 
            mem[addra_int * 16 + 3] <= dia_int[3];
791 
            mem[addra_int * 16 + 4] <= dia_int[4];
792 
            mem[addra_int * 16 + 5] <= dia_int[5];
793 
            mem[addra_int * 16 + 6] <= dia_int[6];
794 
            mem[addra_int * 16 + 7] <= dia_int[7];
795 
            mem[addra_int * 16 + 8] <= dia_int[8];
796 
            mem[addra_int * 16 + 9] <= dia_int[9];
797 
            mem[addra_int * 16 + 10] <= dia_int[10];
798 
            mem[addra_int * 16 + 11] <= dia_int[11];
799 
            mem[addra_int * 16 + 12] <= dia_int[12];
800 
            mem[addra_int * 16 + 13] <= dia_int[13];
801 
            mem[addra_int * 16 + 14] <= dia_int[14];
802 
            mem[addra_int * 16 + 15] <= dia_int[15];
803 
            mem[16384 + addra_int * 2 + 0] <= dipa_int[0];
804 
            mem[16384 + addra_int * 2 + 1] <= dipa_int[1];
805 
        end
806 
    end
807 
 
808 
    // Port B
809 
    always @(posedge clkb_int) begin
810 
        if (enb_int == 1'b1) begin
811 
            if (ssrb_int == 1'b1) begin
812 
                dob_out[0] <= SRVAL_B[0];
813 
                dob_out[1] <= SRVAL_B[1];
814 
                dob_out[2] <= SRVAL_B[2];
815 
                dob_out[3] <= SRVAL_B[3];
816 
                dob_out[4] <= SRVAL_B[4];
817 
                dob_out[5] <= SRVAL_B[5];
818 
                dob_out[6] <= SRVAL_B[6];
819 
                dob_out[7] <= SRVAL_B[7];
820 
                dob_out[8] <= SRVAL_B[8];
821 
                dob_out[9] <= SRVAL_B[9];
822 
                dob_out[10] <= SRVAL_B[10];
823 
                dob_out[11] <= SRVAL_B[11];
824 
                dob_out[12] <= SRVAL_B[12];
825 
                dob_out[13] <= SRVAL_B[13];
826 
                dob_out[14] <= SRVAL_B[14];
827 
                dob_out[15] <= SRVAL_B[15];
828 
                dob_out[16] <= SRVAL_B[16];
829 
                dob_out[17] <= SRVAL_B[17];
830 
                dob_out[18] <= SRVAL_B[18];
831 
                dob_out[19] <= SRVAL_B[19];
832 
                dob_out[20] <= SRVAL_B[20];
833 
                dob_out[21] <= SRVAL_B[21];
834 
                dob_out[22] <= SRVAL_B[22];
835 
                dob_out[23] <= SRVAL_B[23];
836 
                dob_out[24] <= SRVAL_B[24];
837 
                dob_out[25] <= SRVAL_B[25];
838 
                dob_out[26] <= SRVAL_B[26];
839 
                dob_out[27] <= SRVAL_B[27];
840 
                dob_out[28] <= SRVAL_B[28];
841 
                dob_out[29] <= SRVAL_B[29];
842 
                dob_out[30] <= SRVAL_B[30];
843 
                dob_out[31] <= SRVAL_B[31];
844 
                dopb_out[0] <= SRVAL_B[32];
845 
                dopb_out[1] <= SRVAL_B[33];
846 
                dopb_out[2] <= SRVAL_B[34];
847 
                dopb_out[3] <= SRVAL_B[35];
848 
            end
849 
            else begin
850 
                if (web_int == 1'b1) begin
851 
                    if (wr_mode_b == 2'b00) begin
852 
                        dob_out[0] <= dib_int[0];
853 
                        dob_out[1] <= dib_int[1];
854 
                        dob_out[2] <= dib_int[2];
855 
                        dob_out[3] <= dib_int[3];
856 
                        dob_out[4] <= dib_int[4];
857 
                        dob_out[5] <= dib_int[5];
858 
                        dob_out[6] <= dib_int[6];
859 
                        dob_out[7] <= dib_int[7];
860 
                        dob_out[8] <= dib_int[8];
861 
                        dob_out[9] <= dib_int[9];
862 
                        dob_out[10] <= dib_int[10];
863 
                        dob_out[11] <= dib_int[11];
864 
                        dob_out[12] <= dib_int[12];
865 
                        dob_out[13] <= dib_int[13];
866 
                        dob_out[14] <= dib_int[14];
867 
                        dob_out[15] <= dib_int[15];
868 
                        dob_out[16] <= dib_int[16];
869 
                        dob_out[17] <= dib_int[17];
870 
                        dob_out[18] <= dib_int[18];
871 
                        dob_out[19] <= dib_int[19];
872 
                        dob_out[20] <= dib_int[20];
873 
                        dob_out[21] <= dib_int[21];
874 
                        dob_out[22] <= dib_int[22];
875 
                        dob_out[23] <= dib_int[23];
876 
                        dob_out[24] <= dib_int[24];
877 
                        dob_out[25] <= dib_int[25];
878 
                        dob_out[26] <= dib_int[26];
879 
                        dob_out[27] <= dib_int[27];
880 
                        dob_out[28] <= dib_int[28];
881 
                        dob_out[29] <= dib_int[29];
882 
                        dob_out[30] <= dib_int[30];
883 
                        dob_out[31] <= dib_int[31];
884 
                        dopb_out[0] <= dipb_int[0];
885 
                        dopb_out[1] <= dipb_int[1];
886 
                        dopb_out[2] <= dipb_int[2];
887 
                        dopb_out[3] <= dipb_int[3];
888 
                    end
889 
                    else if (wr_mode_b == 2'b01) begin
890 
                        dob_out[0] <= mem[addrb_int * 32 + 0];
891 
                        dob_out[1] <= mem[addrb_int * 32 + 1];
892 
                        dob_out[2] <= mem[addrb_int * 32 + 2];
893 
                        dob_out[3] <= mem[addrb_int * 32 + 3];
894 
                        dob_out[4] <= mem[addrb_int * 32 + 4];
895 
                        dob_out[5] <= mem[addrb_int * 32 + 5];
896 
                        dob_out[6] <= mem[addrb_int * 32 + 6];
897 
                        dob_out[7] <= mem[addrb_int * 32 + 7];
898 
                        dob_out[8] <= mem[addrb_int * 32 + 8];
899 
                        dob_out[9] <= mem[addrb_int * 32 + 9];
900 
                        dob_out[10] <= mem[addrb_int * 32 + 10];
901 
                        dob_out[11] <= mem[addrb_int * 32 + 11];
902 
                        dob_out[12] <= mem[addrb_int * 32 + 12];
903 
                        dob_out[13] <= mem[addrb_int * 32 + 13];
904 
                        dob_out[14] <= mem[addrb_int * 32 + 14];
905 
                        dob_out[15] <= mem[addrb_int * 32 + 15];
906 
                        dob_out[16] <= mem[addrb_int * 32 + 16];
907 
                        dob_out[17] <= mem[addrb_int * 32 + 17];
908 
                        dob_out[18] <= mem[addrb_int * 32 + 18];
909 
                        dob_out[19] <= mem[addrb_int * 32 + 19];
910 
                        dob_out[20] <= mem[addrb_int * 32 + 20];
911 
                        dob_out[21] <= mem[addrb_int * 32 + 21];
912 
                        dob_out[22] <= mem[addrb_int * 32 + 22];
913 
                        dob_out[23] <= mem[addrb_int * 32 + 23];
914 
                        dob_out[24] <= mem[addrb_int * 32 + 24];
915 
                        dob_out[25] <= mem[addrb_int * 32 + 25];
916 
                        dob_out[26] <= mem[addrb_int * 32 + 26];
917 
                        dob_out[27] <= mem[addrb_int * 32 + 27];
918 
                        dob_out[28] <= mem[addrb_int * 32 + 28];
919 
                        dob_out[29] <= mem[addrb_int * 32 + 29];
920 
                        dob_out[30] <= mem[addrb_int * 32 + 30];
921 
                        dob_out[31] <= mem[addrb_int * 32 + 31];
922 
                        dopb_out[0] <= mem[16384 + addrb_int * 4 + 0];
923 
                        dopb_out[1] <= mem[16384 + addrb_int * 4 + 1];
924 
                        dopb_out[2] <= mem[16384 + addrb_int * 4 + 2];
925 
                        dopb_out[3] <= mem[16384 + addrb_int * 4 + 3];
926 
                    end
927 
                    else begin
928 
                        dob_out[0] <= dob_out[0];
929 
                        dob_out[1] <= dob_out[1];
930 
                        dob_out[2] <= dob_out[2];
931 
                        dob_out[3] <= dob_out[3];
932 
                        dob_out[4] <= dob_out[4];
933 
                        dob_out[5] <= dob_out[5];
934 
                        dob_out[6] <= dob_out[6];
935 
                        dob_out[7] <= dob_out[7];
936 
                        dob_out[8] <= dob_out[8];
937 
                        dob_out[9] <= dob_out[9];
938 
                        dob_out[10] <= dob_out[10];
939 
                        dob_out[11] <= dob_out[11];
940 
                        dob_out[12] <= dob_out[12];
941 
                        dob_out[13] <= dob_out[13];
942 
                        dob_out[14] <= dob_out[14];
943 
                        dob_out[15] <= dob_out[15];
944 
                        dob_out[16] <= dob_out[16];
945 
                        dob_out[17] <= dob_out[17];
946 
                        dob_out[18] <= dob_out[18];
947 
                        dob_out[19] <= dob_out[19];
948 
                        dob_out[20] <= dob_out[20];
949 
                        dob_out[21] <= dob_out[21];
950 
                        dob_out[22] <= dob_out[22];
951 
                        dob_out[23] <= dob_out[23];
952 
                        dob_out[24] <= dob_out[24];
953 
                        dob_out[25] <= dob_out[25];
954 
                        dob_out[26] <= dob_out[26];
955 
                        dob_out[27] <= dob_out[27];
956 
                        dob_out[28] <= dob_out[28];
957 
                        dob_out[29] <= dob_out[29];
958 
                        dob_out[30] <= dob_out[30];
959 
                        dob_out[31] <= dob_out[31];
960 
                        dopb_out[0] <= dopb_out[0];
961 
                        dopb_out[1] <= dopb_out[1];
962 
                        dopb_out[2] <= dopb_out[2];
963 
                        dopb_out[3] <= dopb_out[3];
964 
                    end
965 
                end
966 
                else begin
967 
                    dob_out[0] <= mem[addrb_int * 32 + 0];
968 
                    dob_out[1] <= mem[addrb_int * 32 + 1];
969 
                    dob_out[2] <= mem[addrb_int * 32 + 2];
970 
                    dob_out[3] <= mem[addrb_int * 32 + 3];
971 
                    dob_out[4] <= mem[addrb_int * 32 + 4];
972 
                    dob_out[5] <= mem[addrb_int * 32 + 5];
973 
                    dob_out[6] <= mem[addrb_int * 32 + 6];
974 
                    dob_out[7] <= mem[addrb_int * 32 + 7];
975 
                    dob_out[8] <= mem[addrb_int * 32 + 8];
976 
                    dob_out[9] <= mem[addrb_int * 32 + 9];
977 
                    dob_out[10] <= mem[addrb_int * 32 + 10];
978 
                    dob_out[11] <= mem[addrb_int * 32 + 11];
979 
                    dob_out[12] <= mem[addrb_int * 32 + 12];
980 
                    dob_out[13] <= mem[addrb_int * 32 + 13];
981 
                    dob_out[14] <= mem[addrb_int * 32 + 14];
982 
                    dob_out[15] <= mem[addrb_int * 32 + 15];
983 
                    dob_out[16] <= mem[addrb_int * 32 + 16];
984 
                    dob_out[17] <= mem[addrb_int * 32 + 17];
985 
                    dob_out[18] <= mem[addrb_int * 32 + 18];
986 
                    dob_out[19] <= mem[addrb_int * 32 + 19];
987 
                    dob_out[20] <= mem[addrb_int * 32 + 20];
988 
                    dob_out[21] <= mem[addrb_int * 32 + 21];
989 
                    dob_out[22] <= mem[addrb_int * 32 + 22];
990 
                    dob_out[23] <= mem[addrb_int * 32 + 23];
991 
                    dob_out[24] <= mem[addrb_int * 32 + 24];
992 
                    dob_out[25] <= mem[addrb_int * 32 + 25];
993 
                    dob_out[26] <= mem[addrb_int * 32 + 26];
994 
                    dob_out[27] <= mem[addrb_int * 32 + 27];
995 
                    dob_out[28] <= mem[addrb_int * 32 + 28];
996 
                    dob_out[29] <= mem[addrb_int * 32 + 29];
997 
                    dob_out[30] <= mem[addrb_int * 32 + 30];
998 
                    dob_out[31] <= mem[addrb_int * 32 + 31];
999 
                    dopb_out[0] <= mem[16384 + addrb_int * 4 + 0];
1000 
                    dopb_out[1] <= mem[16384 + addrb_int * 4 + 1];
1001 
                    dopb_out[2] <= mem[16384 + addrb_int * 4 + 2];
1002 
                    dopb_out[3] <= mem[16384 + addrb_int * 4 + 3];
1003 
                end
1004 
            end
1005 
        end
1006 
    end
1007 
 
1008 
    always @(posedge clkb_int) begin
1009 
        if (enb_int == 1'b1 && web_int == 1'b1) begin
1010 
            mem[addrb_int * 32 + 0] <= dib_int[0];
1011 
            mem[addrb_int * 32 + 1] <= dib_int[1];
1012 
            mem[addrb_int * 32 + 2] <= dib_int[2];
1013 
            mem[addrb_int * 32 + 3] <= dib_int[3];
1014 
            mem[addrb_int * 32 + 4] <= dib_int[4];
1015 
            mem[addrb_int * 32 + 5] <= dib_int[5];
1016 
            mem[addrb_int * 32 + 6] <= dib_int[6];
1017 
            mem[addrb_int * 32 + 7] <= dib_int[7];
1018 
            mem[addrb_int * 32 + 8] <= dib_int[8];
1019 
            mem[addrb_int * 32 + 9] <= dib_int[9];
1020 
            mem[addrb_int * 32 + 10] <= dib_int[10];
1021 
            mem[addrb_int * 32 + 11] <= dib_int[11];
1022 
            mem[addrb_int * 32 + 12] <= dib_int[12];
1023 
            mem[addrb_int * 32 + 13] <= dib_int[13];
1024 
            mem[addrb_int * 32 + 14] <= dib_int[14];
1025 
            mem[addrb_int * 32 + 15] <= dib_int[15];
1026 
            mem[addrb_int * 32 + 16] <= dib_int[16];
1027 
            mem[addrb_int * 32 + 17] <= dib_int[17];
1028 
            mem[addrb_int * 32 + 18] <= dib_int[18];
1029 
            mem[addrb_int * 32 + 19] <= dib_int[19];
1030 
            mem[addrb_int * 32 + 20] <= dib_int[20];
1031 
            mem[addrb_int * 32 + 21] <= dib_int[21];
1032 
            mem[addrb_int * 32 + 22] <= dib_int[22];
1033 
            mem[addrb_int * 32 + 23] <= dib_int[23];
1034 
            mem[addrb_int * 32 + 24] <= dib_int[24];
1035 
            mem[addrb_int * 32 + 25] <= dib_int[25];
1036 
            mem[addrb_int * 32 + 26] <= dib_int[26];
1037 
            mem[addrb_int * 32 + 27] <= dib_int[27];
1038 
            mem[addrb_int * 32 + 28] <= dib_int[28];
1039 
            mem[addrb_int * 32 + 29] <= dib_int[29];
1040 
            mem[addrb_int * 32 + 30] <= dib_int[30];
1041 
            mem[addrb_int * 32 + 31] <= dib_int[31];
1042 
            mem[16384 + addrb_int * 4 + 0] <= dipb_int[0];
1043 
            mem[16384 + addrb_int * 4 + 1] <= dipb_int[1];
1044 
            mem[16384 + addrb_int * 4 + 2] <= dipb_int[2];
1045 
            mem[16384 + addrb_int * 4 + 3] <= dipb_int[3];
1046 
        end
1047 
    end
1048 
 
1049 
    specify
1050 
        (CLKA *> DOA) = (1, 1);
1051 
        (CLKA *> DOPA) = (1, 1);
1052 
        (CLKB *> DOB) = (1, 1);
1053 
        (CLKB *> DOPB) = (1, 1);
1054 
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
1055 
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
1056 
    endspecify
1057 
 
1058 
endmodule
1059 
 
1060 
`endcelldefine

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