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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S1_S9.v] - Blame information for rev 1767

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S1_S9.v,v 1.1.1.1 2001-11-04 18:59:53 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x1x9 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S1_S9 (DOA, DOB, DOPB, ADDRA, CLKA, DIA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, DIPB, ENB, SSRB, WEB);
14 
    parameter cds_action = "ignore";
15 
    parameter INIT_A = 1'h0;
16 
    parameter INIT_B = 9'h0;
17 
    parameter SRVAL_A = 1'h0;
18 
    parameter SRVAL_B = 9'h0;
19 
    parameter WRITE_MODE_A = "WRITE_FIRST";
20 
    parameter WRITE_MODE_B = "WRITE_FIRST";
21 
 
22 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
34 
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
35 
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
36 
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37 
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38 
    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39 
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40 
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42 
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45 
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63 
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65 
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66 
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77 
    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86 
    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94 
 
95 
    output [0:0] DOA;
96 
    reg [0:0] doa_out;
97 
    wire doa_out0;
98 
 
99 
    input [13:0] ADDRA;
100 
    input [0:0] DIA;
101 
    input ENA, CLKA, WEA, SSRA;
102 
 
103 
    output [7:0] DOB;
104 
    output [0:0] DOPB;
105 
    reg [7:0] dob_out;
106 
    reg [0:0] dopb_out;
107 
    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7;
108 
    wire dopb0_out;
109 
 
110 
    input [10:0] ADDRB;
111 
    input [7:0] DIB;
112 
    input [0:0] DIPB;
113 
    input ENB, CLKB, WEB, SSRB;
114 
 
115 
    reg [18431:0] mem;
116 
    reg [8:0] count;
117 
    reg [1:0] wr_mode_a, wr_mode_b;
118 
 
119 
    reg [5:0] ci, cj;
120 
    reg [5:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
121 
    reg [5:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
122 
 
123 
    wire [13:0] addra_int;
124 
    wire [0:0] dia_int;
125 
    wire ena_int, clka_int, wea_int, ssra_int;
126 
    wire [10:0] addrb_int;
127 
    wire [7:0] dib_int;
128 
    wire [0:0] dipb_int;
129 
    wire enb_int, clkb_int, web_int, ssrb_int;
130 
 
131 
    reg recovery_a, recovery_b;
132 
    reg address_collision;
133 
 
134 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
135 
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
136 
    wire collision = clka_enable || clkb_enable;
137 
 
138 
    tri0 GSR = glbl.GSR;
139 
 
140 
    always @(GSR)
141 
        if (GSR) begin
142 
            assign doa_out = INIT_A[0:0];
143 
            assign dob_out = INIT_B[7:0];
144 
            assign dopb_out = INIT_B[8:8];
145 
        end
146 
        else begin
147 
            deassign doa_out;
148 
            deassign dob_out;
149 
            deassign dopb_out;
150 
        end
151 
 
152 
    buf b_doa_out0 (doa_out0, doa_out[0]);
153 
    buf b_dob_out0 (dob_out0, dob_out[0]);
154 
    buf b_dob_out1 (dob_out1, dob_out[1]);
155 
    buf b_dob_out2 (dob_out2, dob_out[2]);
156 
    buf b_dob_out3 (dob_out3, dob_out[3]);
157 
    buf b_dob_out4 (dob_out4, dob_out[4]);
158 
    buf b_dob_out5 (dob_out5, dob_out[5]);
159 
    buf b_dob_out6 (dob_out6, dob_out[6]);
160 
    buf b_dob_out7 (dob_out7, dob_out[7]);
161 
    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
162 
 
163 
    buf b_doa0 (DOA[0], doa_out0);
164 
    buf b_dob0 (DOB[0], dob_out0);
165 
    buf b_dob1 (DOB[1], dob_out1);
166 
    buf b_dob2 (DOB[2], dob_out2);
167 
    buf b_dob3 (DOB[3], dob_out3);
168 
    buf b_dob4 (DOB[4], dob_out4);
169 
    buf b_dob5 (DOB[5], dob_out5);
170 
    buf b_dob6 (DOB[6], dob_out6);
171 
    buf b_dob7 (DOB[7], dob_out7);
172 
    buf b_dopb0 (DOPB[0], dopb_out0);
173 
 
174 
    buf b_addra_0 (addra_int[0], ADDRA[0]);
175 
    buf b_addra_1 (addra_int[1], ADDRA[1]);
176 
    buf b_addra_2 (addra_int[2], ADDRA[2]);
177 
    buf b_addra_3 (addra_int[3], ADDRA[3]);
178 
    buf b_addra_4 (addra_int[4], ADDRA[4]);
179 
    buf b_addra_5 (addra_int[5], ADDRA[5]);
180 
    buf b_addra_6 (addra_int[6], ADDRA[6]);
181 
    buf b_addra_7 (addra_int[7], ADDRA[7]);
182 
    buf b_addra_8 (addra_int[8], ADDRA[8]);
183 
    buf b_addra_9 (addra_int[9], ADDRA[9]);
184 
    buf b_addra_10 (addra_int[10], ADDRA[10]);
185 
    buf b_addra_11 (addra_int[11], ADDRA[11]);
186 
    buf b_addra_12 (addra_int[12], ADDRA[12]);
187 
    buf b_addra_13 (addra_int[13], ADDRA[13]);
188 
    buf b_dia_0 (dia_int[0], DIA[0]);
189 
    buf b_ena (ena_int, ENA);
190 
    buf b_clka (clka_int, CLKA);
191 
    buf b_ssra (ssra_int, SSRA);
192 
    buf b_wea (wea_int, WEA);
193 
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
194 
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
195 
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
196 
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
197 
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
198 
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
199 
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
200 
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
201 
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
202 
    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
203 
    buf b_addrb_10 (addrb_int[10], ADDRB[10]);
204 
    buf b_dib_0 (dib_int[0], DIB[0]);
205 
    buf b_dib_1 (dib_int[1], DIB[1]);
206 
    buf b_dib_2 (dib_int[2], DIB[2]);
207 
    buf b_dib_3 (dib_int[3], DIB[3]);
208 
    buf b_dib_4 (dib_int[4], DIB[4]);
209 
    buf b_dib_5 (dib_int[5], DIB[5]);
210 
    buf b_dib_6 (dib_int[6], DIB[6]);
211 
    buf b_dib_7 (dib_int[7], DIB[7]);
212 
    buf b_dipb_0 (dipb_int[0], DIPB[0]);
213 
    buf b_enb (enb_int, ENB);
214 
    buf b_clkb (clkb_int, CLKB);
215 
    buf b_ssrb (ssrb_int, SSRB);
216 
    buf b_web (web_int, WEB);
217 
 
218 
    initial begin
219 
        for (count = 0; count < 256; count = count + 1) begin
220 
            mem[count]            <= INIT_00[count];
221 
            mem[256 * 1 + count]  <= INIT_01[count];
222 
            mem[256 * 2 + count]  <= INIT_02[count];
223 
            mem[256 * 3 + count]  <= INIT_03[count];
224 
            mem[256 * 4 + count]  <= INIT_04[count];
225 
            mem[256 * 5 + count]  <= INIT_05[count];
226 
            mem[256 * 6 + count]  <= INIT_06[count];
227 
            mem[256 * 7 + count]  <= INIT_07[count];
228 
            mem[256 * 8 + count]  <= INIT_08[count];
229 
            mem[256 * 9 + count]  <= INIT_09[count];
230 
            mem[256 * 10 + count] <= INIT_0A[count];
231 
            mem[256 * 11 + count] <= INIT_0B[count];
232 
            mem[256 * 12 + count] <= INIT_0C[count];
233 
            mem[256 * 13 + count] <= INIT_0D[count];
234 
            mem[256 * 14 + count] <= INIT_0E[count];
235 
            mem[256 * 15 + count] <= INIT_0F[count];
236 
            mem[256 * 16 + count] <= INIT_10[count];
237 
            mem[256 * 17 + count] <= INIT_11[count];
238 
            mem[256 * 18 + count] <= INIT_12[count];
239 
            mem[256 * 19 + count] <= INIT_13[count];
240 
            mem[256 * 20 + count] <= INIT_14[count];
241 
            mem[256 * 21 + count] <= INIT_15[count];
242 
            mem[256 * 22 + count] <= INIT_16[count];
243 
            mem[256 * 23 + count] <= INIT_17[count];
244 
            mem[256 * 24 + count] <= INIT_18[count];
245 
            mem[256 * 25 + count] <= INIT_19[count];
246 
            mem[256 * 26 + count] <= INIT_1A[count];
247 
            mem[256 * 27 + count] <= INIT_1B[count];
248 
            mem[256 * 28 + count] <= INIT_1C[count];
249 
            mem[256 * 29 + count] <= INIT_1D[count];
250 
            mem[256 * 30 + count] <= INIT_1E[count];
251 
            mem[256 * 31 + count] <= INIT_1F[count];
252 
            mem[256 * 32 + count] <= INIT_20[count];
253 
            mem[256 * 33 + count] <= INIT_21[count];
254 
            mem[256 * 34 + count] <= INIT_22[count];
255 
            mem[256 * 35 + count] <= INIT_23[count];
256 
            mem[256 * 36 + count] <= INIT_24[count];
257 
            mem[256 * 37 + count] <= INIT_25[count];
258 
            mem[256 * 38 + count] <= INIT_26[count];
259 
            mem[256 * 39 + count] <= INIT_27[count];
260 
            mem[256 * 40 + count] <= INIT_28[count];
261 
            mem[256 * 41 + count] <= INIT_29[count];
262 
            mem[256 * 42 + count] <= INIT_2A[count];
263 
            mem[256 * 43 + count] <= INIT_2B[count];
264 
            mem[256 * 44 + count] <= INIT_2C[count];
265 
            mem[256 * 45 + count] <= INIT_2D[count];
266 
            mem[256 * 46 + count] <= INIT_2E[count];
267 
            mem[256 * 47 + count] <= INIT_2F[count];
268 
            mem[256 * 48 + count] <= INIT_30[count];
269 
            mem[256 * 49 + count] <= INIT_31[count];
270 
            mem[256 * 50 + count] <= INIT_32[count];
271 
            mem[256 * 51 + count] <= INIT_33[count];
272 
            mem[256 * 52 + count] <= INIT_34[count];
273 
            mem[256 * 53 + count] <= INIT_35[count];
274 
            mem[256 * 54 + count] <= INIT_36[count];
275 
            mem[256 * 55 + count] <= INIT_37[count];
276 
            mem[256 * 56 + count] <= INIT_38[count];
277 
            mem[256 * 57 + count] <= INIT_39[count];
278 
            mem[256 * 58 + count] <= INIT_3A[count];
279 
            mem[256 * 59 + count] <= INIT_3B[count];
280 
            mem[256 * 60 + count] <= INIT_3C[count];
281 
            mem[256 * 61 + count] <= INIT_3D[count];
282 
            mem[256 * 62 + count] <= INIT_3E[count];
283 
            mem[256 * 63 + count] <= INIT_3F[count];
284 
            mem[256 * 64 + count] <= INITP_00[count];
285 
            mem[256 * 65 + count] <= INITP_01[count];
286 
            mem[256 * 66 + count] <= INITP_02[count];
287 
            mem[256 * 67 + count] <= INITP_03[count];
288 
            mem[256 * 68 + count] <= INITP_04[count];
289 
            mem[256 * 69 + count] <= INITP_05[count];
290 
            mem[256 * 70 + count] <= INITP_06[count];
291 
            mem[256 * 71 + count] <= INITP_07[count];
292 
        end
293 
    end
294 
 
295 
    always @(addra_int or addrb_int) begin
296 
        address_collision <= 1'b0;
297 
        for (ci = 0; ci < 1; ci = ci + 1) begin
298 
            for (cj = 0; cj < 8; cj = cj + 1) begin
299 
                if ((addra_int * 1 + ci) == (addrb_int * 8 + cj)) begin
300 
                    address_collision <= 1'b1;
301 
                end
302 
            end
303 
        end
304 
    end
305 
 
306 
    // Data
307 
    always @(posedge recovery_a or posedge recovery_b) begin
308 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
309 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
310 
            if (wea_int == 1 && web_int == 1) begin
311 
                for (dmi = 0; dmi < 1; dmi = dmi + 1) begin
312 
                    for (dmj = 0; dmj < 8; dmj = dmj + 1) begin
313 
                        if ((addra_int * 1 + dmi) == (addrb_int * 8 + dmj)) begin
314 
                            mem[addra_int * 1 + dmi] <= 1'bX;
315 
                        end
316 
                    end
317 
                end
318 
            end
319 
        end
320 
        recovery_a <= 0;
321 
        recovery_b <= 0;
322 
    end
323 
 
324 
    always @(posedge recovery_a or posedge recovery_b) begin
325 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
326 
            if (wea_int == 1 && web_int == 1) begin
327 
                for (dni = 0; dni < 1; dni = dni + 1) begin
328 
                    for (dnj = 0; dnj < 8; dnj = dnj + 1) begin
329 
                        if ((addra_int * 1 + dni) == (addrb_int * 8 + dnj)) begin
330 
                            mem[addra_int * 1 + dni] <= dia_int[dni];
331 
                        end
332 
                    end
333 
                end
334 
            end
335 
        end
336 
    end
337 
 
338 
    always @(posedge recovery_a or posedge recovery_b) begin
339 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
340 
            if (wea_int == 1 && web_int == 1) begin
341 
                for (doi = 0; doi < 1; doi = doi + 1) begin
342 
                    for (doj = 0; doj < 8; doj = doj + 1) begin
343 
                        if ((addra_int * 1 + doi) == (addrb_int * 8 + doj)) begin
344 
                            mem[addrb_int * 8 + doj] <= dib_int[doj];
345 
                        end
346 
                    end
347 
                end
348 
            end
349 
        end
350 
    end
351 
 
352 
    always @(posedge recovery_a or posedge recovery_b) begin
353 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
354 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
355 
                for (dai = 0; dai < 1; dai = dai + 1) begin
356 
                    for (daj = 0; daj < 8; daj = daj + 1) begin
357 
                        if ((addra_int * 1 + dai) == (addrb_int * 8 + daj)) begin
358 
                            doa_out[dai] <= 1'bX;
359 
                        end
360 
                    end
361 
                end
362 
            end
363 
        end
364 
    end
365 
 
366 
    always @(posedge recovery_a or posedge recovery_b) begin
367 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
368 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
369 
                for (dbi = 0; dbi < 1; dbi = dbi + 1) begin
370 
                    for (dbj = 0; dbj < 8; dbj = dbj + 1) begin
371 
                        if ((addra_int * 1 + dbi) == (addrb_int * 8 + dbj)) begin
372 
                            dob_out[dbj] <= 1'bX;
373 
                        end
374 
                    end
375 
                end
376 
            end
377 
        end
378 
    end
379 
 
380 
    always @(posedge recovery_a or posedge recovery_b) begin
381 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
382 
            (wr_mode_b == 2'b10) ||
383 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
384 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
385 
                for (dci = 0; dci < 1; dci = dci + 1) begin
386 
                    for (dcj = 0; dcj < 8; dcj = dcj + 1) begin
387 
                        if ((addra_int * 1 + dci) == (addrb_int * 8 + dcj)) begin
388 
                            doa_out[dci] <= 1'bX;
389 
                        end
390 
                    end
391 
                end
392 
            end
393 
        end
394 
    end
395 
 
396 
    always @(posedge recovery_a or posedge recovery_b) begin
397 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
398 
            (wr_mode_a == 2'b10) ||
399 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
400 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
401 
                for (ddi = 0; ddi < 1; ddi = ddi + 1) begin
402 
                    for (ddj = 0; ddj < 8; ddj = ddj + 1) begin
403 
                        if ((addra_int * 1 + ddi) == (addrb_int * 8 + ddj)) begin
404 
                            dob_out[ddj] <= 1'bX;
405 
                        end
406 
                    end
407 
                end
408 
            end
409 
        end
410 
    end
411 
 
412 
    initial begin
413 
        case (WRITE_MODE_A)
414 
            "WRITE_FIRST" : wr_mode_a <= 2'b00;
415 
            "READ_FIRST"  : wr_mode_a <= 2'b01;
416 
            "NO_CHANGE"   : wr_mode_a <= 2'b10;
417 
            default       : begin
418 
                                $display("Error : WRITE_MODE_A = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
419 
                                $finish;
420 
                            end
421 
        endcase
422 
    end
423 
 
424 
    initial begin
425 
        case (WRITE_MODE_B)
426 
            "WRITE_FIRST" : wr_mode_b <= 2'b00;
427 
            "READ_FIRST"  : wr_mode_b <= 2'b01;
428 
            "NO_CHANGE"   : wr_mode_b <= 2'b10;
429 
            default       : begin
430 
                                $display("Error : WRITE_MODE_B = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
431 
                                $finish;
432 
                            end
433 
        endcase
434 
    end
435 
 
436 
    // Port A
437 
    always @(posedge clka_int) begin
438 
        if (ena_int == 1'b1) begin
439 
            if (ssra_int == 1'b1) begin
440 
                doa_out[0] <= SRVAL_A[0];
441 
            end
442 
            else begin
443 
                if (wea_int == 1'b1) begin
444 
                    if (wr_mode_a == 2'b00) begin
445 
                        doa_out[0] <= dia_int[0];
446 
                    end
447 
                    else if (wr_mode_a == 2'b01) begin
448 
                        doa_out[0] <= mem[addra_int * 1 + 0];
449 
                    end
450 
                    else begin
451 
                        doa_out[0] <= doa_out[0];
452 
                    end
453 
                end
454 
                else begin
455 
                    doa_out[0] <= mem[addra_int * 1 + 0];
456 
                end
457 
            end
458 
        end
459 
    end
460 
 
461 
    always @(posedge clka_int) begin
462 
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
463 
            mem[addra_int * 1 + 0] <= dia_int[0];
464 
        end
465 
    end
466 
 
467 
    // Port B
468 
    always @(posedge clkb_int) begin
469 
        if (enb_int == 1'b1) begin
470 
            if (ssrb_int == 1'b1) begin
471 
                dob_out[0] <= SRVAL_B[0];
472 
                dob_out[1] <= SRVAL_B[1];
473 
                dob_out[2] <= SRVAL_B[2];
474 
                dob_out[3] <= SRVAL_B[3];
475 
                dob_out[4] <= SRVAL_B[4];
476 
                dob_out[5] <= SRVAL_B[5];
477 
                dob_out[6] <= SRVAL_B[6];
478 
                dob_out[7] <= SRVAL_B[7];
479 
                dopb_out[0] <= SRVAL_B[8];
480 
            end
481 
            else begin
482 
                if (web_int == 1'b1) begin
483 
                    if (wr_mode_b == 2'b00) begin
484 
                        dob_out[0] <= dib_int[0];
485 
                        dob_out[1] <= dib_int[1];
486 
                        dob_out[2] <= dib_int[2];
487 
                        dob_out[3] <= dib_int[3];
488 
                        dob_out[4] <= dib_int[4];
489 
                        dob_out[5] <= dib_int[5];
490 
                        dob_out[6] <= dib_int[6];
491 
                        dob_out[7] <= dib_int[7];
492 
                        dopb_out[0] <= dipb_int[0];
493 
                    end
494 
                    else if (wr_mode_b == 2'b01) begin
495 
                        dob_out[0] <= mem[addrb_int * 8 + 0];
496 
                        dob_out[1] <= mem[addrb_int * 8 + 1];
497 
                        dob_out[2] <= mem[addrb_int * 8 + 2];
498 
                        dob_out[3] <= mem[addrb_int * 8 + 3];
499 
                        dob_out[4] <= mem[addrb_int * 8 + 4];
500 
                        dob_out[5] <= mem[addrb_int * 8 + 5];
501 
                        dob_out[6] <= mem[addrb_int * 8 + 6];
502 
                        dob_out[7] <= mem[addrb_int * 8 + 7];
503 
                        dopb_out[0] <= mem[16384 + addrb_int * 1 + 0];
504 
                    end
505 
                    else begin
506 
                        dob_out[0] <= dob_out[0];
507 
                        dob_out[1] <= dob_out[1];
508 
                        dob_out[2] <= dob_out[2];
509 
                        dob_out[3] <= dob_out[3];
510 
                        dob_out[4] <= dob_out[4];
511 
                        dob_out[5] <= dob_out[5];
512 
                        dob_out[6] <= dob_out[6];
513 
                        dob_out[7] <= dob_out[7];
514 
                        dopb_out[0] <= dopb_out[0];
515 
                    end
516 
                end
517 
                else begin
518 
                    dob_out[0] <= mem[addrb_int * 8 + 0];
519 
                    dob_out[1] <= mem[addrb_int * 8 + 1];
520 
                    dob_out[2] <= mem[addrb_int * 8 + 2];
521 
                    dob_out[3] <= mem[addrb_int * 8 + 3];
522 
                    dob_out[4] <= mem[addrb_int * 8 + 4];
523 
                    dob_out[5] <= mem[addrb_int * 8 + 5];
524 
                    dob_out[6] <= mem[addrb_int * 8 + 6];
525 
                    dob_out[7] <= mem[addrb_int * 8 + 7];
526 
                    dopb_out[0] <= mem[16384 + addrb_int * 1 + 0];
527 
                end
528 
            end
529 
        end
530 
    end
531 
 
532 
    always @(posedge clkb_int) begin
533 
        if (enb_int == 1'b1 && web_int == 1'b1) begin
534 
            mem[addrb_int * 8 + 0] <= dib_int[0];
535 
            mem[addrb_int * 8 + 1] <= dib_int[1];
536 
            mem[addrb_int * 8 + 2] <= dib_int[2];
537 
            mem[addrb_int * 8 + 3] <= dib_int[3];
538 
            mem[addrb_int * 8 + 4] <= dib_int[4];
539 
            mem[addrb_int * 8 + 5] <= dib_int[5];
540 
            mem[addrb_int * 8 + 6] <= dib_int[6];
541 
            mem[addrb_int * 8 + 7] <= dib_int[7];
542 
            mem[16384 + addrb_int * 1 + 0] <= dipb_int[0];
543 
        end
544 
    end
545 
 
546 
    specify
547 
        (CLKA *> DOA) = (1, 1);
548 
        (CLKB *> DOB) = (1, 1);
549 
        (CLKB *> DOPB) = (1, 1);
550 
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
551 
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
552 
    endspecify
553 
 
554 
endmodule
555 
 
556 
`endcelldefine

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