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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S2_S2.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S2_S2.v,v 1.1.1.1 2001-11-04 18:59:53 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x2x2 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S2_S2 (DOA, DOB, ADDRA, CLKA, DIA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, ENB, SSRB, WEB);
14 
    parameter cds_action = "ignore";
15 
    parameter INIT_A = 2'h0;
16 
    parameter INIT_B = 2'h0;
17 
    parameter SRVAL_A = 2'h0;
18 
    parameter SRVAL_B = 2'h0;
19 
    parameter WRITE_MODE_A = "WRITE_FIRST";
20 
    parameter WRITE_MODE_B = "WRITE_FIRST";
21 
 
22 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
34 
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
35 
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
36 
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37 
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38 
    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39 
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40 
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42 
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45 
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63 
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65 
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66 
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77 
    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86 
    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94 
 
95 
    output [1:0] DOA;
96 
    reg [1:0] doa_out;
97 
    wire doa_out0, doa_out1;
98 
 
99 
    input [12:0] ADDRA;
100 
    input [1:0] DIA;
101 
    input ENA, CLKA, WEA, SSRA;
102 
 
103 
    output [1:0] DOB;
104 
    reg [1:0] dob_out;
105 
    wire dob_out0, dob_out1;
106 
 
107 
    input [12:0] ADDRB;
108 
    input [1:0] DIB;
109 
    input ENB, CLKB, WEB, SSRB;
110 
 
111 
    reg [18431:0] mem;
112 
    reg [8:0] count;
113 
    reg [1:0] wr_mode_a, wr_mode_b;
114 
 
115 
    reg [5:0] ci, cj;
116 
    reg [5:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
117 
    reg [5:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
118 
 
119 
    wire [12:0] addra_int;
120 
    wire [1:0] dia_int;
121 
    wire ena_int, clka_int, wea_int, ssra_int;
122 
    wire [12:0] addrb_int;
123 
    wire [1:0] dib_int;
124 
    wire enb_int, clkb_int, web_int, ssrb_int;
125 
 
126 
    reg recovery_a, recovery_b;
127 
    reg address_collision;
128 
 
129 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
130 
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
131 
    wire collision = clka_enable || clkb_enable;
132 
 
133 
    tri0 GSR = glbl.GSR;
134 
 
135 
    always @(GSR)
136 
        if (GSR) begin
137 
            assign doa_out = INIT_A[1:0];
138 
            assign dob_out = INIT_B[1:0];
139 
        end
140 
        else begin
141 
            deassign doa_out;
142 
            deassign dob_out;
143 
        end
144 
 
145 
    buf b_doa_out0 (doa_out0, doa_out[0]);
146 
    buf b_doa_out1 (doa_out1, doa_out[1]);
147 
    buf b_dob_out0 (dob_out0, dob_out[0]);
148 
    buf b_dob_out1 (dob_out1, dob_out[1]);
149 
 
150 
    buf b_doa0 (DOA[0], doa_out0);
151 
    buf b_doa1 (DOA[1], doa_out1);
152 
    buf b_dob0 (DOB[0], dob_out0);
153 
    buf b_dob1 (DOB[1], dob_out1);
154 
 
155 
    buf b_addra_0 (addra_int[0], ADDRA[0]);
156 
    buf b_addra_1 (addra_int[1], ADDRA[1]);
157 
    buf b_addra_2 (addra_int[2], ADDRA[2]);
158 
    buf b_addra_3 (addra_int[3], ADDRA[3]);
159 
    buf b_addra_4 (addra_int[4], ADDRA[4]);
160 
    buf b_addra_5 (addra_int[5], ADDRA[5]);
161 
    buf b_addra_6 (addra_int[6], ADDRA[6]);
162 
    buf b_addra_7 (addra_int[7], ADDRA[7]);
163 
    buf b_addra_8 (addra_int[8], ADDRA[8]);
164 
    buf b_addra_9 (addra_int[9], ADDRA[9]);
165 
    buf b_addra_10 (addra_int[10], ADDRA[10]);
166 
    buf b_addra_11 (addra_int[11], ADDRA[11]);
167 
    buf b_addra_12 (addra_int[12], ADDRA[12]);
168 
    buf b_dia_0 (dia_int[0], DIA[0]);
169 
    buf b_dia_1 (dia_int[1], DIA[1]);
170 
    buf b_ena (ena_int, ENA);
171 
    buf b_clka (clka_int, CLKA);
172 
    buf b_ssra (ssra_int, SSRA);
173 
    buf b_wea (wea_int, WEA);
174 
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
175 
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
176 
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
177 
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
178 
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
179 
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
180 
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
181 
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
182 
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
183 
    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
184 
    buf b_addrb_10 (addrb_int[10], ADDRB[10]);
185 
    buf b_addrb_11 (addrb_int[11], ADDRB[11]);
186 
    buf b_addrb_12 (addrb_int[12], ADDRB[12]);
187 
    buf b_dib_0 (dib_int[0], DIB[0]);
188 
    buf b_dib_1 (dib_int[1], DIB[1]);
189 
    buf b_enb (enb_int, ENB);
190 
    buf b_clkb (clkb_int, CLKB);
191 
    buf b_ssrb (ssrb_int, SSRB);
192 
    buf b_web (web_int, WEB);
193 
 
194 
    initial begin
195 
        for (count = 0; count < 256; count = count + 1) begin
196 
            mem[count]            <= INIT_00[count];
197 
            mem[256 * 1 + count]  <= INIT_01[count];
198 
            mem[256 * 2 + count]  <= INIT_02[count];
199 
            mem[256 * 3 + count]  <= INIT_03[count];
200 
            mem[256 * 4 + count]  <= INIT_04[count];
201 
            mem[256 * 5 + count]  <= INIT_05[count];
202 
            mem[256 * 6 + count]  <= INIT_06[count];
203 
            mem[256 * 7 + count]  <= INIT_07[count];
204 
            mem[256 * 8 + count]  <= INIT_08[count];
205 
            mem[256 * 9 + count]  <= INIT_09[count];
206 
            mem[256 * 10 + count] <= INIT_0A[count];
207 
            mem[256 * 11 + count] <= INIT_0B[count];
208 
            mem[256 * 12 + count] <= INIT_0C[count];
209 
            mem[256 * 13 + count] <= INIT_0D[count];
210 
            mem[256 * 14 + count] <= INIT_0E[count];
211 
            mem[256 * 15 + count] <= INIT_0F[count];
212 
            mem[256 * 16 + count] <= INIT_10[count];
213 
            mem[256 * 17 + count] <= INIT_11[count];
214 
            mem[256 * 18 + count] <= INIT_12[count];
215 
            mem[256 * 19 + count] <= INIT_13[count];
216 
            mem[256 * 20 + count] <= INIT_14[count];
217 
            mem[256 * 21 + count] <= INIT_15[count];
218 
            mem[256 * 22 + count] <= INIT_16[count];
219 
            mem[256 * 23 + count] <= INIT_17[count];
220 
            mem[256 * 24 + count] <= INIT_18[count];
221 
            mem[256 * 25 + count] <= INIT_19[count];
222 
            mem[256 * 26 + count] <= INIT_1A[count];
223 
            mem[256 * 27 + count] <= INIT_1B[count];
224 
            mem[256 * 28 + count] <= INIT_1C[count];
225 
            mem[256 * 29 + count] <= INIT_1D[count];
226 
            mem[256 * 30 + count] <= INIT_1E[count];
227 
            mem[256 * 31 + count] <= INIT_1F[count];
228 
            mem[256 * 32 + count] <= INIT_20[count];
229 
            mem[256 * 33 + count] <= INIT_21[count];
230 
            mem[256 * 34 + count] <= INIT_22[count];
231 
            mem[256 * 35 + count] <= INIT_23[count];
232 
            mem[256 * 36 + count] <= INIT_24[count];
233 
            mem[256 * 37 + count] <= INIT_25[count];
234 
            mem[256 * 38 + count] <= INIT_26[count];
235 
            mem[256 * 39 + count] <= INIT_27[count];
236 
            mem[256 * 40 + count] <= INIT_28[count];
237 
            mem[256 * 41 + count] <= INIT_29[count];
238 
            mem[256 * 42 + count] <= INIT_2A[count];
239 
            mem[256 * 43 + count] <= INIT_2B[count];
240 
            mem[256 * 44 + count] <= INIT_2C[count];
241 
            mem[256 * 45 + count] <= INIT_2D[count];
242 
            mem[256 * 46 + count] <= INIT_2E[count];
243 
            mem[256 * 47 + count] <= INIT_2F[count];
244 
            mem[256 * 48 + count] <= INIT_30[count];
245 
            mem[256 * 49 + count] <= INIT_31[count];
246 
            mem[256 * 50 + count] <= INIT_32[count];
247 
            mem[256 * 51 + count] <= INIT_33[count];
248 
            mem[256 * 52 + count] <= INIT_34[count];
249 
            mem[256 * 53 + count] <= INIT_35[count];
250 
            mem[256 * 54 + count] <= INIT_36[count];
251 
            mem[256 * 55 + count] <= INIT_37[count];
252 
            mem[256 * 56 + count] <= INIT_38[count];
253 
            mem[256 * 57 + count] <= INIT_39[count];
254 
            mem[256 * 58 + count] <= INIT_3A[count];
255 
            mem[256 * 59 + count] <= INIT_3B[count];
256 
            mem[256 * 60 + count] <= INIT_3C[count];
257 
            mem[256 * 61 + count] <= INIT_3D[count];
258 
            mem[256 * 62 + count] <= INIT_3E[count];
259 
            mem[256 * 63 + count] <= INIT_3F[count];
260 
            mem[256 * 64 + count] <= INITP_00[count];
261 
            mem[256 * 65 + count] <= INITP_01[count];
262 
            mem[256 * 66 + count] <= INITP_02[count];
263 
            mem[256 * 67 + count] <= INITP_03[count];
264 
            mem[256 * 68 + count] <= INITP_04[count];
265 
            mem[256 * 69 + count] <= INITP_05[count];
266 
            mem[256 * 70 + count] <= INITP_06[count];
267 
            mem[256 * 71 + count] <= INITP_07[count];
268 
        end
269 
    end
270 
 
271 
    always @(addra_int or addrb_int) begin
272 
        address_collision <= 1'b0;
273 
        for (ci = 0; ci < 2; ci = ci + 1) begin
274 
            for (cj = 0; cj < 2; cj = cj + 1) begin
275 
                if ((addra_int * 2 + ci) == (addrb_int * 2 + cj)) begin
276 
                    address_collision <= 1'b1;
277 
                end
278 
            end
279 
        end
280 
    end
281 
 
282 
    // Data
283 
    always @(posedge recovery_a or posedge recovery_b) begin
284 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
285 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
286 
            if (wea_int == 1 && web_int == 1) begin
287 
                for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
288 
                    for (dmj = 0; dmj < 2; dmj = dmj + 1) begin
289 
                        if ((addra_int * 2 + dmi) == (addrb_int * 2 + dmj)) begin
290 
                            mem[addra_int * 2 + dmi] <= 1'bX;
291 
                        end
292 
                    end
293 
                end
294 
            end
295 
        end
296 
        recovery_a <= 0;
297 
        recovery_b <= 0;
298 
    end
299 
 
300 
    always @(posedge recovery_a or posedge recovery_b) begin
301 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
302 
            if (wea_int == 1 && web_int == 1) begin
303 
                for (dni = 0; dni < 2; dni = dni + 1) begin
304 
                    for (dnj = 0; dnj < 2; dnj = dnj + 1) begin
305 
                        if ((addra_int * 2 + dni) == (addrb_int * 2 + dnj)) begin
306 
                            mem[addra_int * 2 + dni] <= dia_int[dni];
307 
                        end
308 
                    end
309 
                end
310 
            end
311 
        end
312 
    end
313 
 
314 
    always @(posedge recovery_a or posedge recovery_b) begin
315 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
316 
            if (wea_int == 1 && web_int == 1) begin
317 
                for (doi = 0; doi < 2; doi = doi + 1) begin
318 
                    for (doj = 0; doj < 2; doj = doj + 1) begin
319 
                        if ((addra_int * 2 + doi) == (addrb_int * 2 + doj)) begin
320 
                            mem[addrb_int * 2 + doj] <= dib_int[doj];
321 
                        end
322 
                    end
323 
                end
324 
            end
325 
        end
326 
    end
327 
 
328 
    always @(posedge recovery_a or posedge recovery_b) begin
329 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
330 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
331 
                for (dai = 0; dai < 2; dai = dai + 1) begin
332 
                    for (daj = 0; daj < 2; daj = daj + 1) begin
333 
                        if ((addra_int * 2 + dai) == (addrb_int * 2 + daj)) begin
334 
                            doa_out[dai] <= 1'bX;
335 
                        end
336 
                    end
337 
                end
338 
            end
339 
        end
340 
    end
341 
 
342 
    always @(posedge recovery_a or posedge recovery_b) begin
343 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
344 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
345 
                for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
346 
                    for (dbj = 0; dbj < 2; dbj = dbj + 1) begin
347 
                        if ((addra_int * 2 + dbi) == (addrb_int * 2 + dbj)) begin
348 
                            dob_out[dbj] <= 1'bX;
349 
                        end
350 
                    end
351 
                end
352 
            end
353 
        end
354 
    end
355 
 
356 
    always @(posedge recovery_a or posedge recovery_b) begin
357 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
358 
            (wr_mode_b == 2'b10) ||
359 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
360 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
361 
                for (dci = 0; dci < 2; dci = dci + 1) begin
362 
                    for (dcj = 0; dcj < 2; dcj = dcj + 1) begin
363 
                        if ((addra_int * 2 + dci) == (addrb_int * 2 + dcj)) begin
364 
                            doa_out[dci] <= 1'bX;
365 
                        end
366 
                    end
367 
                end
368 
            end
369 
        end
370 
    end
371 
 
372 
    always @(posedge recovery_a or posedge recovery_b) begin
373 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
374 
            (wr_mode_a == 2'b10) ||
375 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
376 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
377 
                for (ddi = 0; ddi < 2; ddi = ddi + 1) begin
378 
                    for (ddj = 0; ddj < 2; ddj = ddj + 1) begin
379 
                        if ((addra_int * 2 + ddi) == (addrb_int * 2 + ddj)) begin
380 
                            dob_out[ddj] <= 1'bX;
381 
                        end
382 
                    end
383 
                end
384 
            end
385 
        end
386 
    end
387 
 
388 
    initial begin
389 
        case (WRITE_MODE_A)
390 
            "WRITE_FIRST" : wr_mode_a <= 2'b00;
391 
            "READ_FIRST"  : wr_mode_a <= 2'b01;
392 
            "NO_CHANGE"   : wr_mode_a <= 2'b10;
393 
            default       : begin
394 
                                $display("Error : WRITE_MODE_A = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
395 
                                $finish;
396 
                            end
397 
        endcase
398 
    end
399 
 
400 
    initial begin
401 
        case (WRITE_MODE_B)
402 
            "WRITE_FIRST" : wr_mode_b <= 2'b00;
403 
            "READ_FIRST"  : wr_mode_b <= 2'b01;
404 
            "NO_CHANGE"   : wr_mode_b <= 2'b10;
405 
            default       : begin
406 
                                $display("Error : WRITE_MODE_B = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
407 
                                $finish;
408 
                            end
409 
        endcase
410 
    end
411 
 
412 
    // Port A
413 
    always @(posedge clka_int) begin
414 
        if (ena_int == 1'b1) begin
415 
            if (ssra_int == 1'b1) begin
416 
                doa_out[0] <= SRVAL_A[0];
417 
                doa_out[1] <= SRVAL_A[1];
418 
            end
419 
            else begin
420 
                if (wea_int == 1'b1) begin
421 
                    if (wr_mode_a == 2'b00) begin
422 
                        doa_out[0] <= dia_int[0];
423 
                        doa_out[1] <= dia_int[1];
424 
                    end
425 
                    else if (wr_mode_a == 2'b01) begin
426 
                        doa_out[0] <= mem[addra_int * 2 + 0];
427 
                        doa_out[1] <= mem[addra_int * 2 + 1];
428 
                    end
429 
                    else begin
430 
                        doa_out[0] <= doa_out[0];
431 
                        doa_out[1] <= doa_out[1];
432 
                    end
433 
                end
434 
                else begin
435 
                    doa_out[0] <= mem[addra_int * 2 + 0];
436 
                    doa_out[1] <= mem[addra_int * 2 + 1];
437 
                end
438 
            end
439 
        end
440 
    end
441 
 
442 
    always @(posedge clka_int) begin
443 
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
444 
            mem[addra_int * 2 + 0] <= dia_int[0];
445 
            mem[addra_int * 2 + 1] <= dia_int[1];
446 
        end
447 
    end
448 
 
449 
    // Port B
450 
    always @(posedge clkb_int) begin
451 
        if (enb_int == 1'b1) begin
452 
            if (ssrb_int == 1'b1) begin
453 
                dob_out[0] <= SRVAL_B[0];
454 
                dob_out[1] <= SRVAL_B[1];
455 
            end
456 
            else begin
457 
                if (web_int == 1'b1) begin
458 
                    if (wr_mode_b == 2'b00) begin
459 
                        dob_out[0] <= dib_int[0];
460 
                        dob_out[1] <= dib_int[1];
461 
                    end
462 
                    else if (wr_mode_b == 2'b01) begin
463 
                        dob_out[0] <= mem[addrb_int * 2 + 0];
464 
                        dob_out[1] <= mem[addrb_int * 2 + 1];
465 
                    end
466 
                    else begin
467 
                        dob_out[0] <= dob_out[0];
468 
                        dob_out[1] <= dob_out[1];
469 
                    end
470 
                end
471 
                else begin
472 
                    dob_out[0] <= mem[addrb_int * 2 + 0];
473 
                    dob_out[1] <= mem[addrb_int * 2 + 1];
474 
                end
475 
            end
476 
        end
477 
    end
478 
 
479 
    always @(posedge clkb_int) begin
480 
        if (enb_int == 1'b1 && web_int == 1'b1) begin
481 
            mem[addrb_int * 2 + 0] <= dib_int[0];
482 
            mem[addrb_int * 2 + 1] <= dib_int[1];
483 
        end
484 
    end
485 
 
486 
    specify
487 
        (CLKA *> DOA) = (1, 1);
488 
        (CLKB *> DOB) = (1, 1);
489 
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
490 
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
491 
    endspecify
492 
 
493 
endmodule
494 
 
495 
`endcelldefine

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