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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB4_S1_S4.v,v 1.1.1.1 2001-11-04 18:59:59 lampret Exp $
 
/*
 
FUNCTION        : 4x1x4 Block RAM with synchronous write capability
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module RAMB4_S1_S4 (DOA, DOB, ADDRA, CLKA, DIA, ENA, RSTA, WEA, ADDRB, CLKB, DIB, ENB, RSTB, WEB);
 
    parameter cds_action = "ignore";
 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
    output [0:0] DOA;
    reg [0:0] doa_out;
    wire doa_out0;
 
    input [11:0] ADDRA;
    input [0:0] DIA;
    input ENA, CLKA, WEA, RSTA;
 
    output [3:0] DOB;
    reg [3:0] dob_out;
    wire dob_out0, dob_out1, dob_out2, dob_out3;
 
    input [9:0] ADDRB;
    input [3:0] DIB;
    input ENB, CLKB, WEB, RSTB;
 
    reg [4095:0] mem;
    reg [8:0] count;
 
    reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj;
 
    wire [11:0] addra_int;
    wire [0:0] dia_int;
    wire ena_int, clka_int, wea_int, rsta_int;
    wire [9:0] addrb_int;
    wire [3:0] dib_int;
    wire enb_int, clkb_int, web_int, rstb_int;
 
    reg recovery_a, recovery_b;
    reg address_collision;
 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
    wire collision = clka_enable || clkb_enable;
 
    tri0 GSR = glbl.GSR;
 
    always @(GSR)
        if (GSR) begin
            assign doa_out = 0;
        end
        else begin
            deassign doa_out;
        end
 
    always @(GSR)
        if (GSR) begin
            assign dob_out = 0;
        end
        else begin
            deassign dob_out;
        end
 
    buf b_doa_out0 (doa_out0, doa_out[0]);
    buf b_dob_out0 (dob_out0, dob_out[0]);
    buf b_dob_out1 (dob_out1, dob_out[1]);
    buf b_dob_out2 (dob_out2, dob_out[2]);
    buf b_dob_out3 (dob_out3, dob_out[3]);
    buf b_doa0 (DOA[0], doa_out0);
    buf b_dob0 (DOB[0], dob_out0);
    buf b_dob1 (DOB[1], dob_out1);
    buf b_dob2 (DOB[2], dob_out2);
    buf b_dob3 (DOB[3], dob_out3);
    buf b_addra_0 (addra_int[0], ADDRA[0]);
    buf b_addra_1 (addra_int[1], ADDRA[1]);
    buf b_addra_2 (addra_int[2], ADDRA[2]);
    buf b_addra_3 (addra_int[3], ADDRA[3]);
    buf b_addra_4 (addra_int[4], ADDRA[4]);
    buf b_addra_5 (addra_int[5], ADDRA[5]);
    buf b_addra_6 (addra_int[6], ADDRA[6]);
    buf b_addra_7 (addra_int[7], ADDRA[7]);
    buf b_addra_8 (addra_int[8], ADDRA[8]);
    buf b_addra_9 (addra_int[9], ADDRA[9]);
    buf b_addra_10 (addra_int[10], ADDRA[10]);
    buf b_addra_11 (addra_int[11], ADDRA[11]);
    buf b_dia_0 (dia_int[0], DIA[0]);
    buf b_clka (clka_int, CLKA);
    buf b_ena (ena_int, ENA);
    buf b_rsta (rsta_int, RSTA);
    buf b_wea (wea_int, WEA);
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
    buf b_dib_0 (dib_int[0], DIB[0]);
    buf b_dib_1 (dib_int[1], DIB[1]);
    buf b_dib_2 (dib_int[2], DIB[2]);
    buf b_dib_3 (dib_int[3], DIB[3]);
    buf b_clkb (clkb_int, CLKB);
    buf b_enb (enb_int, ENB);
    buf b_rstb (rstb_int, RSTB);
    buf b_web (web_int, WEB);
 
    initial begin
        for (count = 0; count < 256; count = count + 1) begin
            mem[count]            <= INIT_00[count];
            mem[256 * 1 + count]  <= INIT_01[count];
            mem[256 * 2 + count]  <= INIT_02[count];
            mem[256 * 3 + count]  <= INIT_03[count];
            mem[256 * 4 + count]  <= INIT_04[count];
            mem[256 * 5 + count]  <= INIT_05[count];
            mem[256 * 6 + count]  <= INIT_06[count];
            mem[256 * 7 + count]  <= INIT_07[count];
            mem[256 * 8 + count]  <= INIT_08[count];
            mem[256 * 9 + count]  <= INIT_09[count];
            mem[256 * 10 + count] <= INIT_0A[count];
            mem[256 * 11 + count] <= INIT_0B[count];
            mem[256 * 12 + count] <= INIT_0C[count];
            mem[256 * 13 + count] <= INIT_0D[count];
            mem[256 * 14 + count] <= INIT_0E[count];
            mem[256 * 15 + count] <= INIT_0F[count];
        end
        recovery_a <= 0;
        recovery_b <= 0;
    end
 
    always @(addra_int or addrb_int) begin
        address_collision <= 1'b0;
        for (ci = 0; ci < 1; ci = ci + 1) begin
            for (cj = 0; cj < 4; cj = cj + 1) begin
                if ((addra_int * 1 + ci) == (addrb_int * 4 + cj)) begin
                    address_collision <= 1'b1;
                end
            end
        end
    end
 
    always @(posedge recovery_a or posedge recovery_b) begin
        if (wea_int == 1 && web_int == 1) begin
            for (mi = 0; mi < 1; mi = mi + 1) begin
                for (mj = 0; mj < 4; mj = mj + 1) begin
                    if ((addra_int * 1 + mi) == (addrb_int * 4 + mj)) begin
                        mem[addra_int * 1 + mi] <= 1'bX;
                    end
                end
            end
        end
        recovery_a <= 0;
        recovery_b <= 0;
    end
 
    always @(posedge recovery_a or posedge recovery_b) begin
        if (web_int == 1 && rsta_int == 0) begin
            for (ai = 0; ai < 1; ai = ai + 1) begin
                for (aj = 0; aj < 4; aj = aj + 1) begin
                    if ((addra_int * 1 + ai) == (addrb_int * 4 + aj)) begin
                        doa_out[ai] <= 1'bX;
                    end
                end
            end
        end
    end
 
    always @(posedge recovery_a or posedge recovery_b) begin
        if (wea_int == 1 && rstb_int == 0) begin
            for (bi = 0; bi < 1; bi = bi + 1) begin
                for (bj = 0; bj < 4; bj = bj + 1) begin
                    if ((addra_int * 1 + bi) == (addrb_int * 4 + bj)) begin
                        dob_out[bj] <= 1'bX;
                    end
                end
            end
        end
    end
 
    always @(posedge clka_int) begin
        if (ena_int == 1'b1) begin
            if (rsta_int == 1'b1) begin
                doa_out[0] <= 0;
            end
            else if (wea_int == 0) begin
                doa_out[0] <= mem[addra_int * 1 + 0];
            end
            else begin
                doa_out[0] <= dia_int[0];
            end
        end
    end
 
    always @(posedge clka_int) begin
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
            mem[addra_int * 1 + 0] <= dia_int[0];
        end
    end
 
    always @(posedge clkb_int) begin
        if (enb_int == 1'b1) begin
            if (rstb_int == 1'b1) begin
                dob_out[0] <= 0;
                dob_out[1] <= 0;
                dob_out[2] <= 0;
                dob_out[3] <= 0;
            end
            else if (web_int == 0) begin
                dob_out[0] <= mem[addrb_int * 4 + 0];
                dob_out[1] <= mem[addrb_int * 4 + 1];
                dob_out[2] <= mem[addrb_int * 4 + 2];
                dob_out[3] <= mem[addrb_int * 4 + 3];
            end
            else begin
                dob_out[0] <= dib_int[0];
                dob_out[1] <= dib_int[1];
                dob_out[2] <= dib_int[2];
                dob_out[3] <= dib_int[3];
            end
        end
    end
 
    always @(posedge clkb_int) begin
        if (enb_int == 1'b1 && web_int == 1'b1) begin
            mem[addrb_int * 4 + 0] <= dib_int[0];
            mem[addrb_int * 4 + 1] <= dib_int[1];
            mem[addrb_int * 4 + 2] <= dib_int[2];
            mem[addrb_int * 4 + 3] <= dib_int[3];
        end
    end
 
    specify
        (CLKA *> DOA) = (1, 1);
        (CLKB *> DOB) = (1, 1);
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
    endspecify
 
endmodule
 
`endcelldefine

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[/] [or1k/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB4_S1_S4.v] - Blame information for rev 1779

Line No.	Rev	Author	Line
1	266	lampret	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB4_S1_S4.v,v 1.1.1.1 2001-11-04 18:59:59 lampret Exp $`
2
3			`/*`
4
5			`FUNCTION : 4x1x4 Block RAM with synchronous write capability`
6
7			`*/`
8
9			`timescale 100 ps / 10 ps
10
11			`celldefine
12
13			`module RAMB4_S1_S4 (DOA, DOB, ADDRA, CLKA, DIA, ENA, RSTA, WEA, ADDRB, CLKB, DIB, ENB, RSTB, WEB);`
14
15			`parameter cds_action = "ignore";`
16
17			`parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
18			`parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
19			`parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
20			`parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
21			`parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
22			`parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
23			`parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
24			`parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
25			`parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
26			`parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
27			`parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
28			`parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
29			`parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
30			`parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
31			`parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
32			`parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
33
34			`output [0:0] DOA;`
35			`reg [0:0] doa_out;`
36			`wire doa_out0;`
37
38			`input [11:0] ADDRA;`
39			`input [0:0] DIA;`
40			`input ENA, CLKA, WEA, RSTA;`
41
42			`output [3:0] DOB;`
43			`reg [3:0] dob_out;`
44			`wire dob_out0, dob_out1, dob_out2, dob_out3;`
45
46			`input [9:0] ADDRB;`
47			`input [3:0] DIB;`
48			`input ENB, CLKB, WEB, RSTB;`
49
50			`reg [4095:0] mem;`
51			`reg [8:0] count;`
52
53			`reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj;`
54
55			`wire [11:0] addra_int;`
56			`wire [0:0] dia_int;`
57			`wire ena_int, clka_int, wea_int, rsta_int;`
58			`wire [9:0] addrb_int;`
59			`wire [3:0] dib_int;`
60			`wire enb_int, clkb_int, web_int, rstb_int;`
61
62			`reg recovery_a, recovery_b;`
63			`reg address_collision;`
64
65			`wire clka_enable = ena_int && wea_int && enb_int && address_collision;`
66			`wire clkb_enable = enb_int && web_int && ena_int && address_collision;`
67			`wire collision = clka_enable \|\| clkb_enable;`
68
69			`tri0 GSR = glbl.GSR;`
70
71			`always @(GSR)`
72			`if (GSR) begin`
73			`assign doa_out = 0;`
74			`end`
75			`else begin`
76			`deassign doa_out;`
77			`end`
78
79			`always @(GSR)`
80			`if (GSR) begin`
81			`assign dob_out = 0;`
82			`end`
83			`else begin`
84			`deassign dob_out;`
85			`end`
86
87			`buf b_doa_out0 (doa_out0, doa_out[0]);`
88			`buf b_dob_out0 (dob_out0, dob_out[0]);`
89			`buf b_dob_out1 (dob_out1, dob_out[1]);`
90			`buf b_dob_out2 (dob_out2, dob_out[2]);`
91			`buf b_dob_out3 (dob_out3, dob_out[3]);`
92			`buf b_doa0 (DOA[0], doa_out0);`
93			`buf b_dob0 (DOB[0], dob_out0);`
94			`buf b_dob1 (DOB[1], dob_out1);`
95			`buf b_dob2 (DOB[2], dob_out2);`
96			`buf b_dob3 (DOB[3], dob_out3);`
97			`buf b_addra_0 (addra_int[0], ADDRA[0]);`
98			`buf b_addra_1 (addra_int[1], ADDRA[1]);`
99			`buf b_addra_2 (addra_int[2], ADDRA[2]);`
100			`buf b_addra_3 (addra_int[3], ADDRA[3]);`
101			`buf b_addra_4 (addra_int[4], ADDRA[4]);`
102			`buf b_addra_5 (addra_int[5], ADDRA[5]);`
103			`buf b_addra_6 (addra_int[6], ADDRA[6]);`
104			`buf b_addra_7 (addra_int[7], ADDRA[7]);`
105			`buf b_addra_8 (addra_int[8], ADDRA[8]);`
106			`buf b_addra_9 (addra_int[9], ADDRA[9]);`
107			`buf b_addra_10 (addra_int[10], ADDRA[10]);`
108			`buf b_addra_11 (addra_int[11], ADDRA[11]);`
109			`buf b_dia_0 (dia_int[0], DIA[0]);`
110			`buf b_clka (clka_int, CLKA);`
111			`buf b_ena (ena_int, ENA);`
112			`buf b_rsta (rsta_int, RSTA);`
113			`buf b_wea (wea_int, WEA);`
114			`buf b_addrb_0 (addrb_int[0], ADDRB[0]);`
115			`buf b_addrb_1 (addrb_int[1], ADDRB[1]);`
116			`buf b_addrb_2 (addrb_int[2], ADDRB[2]);`
117			`buf b_addrb_3 (addrb_int[3], ADDRB[3]);`
118			`buf b_addrb_4 (addrb_int[4], ADDRB[4]);`
119			`buf b_addrb_5 (addrb_int[5], ADDRB[5]);`
120			`buf b_addrb_6 (addrb_int[6], ADDRB[6]);`
121			`buf b_addrb_7 (addrb_int[7], ADDRB[7]);`
122			`buf b_addrb_8 (addrb_int[8], ADDRB[8]);`
123			`buf b_addrb_9 (addrb_int[9], ADDRB[9]);`
124			`buf b_dib_0 (dib_int[0], DIB[0]);`
125			`buf b_dib_1 (dib_int[1], DIB[1]);`
126			`buf b_dib_2 (dib_int[2], DIB[2]);`
127			`buf b_dib_3 (dib_int[3], DIB[3]);`
128			`buf b_clkb (clkb_int, CLKB);`
129			`buf b_enb (enb_int, ENB);`
130			`buf b_rstb (rstb_int, RSTB);`
131			`buf b_web (web_int, WEB);`
132
133			`initial begin`
134			`for (count = 0; count < 256; count = count + 1) begin`
135			`mem[count] <= INIT_00[count];`
136			`mem[256 * 1 + count] <= INIT_01[count];`
137			`mem[256 * 2 + count] <= INIT_02[count];`
138			`mem[256 * 3 + count] <= INIT_03[count];`
139			`mem[256 * 4 + count] <= INIT_04[count];`
140			`mem[256 * 5 + count] <= INIT_05[count];`
141			`mem[256 * 6 + count] <= INIT_06[count];`
142			`mem[256 * 7 + count] <= INIT_07[count];`
143			`mem[256 * 8 + count] <= INIT_08[count];`
144			`mem[256 * 9 + count] <= INIT_09[count];`
145			`mem[256 * 10 + count] <= INIT_0A[count];`
146			`mem[256 * 11 + count] <= INIT_0B[count];`
147			`mem[256 * 12 + count] <= INIT_0C[count];`
148			`mem[256 * 13 + count] <= INIT_0D[count];`
149			`mem[256 * 14 + count] <= INIT_0E[count];`
150			`mem[256 * 15 + count] <= INIT_0F[count];`
151			`end`
152			`recovery_a <= 0;`
153			`recovery_b <= 0;`
154			`end`
155
156			`always @(addra_int or addrb_int) begin`
157			`address_collision <= 1'b0;`
158			`for (ci = 0; ci < 1; ci = ci + 1) begin`
159			`for (cj = 0; cj < 4; cj = cj + 1) begin`
160			`if ((addra_int * 1 + ci) == (addrb_int * 4 + cj)) begin`
161			`address_collision <= 1'b1;`
162			`end`
163			`end`
164			`end`
165			`end`
166
167			`always @(posedge recovery_a or posedge recovery_b) begin`
168			`if (wea_int == 1 && web_int == 1) begin`
169			`for (mi = 0; mi < 1; mi = mi + 1) begin`
170			`for (mj = 0; mj < 4; mj = mj + 1) begin`
171			`if ((addra_int * 1 + mi) == (addrb_int * 4 + mj)) begin`
172			`mem[addra_int * 1 + mi] <= 1'bX;`
173			`end`
174			`end`
175			`end`
176			`end`
177			`recovery_a <= 0;`
178			`recovery_b <= 0;`
179			`end`
180
181			`always @(posedge recovery_a or posedge recovery_b) begin`
182			`if (web_int == 1 && rsta_int == 0) begin`
183			`for (ai = 0; ai < 1; ai = ai + 1) begin`
184			`for (aj = 0; aj < 4; aj = aj + 1) begin`
185			`if ((addra_int * 1 + ai) == (addrb_int * 4 + aj)) begin`
186			`doa_out[ai] <= 1'bX;`
187			`end`
188			`end`
189			`end`
190			`end`
191			`end`
192
193			`always @(posedge recovery_a or posedge recovery_b) begin`
194			`if (wea_int == 1 && rstb_int == 0) begin`
195			`for (bi = 0; bi < 1; bi = bi + 1) begin`
196			`for (bj = 0; bj < 4; bj = bj + 1) begin`
197			`if ((addra_int * 1 + bi) == (addrb_int * 4 + bj)) begin`
198			`dob_out[bj] <= 1'bX;`
199			`end`
200			`end`
201			`end`
202			`end`
203			`end`
204
205			`always @(posedge clka_int) begin`
206			`if (ena_int == 1'b1) begin`
207			`if (rsta_int == 1'b1) begin`
208			`doa_out[0] <= 0;`
209			`end`
210			`else if (wea_int == 0) begin`
211			`doa_out[0] <= mem[addra_int * 1 + 0];`
212			`end`
213			`else begin`
214			`doa_out[0] <= dia_int[0];`
215			`end`
216			`end`
217			`end`
218
219			`always @(posedge clka_int) begin`
220			`if (ena_int == 1'b1 && wea_int == 1'b1) begin`
221			`mem[addra_int * 1 + 0] <= dia_int[0];`
222			`end`
223			`end`
224
225			`always @(posedge clkb_int) begin`
226			`if (enb_int == 1'b1) begin`
227			`if (rstb_int == 1'b1) begin`
228			`dob_out[0] <= 0;`
229			`dob_out[1] <= 0;`
230			`dob_out[2] <= 0;`
231			`dob_out[3] <= 0;`
232			`end`
233			`else if (web_int == 0) begin`
234			`dob_out[0] <= mem[addrb_int * 4 + 0];`
235			`dob_out[1] <= mem[addrb_int * 4 + 1];`
236			`dob_out[2] <= mem[addrb_int * 4 + 2];`
237			`dob_out[3] <= mem[addrb_int * 4 + 3];`
238			`end`
239			`else begin`
240			`dob_out[0] <= dib_int[0];`
241			`dob_out[1] <= dib_int[1];`
242			`dob_out[2] <= dib_int[2];`
243			`dob_out[3] <= dib_int[3];`
244			`end`
245			`end`
246			`end`
247
248			`always @(posedge clkb_int) begin`
249			`if (enb_int == 1'b1 && web_int == 1'b1) begin`
250			`mem[addrb_int * 4 + 0] <= dib_int[0];`
251			`mem[addrb_int * 4 + 1] <= dib_int[1];`
252			`mem[addrb_int * 4 + 2] <= dib_int[2];`
253			`mem[addrb_int * 4 + 3] <= dib_int[3];`
254			`end`
255			`end`
256
257			`specify`
258			`(CLKA *> DOA) = (1, 1);`
259			`(CLKB *> DOB) = (1, 1);`
260			`$recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);`
261			`$recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);`
262			`endspecify`
263
264			`endmodule`
265
266			`endcelldefine