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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MP3 demo SRAM interface                                     ////
////                                                              ////
////  This file is part of the MP3 demo application               ////
////  http://www.opencores.org/cores/or1k/mp3/                    ////
////                                                              ////
////  Description                                                 ////
////  Connects MP3 demo to SRAM. It does RMW for byte accesses    ////
////  because XSV board has WEs on a 16-bit basis.                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot, simons@opencores.org                      ////
////      - Igor Mohor, igorm@opencores.org                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module sram_top (
  clk, rstn,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d
 
);
 
parameter addr_width = 19;
 
input   clk;
input   rstn;
 
input [31:0]  wb_dat_i;
output [31:0] wb_dat_o;
input [31:0]  wb_adr_i;
input [3:0] wb_sel_i;
input   wb_we_i;
input   wb_cyc_i;
input   wb_stb_i;
output  wb_ack_o;
output  wb_err_o;
 
output  r_oen;
output  r0_wen;
output  r1_wen;
output  r_cen;
inout [15:0]  r_d;
output [addr_width-1:0] r_a;
 
output    l_oen;
output    l0_wen;
output    l1_wen;
output    l_cen;
inout [15:0]  l_d;
output [addr_width-1:0] l_a;
 
reg [15:0]  r_data;
reg [15:0]  l_data;
 
 
reg  l0_wen;
wire l1_wen = l0_wen;
reg  r0_wen;
wire r1_wen = r0_wen;
 
 
reg [31:0] latch_data;
reg ack_we;
 
wire l_oe;
wire r_oe;
 
assign l_oen  = ~l_oe;
assign r_oen  = ~r_oe;
 
 
reg Mux;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    Mux <= 1'b0;
  else
  if(ack_we)
    Mux <= #1 1'b1;
  else
    Mux <= #1 1'b0;
end
 
 
reg [addr_width-1:0] LatchedAddr;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    LatchedAddr <= 'h0;
  else
  if(wb_cyc_i & wb_stb_i)
    LatchedAddr <= #1 wb_adr_i[addr_width+1:2];
end
 
 
assign l_a = Mux? LatchedAddr : wb_adr_i[addr_width+1:2];
assign r_a = l_a;
 
 
reg [15:0] l_read;
reg [15:0] r_read;
// Data latch from RAM (read data)
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    begin
      l_read <= 16'h0;
      r_read <= 16'h0;
    end
  else
  if(wb_cyc_i & wb_stb_i)
    begin
      l_read <= #1 l_d[15:0];
      r_read <= #1 r_d[15:0];
    end
end
 
assign wb_dat_o = {r_d, l_d};
 
// Mux and latch data for writing (bytes 0 and 1)
reg [15:0] l_mux;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    l_mux <= 16'h0;
  else
  if(~l0_wen)
    begin
      if(wb_sel_i[0])
        l_mux[7:0]  <= #1 wb_dat_i[7:0];
      else
        l_mux[7:0]  <= #1 l_read[7:0];
      if(wb_sel_i[1])
        l_mux[15:8] <= #1 wb_dat_i[15:8];
      else
        l_mux[15:8] <= #1 l_read[15:8];
    end
  else
    l_mux[15:0]  <= #1 16'hz;
end
 
 
 
// Mux and latch data for writing (bytes 2 and 3)
reg [15:0] r_mux;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    r_mux <= 16'h0;
  else
  if(~r0_wen)
    begin
      if(wb_sel_i[2])
        r_mux[7:0]  <= #1 wb_dat_i[23:16];
      else
        r_mux[7:0]  <= #1 r_read[7:0];
      if(wb_sel_i[3])
        r_mux[15:8]  <= #1 wb_dat_i[31:24];
      else
        r_mux[15:8]  <= #1 r_read[15:8];
    end
  else
    r_mux <= #1 16'hz;
end
 
 
assign l_d = l_mux;
assign r_d = r_mux;
 
 
// Output enable
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
 
 
// WE
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    l0_wen <= 1'b1;
  else
  if(wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
    l0_wen <= #1 1'b0;
  else
    l0_wen <= #1 1'b1;
end
 
 
// WE
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    r0_wen <= 1'b1;
  else
  if(wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
    r0_wen <= #1 1'b0;
  else
    r0_wen <= #1 1'b1;
end
 
 
// CE
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
 
 
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    ack_we <= 1'b0;
  else
  if(wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
 
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]);     // If Access to > 2MB (4-bit leading prefix ignored)
 
 
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge clk)
begin
  if (~l0_wen | ~r0_wen)
    $fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d, l_d});
  else
  if(l_oe | r_oe)
    $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d, l_d});
end
// synopsys translate_on
 
 
 
endmodule

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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MP3 demo SRAM interface ////`
4			`//// ////`
5			`//// This file is part of the MP3 demo application ////`
6			`//// http://www.opencores.org/cores/or1k/mp3/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects MP3 demo to SRAM. It does RMW for byte accesses ////`
10			`//// because XSV board has WEs on a 16-bit basis. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Srot, simons@opencores.org ////`
17			`//// - Igor Mohor, igorm@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	609	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
50			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
51			`//`
52	562	lampret	`// Revision 1.1.1.1 2001/11/04 19:00:09 lampret`
53			`// First import.`
54	266	lampret	`//`
55	562	lampret	`//`
56	266	lampret
57			`// synopsys translate_off`
58			`include "timescale.v"
59			`// synopsys translate_on`
60
61			`module sram_top (`
62			`clk, rstn,`
63
64			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
65			`wb_stb_i, wb_ack_o, wb_err_o,`
66
67			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d,`
68			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d`
69
70			`);`
71
72			`parameter addr_width = 19;`
73
74			`input clk;`
75			`input rstn;`
76
77			`input [31:0] wb_dat_i;`
78			`output [31:0] wb_dat_o;`
79			`input [31:0] wb_adr_i;`
80			`input [3:0] wb_sel_i;`
81			`input wb_we_i;`
82			`input wb_cyc_i;`
83			`input wb_stb_i;`
84			`output wb_ack_o;`
85			`output wb_err_o;`
86
87			`output r_oen;`
88			`output r0_wen;`
89			`output r1_wen;`
90			`output r_cen;`
91			`inout [15:0] r_d;`
92			`output [addr_width-1:0] r_a;`
93
94			`output l_oen;`
95			`output l0_wen;`
96			`output l1_wen;`
97			`output l_cen;`
98			`inout [15:0] l_d;`
99			`output [addr_width-1:0] l_a;`
100
101			`reg [15:0] r_data;`
102			`reg [15:0] l_data;`
103
104
105			`reg l0_wen;`
106			`wire l1_wen = l0_wen;`
107			`reg r0_wen;`
108			`wire r1_wen = r0_wen;`
109
110
111			`reg [31:0] latch_data;`
112			`reg ack_we;`
113
114			`wire l_oe;`
115			`wire r_oe;`
116
117			`assign l_oen = ~l_oe;`
118			`assign r_oen = ~r_oe;`
119
120
121			`reg Mux;`
122			`always @ (negedge clk or negedge rstn)`
123			`begin`
124			`if(~rstn)`
125			`Mux <= 1'b0;`
126			`else`
127			`if(ack_we)`
128			`Mux <= #1 1'b1;`
129			`else`
130			`Mux <= #1 1'b0;`
131			`end`
132
133
134			`reg [addr_width-1:0] LatchedAddr;`
135			`always @ (negedge clk or negedge rstn)`
136			`begin`
137			`if(~rstn)`
138			`LatchedAddr <= 'h0;`
139			`else`
140			`if(wb_cyc_i & wb_stb_i)`
141			`LatchedAddr <= #1 wb_adr_i[addr_width+1:2];`
142			`end`
143
144
145			`assign l_a = Mux? LatchedAddr : wb_adr_i[addr_width+1:2];`
146			`assign r_a = l_a;`
147
148
149			`reg [15:0] l_read;`
150			`reg [15:0] r_read;`
151			`// Data latch from RAM (read data)`
152			`always @ (posedge clk or negedge rstn)`
153			`begin`
154			`if(~rstn)`
155			`begin`
156			`l_read <= 16'h0;`
157			`r_read <= 16'h0;`
158			`end`
159			`else`
160			`if(wb_cyc_i & wb_stb_i)`
161			`begin`
162			`l_read <= #1 l_d[15:0];`
163			`r_read <= #1 r_d[15:0];`
164			`end`
165			`end`
166
167			`assign wb_dat_o = {r_d, l_d};`
168
169			`// Mux and latch data for writing (bytes 0 and 1)`
170			`reg [15:0] l_mux;`
171			`always @ (negedge clk or negedge rstn)`
172			`begin`
173			`if(~rstn)`
174			`l_mux <= 16'h0;`
175			`else`
176			`if(~l0_wen)`
177			`begin`
178			`if(wb_sel_i[0])`
179			`l_mux[7:0] <= #1 wb_dat_i[7:0];`
180			`else`
181			`l_mux[7:0] <= #1 l_read[7:0];`
182			`if(wb_sel_i[1])`
183			`l_mux[15:8] <= #1 wb_dat_i[15:8];`
184			`else`
185			`l_mux[15:8] <= #1 l_read[15:8];`
186			`end`
187			`else`
188			`l_mux[15:0] <= #1 16'hz;`
189			`end`
190
191
192
193			`// Mux and latch data for writing (bytes 2 and 3)`
194			`reg [15:0] r_mux;`
195			`always @ (negedge clk or negedge rstn)`
196			`begin`
197			`if(~rstn)`
198			`r_mux <= 16'h0;`
199			`else`
200			`if(~r0_wen)`
201			`begin`
202			`if(wb_sel_i[2])`
203			`r_mux[7:0] <= #1 wb_dat_i[23:16];`
204			`else`
205			`r_mux[7:0] <= #1 r_read[7:0];`
206			`if(wb_sel_i[3])`
207			`r_mux[15:8] <= #1 wb_dat_i[31:24];`
208			`else`
209			`r_mux[15:8] <= #1 r_read[15:8];`
210			`end`
211			`else`
212			`r_mux <= #1 16'hz;`
213			`end`
214
215
216			`assign l_d = l_mux;`
217			`assign r_d = r_mux;`
218
219
220			`// Output enable`
221			`assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;`
222			`assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;`
223
224
225			`// WE`
226			`always @ (posedge clk or negedge rstn)`
227			`begin`
228			`if(~rstn)`
229			`l0_wen <= 1'b1;`
230			`else`
231			`if(wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[1:0]) & ~wb_ack_o)`
232			`l0_wen <= #1 1'b0;`
233			`else`
234	562	lampret	`l0_wen <= #1 1'b1;`
235	266	lampret	`end`
236
237
238			`// WE`
239			`always @ (posedge clk or negedge rstn)`
240			`begin`
241			`if(~rstn)`
242			`r0_wen <= 1'b1;`
243			`else`
244			`if(wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:2]) & ~wb_ack_o)`
245			`r0_wen <= #1 1'b0;`
246			`else`
247	562	lampret	`r0_wen <= #1 1'b1;`
248	266	lampret	`end`
249
250
251			`// CE`
252			`assign l_cen = ~(wb_cyc_i & wb_stb_i);`
253			`assign r_cen = l_cen;`
254
255
256			`always @ (posedge clk or negedge rstn)`
257			`begin`
258			`if(~rstn)`
259			`ack_we <= 1'b0;`
260			`else`
261			`if(wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
262			`ack_we <= #1 1'b1;`
263			`else`
264			`ack_we <= #1 1'b0;`
265			`end`
266
267
268			`assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) \| ack_we;`
269	609	lampret	`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)`
270	266	lampret
271
272			`// synopsys translate_off`
273			`integer fsram;`
274			`initial fsram = $fopen("sram.log");`
275			`always @(posedge clk)`
276			`begin`
277			`if (~l0_wen \| ~r0_wen)`
278			`$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d, l_d});`
279			`else`
280			`if(l_oe \| r_oe)`
281			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d, l_d});`
282			`end`
283			`// synopsys translate_on`
284
285
286
287			`endmodule`