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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 266

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MP3 demo SRAM interface                                     ////
////                                                              ////
////  This file is part of the MP3 demo application               ////
////  http://www.opencores.org/cores/or1k/mp3/                    ////
////                                                              ////
////  Description                                                 ////
////  Connects MP3 demo to SRAM. It does RMW for byte accesses    ////
////  because XSV board has WEs on a 16-bit basis.                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot, simons@opencores.org                      ////
////      - Igor Mohor, igorm@opencores.org                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module sram_top (
  clk, rstn,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d
 
);
 
parameter addr_width = 19;
 
input   clk;
input   rstn;
 
input [31:0]  wb_dat_i;
output [31:0] wb_dat_o;
input [31:0]  wb_adr_i;
input [3:0] wb_sel_i;
input   wb_we_i;
input   wb_cyc_i;
input   wb_stb_i;
output  wb_ack_o;
output  wb_err_o;
 
output  r_oen;
output  r0_wen;
output  r1_wen;
output  r_cen;
inout [15:0]  r_d;
output [addr_width-1:0] r_a;
 
output    l_oen;
output    l0_wen;
output    l1_wen;
output    l_cen;
inout [15:0]  l_d;
output [addr_width-1:0] l_a;
 
reg [15:0]  r_data;
reg [15:0]  l_data;
 
 
reg  l0_wen;
wire l1_wen = l0_wen;
reg  r0_wen;
wire r1_wen = r0_wen;
 
 
reg [31:0] latch_data;
reg ack_we;
 
wire l_oe;
wire r_oe;
 
assign l_oen  = ~l_oe;
assign r_oen  = ~r_oe;
 
 
reg Mux;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    Mux <= 1'b0;
  else
  if(ack_we)
    Mux <= #1 1'b1;
  else
    Mux <= #1 1'b0;
end
 
 
reg [addr_width-1:0] LatchedAddr;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    LatchedAddr <= 'h0;
  else
  if(wb_cyc_i & wb_stb_i)
    LatchedAddr <= #1 wb_adr_i[addr_width+1:2];
end
 
 
assign l_a = Mux? LatchedAddr : wb_adr_i[addr_width+1:2];
assign r_a = l_a;
 
 
reg [15:0] l_read;
reg [15:0] r_read;
// Data latch from RAM (read data)
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    begin
      l_read <= 16'h0;
      r_read <= 16'h0;
    end
  else
  if(wb_cyc_i & wb_stb_i)
    begin
      l_read <= #1 l_d[15:0];
      r_read <= #1 r_d[15:0];
    end
end
 
assign wb_dat_o = {r_d, l_d};
 
// Mux and latch data for writing (bytes 0 and 1)
reg [15:0] l_mux;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    l_mux <= 16'h0;
  else
  if(~l0_wen)
    begin
      if(wb_sel_i[0])
        l_mux[7:0]  <= #1 wb_dat_i[7:0];
      else
        l_mux[7:0]  <= #1 l_read[7:0];
      if(wb_sel_i[1])
        l_mux[15:8] <= #1 wb_dat_i[15:8];
      else
        l_mux[15:8] <= #1 l_read[15:8];
    end
  else
    l_mux[15:0]  <= #1 16'hz;
end
 
 
 
// Mux and latch data for writing (bytes 2 and 3)
reg [15:0] r_mux;
always @ (negedge clk or negedge rstn)
begin
  if(~rstn)
    r_mux <= 16'h0;
  else
  if(~r0_wen)
    begin
      if(wb_sel_i[2])
        r_mux[7:0]  <= #1 wb_dat_i[23:16];
      else
        r_mux[7:0]  <= #1 r_read[7:0];
      if(wb_sel_i[3])
        r_mux[15:8]  <= #1 wb_dat_i[31:24];
      else
        r_mux[15:8]  <= #1 r_read[15:8];
    end
  else
    r_mux <= #1 16'hz;
end
 
 
assign l_d = l_mux;
assign r_d = r_mux;
 
 
// Output enable
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
 
 
// WE
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    l0_wen <= 1'b1;
  else
  if(wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
    l0_wen <= #1 1'b0;
  else
    l0_wen <= 1'b1;
end
 
 
// WE
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    r0_wen <= 1'b1;
  else
  if(wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
    r0_wen <= #1 1'b0;
  else
    r0_wen <= 1'b1;
end
 
 
// CE
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
 
 
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    ack_we <= 1'b0;
  else
  if(wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
 
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) | ack_we;
assign wb_err_o = 1'b0;
 
 
 
 
 
 
 
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge clk)
begin
  if (~l0_wen | ~r0_wen)
    $fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d, l_d});
  else
  if(l_oe | r_oe)
    $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d, l_d});
end
// synopsys translate_on
 
 
 
endmodule

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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 266

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MP3 demo SRAM interface ////`
4			`//// ////`
5			`//// This file is part of the MP3 demo application ////`
6			`//// http://www.opencores.org/cores/or1k/mp3/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects MP3 demo to SRAM. It does RMW for byte accesses ////`
10			`//// because XSV board has WEs on a 16-bit basis. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Srot, simons@opencores.org ////`
17			`//// - Igor Mohor, igorm@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49			`//`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54
55			`module sram_top (`
56			`clk, rstn,`
57
58			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
59			`wb_stb_i, wb_ack_o, wb_err_o,`
60
61			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d,`
62			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d`
63
64			`);`
65
66			`parameter addr_width = 19;`
67
68			`input clk;`
69			`input rstn;`
70
71			`input [31:0] wb_dat_i;`
72			`output [31:0] wb_dat_o;`
73			`input [31:0] wb_adr_i;`
74			`input [3:0] wb_sel_i;`
75			`input wb_we_i;`
76			`input wb_cyc_i;`
77			`input wb_stb_i;`
78			`output wb_ack_o;`
79			`output wb_err_o;`
80
81			`output r_oen;`
82			`output r0_wen;`
83			`output r1_wen;`
84			`output r_cen;`
85			`inout [15:0] r_d;`
86			`output [addr_width-1:0] r_a;`
87
88			`output l_oen;`
89			`output l0_wen;`
90			`output l1_wen;`
91			`output l_cen;`
92			`inout [15:0] l_d;`
93			`output [addr_width-1:0] l_a;`
94
95			`reg [15:0] r_data;`
96			`reg [15:0] l_data;`
97
98
99			`reg l0_wen;`
100			`wire l1_wen = l0_wen;`
101			`reg r0_wen;`
102			`wire r1_wen = r0_wen;`
103
104
105			`reg [31:0] latch_data;`
106			`reg ack_we;`
107
108			`wire l_oe;`
109			`wire r_oe;`
110
111			`assign l_oen = ~l_oe;`
112			`assign r_oen = ~r_oe;`
113
114
115			`reg Mux;`
116			`always @ (negedge clk or negedge rstn)`
117			`begin`
118			`if(~rstn)`
119			`Mux <= 1'b0;`
120			`else`
121			`if(ack_we)`
122			`Mux <= #1 1'b1;`
123			`else`
124			`Mux <= #1 1'b0;`
125			`end`
126
127
128			`reg [addr_width-1:0] LatchedAddr;`
129			`always @ (negedge clk or negedge rstn)`
130			`begin`
131			`if(~rstn)`
132			`LatchedAddr <= 'h0;`
133			`else`
134			`if(wb_cyc_i & wb_stb_i)`
135			`LatchedAddr <= #1 wb_adr_i[addr_width+1:2];`
136			`end`
137
138
139			`assign l_a = Mux? LatchedAddr : wb_adr_i[addr_width+1:2];`
140			`assign r_a = l_a;`
141
142
143			`reg [15:0] l_read;`
144			`reg [15:0] r_read;`
145			`// Data latch from RAM (read data)`
146			`always @ (posedge clk or negedge rstn)`
147			`begin`
148			`if(~rstn)`
149			`begin`
150			`l_read <= 16'h0;`
151			`r_read <= 16'h0;`
152			`end`
153			`else`
154			`if(wb_cyc_i & wb_stb_i)`
155			`begin`
156			`l_read <= #1 l_d[15:0];`
157			`r_read <= #1 r_d[15:0];`
158			`end`
159			`end`
160
161			`assign wb_dat_o = {r_d, l_d};`
162
163			`// Mux and latch data for writing (bytes 0 and 1)`
164			`reg [15:0] l_mux;`
165			`always @ (negedge clk or negedge rstn)`
166			`begin`
167			`if(~rstn)`
168			`l_mux <= 16'h0;`
169			`else`
170			`if(~l0_wen)`
171			`begin`
172			`if(wb_sel_i[0])`
173			`l_mux[7:0] <= #1 wb_dat_i[7:0];`
174			`else`
175			`l_mux[7:0] <= #1 l_read[7:0];`
176			`if(wb_sel_i[1])`
177			`l_mux[15:8] <= #1 wb_dat_i[15:8];`
178			`else`
179			`l_mux[15:8] <= #1 l_read[15:8];`
180			`end`
181			`else`
182			`l_mux[15:0] <= #1 16'hz;`
183			`end`
184
185
186
187			`// Mux and latch data for writing (bytes 2 and 3)`
188			`reg [15:0] r_mux;`
189			`always @ (negedge clk or negedge rstn)`
190			`begin`
191			`if(~rstn)`
192			`r_mux <= 16'h0;`
193			`else`
194			`if(~r0_wen)`
195			`begin`
196			`if(wb_sel_i[2])`
197			`r_mux[7:0] <= #1 wb_dat_i[23:16];`
198			`else`
199			`r_mux[7:0] <= #1 r_read[7:0];`
200			`if(wb_sel_i[3])`
201			`r_mux[15:8] <= #1 wb_dat_i[31:24];`
202			`else`
203			`r_mux[15:8] <= #1 r_read[15:8];`
204			`end`
205			`else`
206			`r_mux <= #1 16'hz;`
207			`end`
208
209
210			`assign l_d = l_mux;`
211			`assign r_d = r_mux;`
212
213
214			`// Output enable`
215			`assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;`
216			`assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;`
217
218
219			`// WE`
220			`always @ (posedge clk or negedge rstn)`
221			`begin`
222			`if(~rstn)`
223			`l0_wen <= 1'b1;`
224			`else`
225			`if(wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[1:0]) & ~wb_ack_o)`
226			`l0_wen <= #1 1'b0;`
227			`else`
228			`l0_wen <= 1'b1;`
229			`end`
230
231
232			`// WE`
233			`always @ (posedge clk or negedge rstn)`
234			`begin`
235			`if(~rstn)`
236			`r0_wen <= 1'b1;`
237			`else`
238			`if(wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:2]) & ~wb_ack_o)`
239			`r0_wen <= #1 1'b0;`
240			`else`
241			`r0_wen <= 1'b1;`
242			`end`
243
244
245			`// CE`
246			`assign l_cen = ~(wb_cyc_i & wb_stb_i);`
247			`assign r_cen = l_cen;`
248
249
250			`always @ (posedge clk or negedge rstn)`
251			`begin`
252			`if(~rstn)`
253			`ack_we <= 1'b0;`
254			`else`
255			`if(wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
256			`ack_we <= #1 1'b1;`
257			`else`
258			`ack_we <= #1 1'b0;`
259			`end`
260
261
262			`assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) \| ack_we;`
263			`assign wb_err_o = 1'b0;`
264
265
266
267
268
269
270
271			`// synopsys translate_off`
272			`integer fsram;`
273			`initial fsram = $fopen("sram.log");`
274			`always @(posedge clk)`
275			`begin`
276			`if (~l0_wen \| ~r0_wen)`
277			`$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d, l_d});`
278			`else`
279			`if(l_oe \| r_oe)`
280			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d, l_d});`
281			`end`
282			`// synopsys translate_on`
283
284
285
286			`endmodule`