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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [cpu.v] - Blame information for rev 1765

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Line No. Rev Author Line
1 266 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
49
// no message
50
//
51
// Revision 1.4  2001/08/17 08:01:19  lampret
52
// IC enable/disable.
53
//
54
// Revision 1.3  2001/08/13 03:36:20  lampret
55
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
56
//
57
// Revision 1.2  2001/08/09 13:39:33  lampret
58
// Major clean-up.
59
//
60
// Revision 1.1  2001/07/20 00:46:03  lampret
61
// Development version of RTL. Libraries are missing.
62
//
63
//
64
 
65
// synopsys translate_off
66
`include "timescale.v"
67
// synopsys translate_on
68
`include "defines.v"
69
 
70
module cpu(
71
        // Clk & Rst
72
        clk, rst,
73
 
74
        // Insn interface
75
        ic_insn, ic_addr, ic_stall, ic_fetchop, ic_en,
76
        immu_en, immuexcept_miss, immuexcept_fault,
77
 
78
        // Debug unit
79
        ex_freeze, branch_op,
80
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except,
81
 
82
        // Data interface
83
        dclsu_stall, dclsu_unstall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en,
84
        dmmu_en, dmmuexcept_miss, dmmuexcept_fault,
85
 
86
        // Interrupt exceptions
87
        int_high, int_low,
88
 
89
        // SPR interface
90
        supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm,
91
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
92
);
93
 
94
parameter dw = `OPERAND_WIDTH;
95
parameter aw = `REGFILE_ADDR_WIDTH;
96
 
97
//
98
// I/O ports
99
//
100
 
101
//
102
// Clk & Rst
103
//
104
input                           clk;
105
input                           rst;
106
 
107
//
108
// Insn (IC) interface
109
//
110
input   [31:0]                   ic_insn;
111
output  [31:0]                   ic_addr;
112
input                           ic_stall;
113
output  [`FETCHOP_WIDTH-1:0]     ic_fetchop;
114
output                          ic_en;
115
 
116
//
117
// Insn (IMMU) interface
118
//
119
input                           immuexcept_miss;
120
input                           immuexcept_fault;
121
output                          immu_en;
122
 
123
//
124
// Debug interface
125
//
126
output                          ex_freeze;
127
output  [`BRANCHOP_WIDTH-1:0]    branch_op;
128
input                           du_stall;
129
input   [dw-1:0]         du_addr;
130
input   [dw-1:0]         du_dat_du;
131
input                           du_read;
132
input                           du_write;
133
output  [`EXCEPT_WIDTH-1:0]      du_except;
134
 
135
//
136
// Data (DC) interface
137
//
138
input                           dclsu_stall;
139
input                           dclsu_unstall;
140
output  [31:0]                   dclsu_addr;
141
input   [31:0]                   dclsu_datain;
142
output  [31:0]                   dclsu_dataout;
143
output  [`LSUOP_WIDTH-1:0]       dclsu_lsuop;
144
output                          dc_en;
145
 
146
//
147
// Data (DMMU) interface
148
//
149
input                           dmmuexcept_miss;
150
input                           dmmuexcept_fault;
151
output                          dmmu_en;
152
 
153
//
154
// SPR interface
155
//
156
output                          supv;
157
input   [dw-1:0]         spr_dat_pic;
158
input   [dw-1:0]         spr_dat_tt;
159
input   [dw-1:0]         spr_dat_pm;
160
input   [dw-1:0]         spr_dat_dmmu;
161
input   [dw-1:0]         spr_dat_immu;
162
input   [dw-1:0]         spr_dat_du;
163
output  [dw-1:0]         spr_addr;
164
output  [dw-1:0]         spr_dataout;
165
output  [31:0]                   spr_cs;
166
output                          spr_we;
167
 
168
//
169
// Interrupt exceptions
170
//
171
input                           int_high;
172
input                           int_low;
173
 
174
//
175
// Internal wires
176
//
177
wire    [31:0]                   insn;
178
wire    [31:0]                   if_pc;
179
wire    [31:2]                  lr_sav;
180
wire    [aw-1:0]         rf_addrw;
181
wire    [aw-1:0]                 rf_addra;
182
wire    [aw-1:0]                 rf_addrb;
183
wire    [dw-1:0]         simm;
184
wire    [dw-1:2]                branch_addrofs;
185
wire    [`ALUOP_WIDTH-1:0]       alu_op;
186
wire    [`SHROTOP_WIDTH-1:0]     shrot_op;
187
wire    [`COMPOP_WIDTH-1:0]      comp_op;
188
wire    [`BRANCHOP_WIDTH-1:0]    branch_op;
189
wire    [`LSUOP_WIDTH-1:0]       lsu_op;
190
wire                            if_freeze;
191
wire                            id_freeze;
192
wire                            ex_freeze;
193
wire                            wb_freeze;
194
wire    [`SEL_WIDTH-1:0] sel_a;
195
wire    [`SEL_WIDTH-1:0] sel_b;
196
wire    [`RFWBOP_WIDTH-1:0]      rfwb_op;
197
wire    [dw-1:0]         rf_dataw;
198
wire    [dw-1:0]         rf_dataa;
199
wire    [dw-1:0]         rf_datab;
200
wire    [dw-1:0]         muxed_b;
201
wire    [dw-1:0]         wb_forw;
202
wire                            wbforw_valid;
203
wire    [dw-1:0]         operand_a;
204
wire    [dw-1:0]         operand_b;
205
wire    [dw-1:0]         alu_dataout;
206
wire    [dw-1:0]         lsu_dataout;
207
wire    [dw-1:0]         sprs_dataout;
208
wire    [31:0]                   lsu_addrofs;
209
wire    [`MULTICYCLE_WIDTH-1:0]  multicycle;
210
wire    [`EXCEPT_WIDTH-1:0]      except_type;
211
wire                            except_flushpipe;
212
wire                            branch_taken;
213
wire                            flag;
214
wire                            lsu_stall;
215
wire                            branch_stall;
216
wire                            epcr_we;
217
wire                            eear_we;
218
wire                            esr_we;
219
wire                            pc_we;
220
wire    [31:0]                   epcr;
221
wire    [31:0]                   eear;
222
wire    [`SR_WIDTH-1:0]          esr;
223
wire    [`SR_WIDTH-1:0]          sr;
224
wire                            except_start;
225
wire                            except_started;
226
wire    [31:0]                   wb_pc;
227
wire    [31:0]                   wb_insn;
228
wire    [15:0]                   spr_addrimm;
229
wire                            sig_syscall;
230
wire                            sig_trap;
231
wire    [31:0]                   spr_dat_cfgr;
232
wire    [31:0]                   spr_dat_rf;
233
wire    [31:0]                   spr_dat_pc;
234
wire                            force_dslot_fetch;
235
wire                            if_stall;
236
wire                            id_macrc_op;
237
wire                            ex_macrc_op;
238
wire    [31:0]                   mult_mac_result;
239
wire                            mac_stall;
240
 
241
//
242
// Exception type going to debug unit
243
//
244
assign du_except = except_type;
245
 
246
//
247
// Data cache enable
248
//
249
//assign dc_en = 1'b1;
250
assign dc_en = sr[`SR_DCE];
251
 
252
//
253
// Instruction cache enable
254
//
255
//assign ic_en = 1'b1;
256
assign ic_en = sr[`SR_ICE];
257
 
258
//
259
// DMMU enable
260
//
261
assign dmmu_en = sr[`SR_DME];
262
 
263
//
264
// IMMU enable
265
//
266
assign immu_en = sr[`SR_IME];
267
 
268
//
269
// SUPV bit
270
//
271
assign supv = sr[`SR_SUPV];
272
 
273
//
274
// Instantiation of exception block
275
//
276
except except(
277
        .clk(clk),
278
        .rst(rst),
279
        .sig_buserr(1'b0),
280
        .sig_illegal(1'b0),
281
        .sig_align(1'b0),
282
        .sig_range(1'b0),
283
        .sig_dtlbmiss(dmmuexcept_miss),
284
        .sig_dmmufault(dmmuexcept_fault),
285
        .sig_inthigh(int_high),
286
        .sig_syscall(sig_syscall),
287
        .sig_trap(sig_trap),
288
        .sig_itlbmiss(immuexcept_miss),
289
        .sig_immufault(immuexcept_fault),
290
        .sig_intlow(int_low),
291
        .branch_taken(branch_taken),
292
        .id_freeze(id_freeze),
293
        .ex_freeze(ex_freeze),
294
        .wb_freeze(wb_freeze),
295
        .if_stall(if_stall),
296
        .if_pc(if_pc),
297
        .lr_sav(lr_sav),
298
        .except_flushpipe(except_flushpipe),
299
        .except_type(except_type),
300
        .except_start(except_start),
301
        .except_started(except_started),
302
        .wb_pc(wb_pc),
303
        .ex_pc(spr_dat_pc),
304
 
305
        .datain(operand_b),
306
        .epcr_we(epcr_we),
307
        .eear_we(eear_we),
308
        .esr_we(esr_we),
309
        .epcr(epcr),
310
        .eear(eear),
311
        .esr(esr),
312
 
313
        .lsu_addr(dclsu_addr),
314
        .sr(sr)
315
);
316
 
317
//
318
// Instantiation of instruction fetch block
319
//
320
ifetch ifetch(
321
        .clk(clk),
322
        .rst(rst),
323
        .ic_insn(ic_insn),
324
        .ic_addr(ic_addr),
325
        .ic_stall(ic_stall),
326
        .ic_fetchop(ic_fetchop),
327
        .if_freeze(if_freeze),
328
        .if_insn(insn),
329
        .if_pc(if_pc),
330
        .branch_op(branch_op),
331
        .except_type(except_type),
332
        .except_start(except_start),
333
        .branch_addrofs(branch_addrofs),
334
        .lr_restor(operand_b),
335
        .flag(flag),
336
        .taken(branch_taken),
337
        .binsn_addr(lr_sav),
338
        .epcr(epcr),
339
        .force_dslot_fetch(force_dslot_fetch),
340
        .if_stall(if_stall),
341
        .branch_stall(branch_stall),
342
        .spr_dat_i(spr_dataout),
343
        .spr_pc_we(pc_we)
344
);
345
 
346
//
347
// Instantiation of instruction decode/control logic
348
//
349
id id(
350
        .clk(clk),
351
        .rst(rst),
352
        .id_freeze(id_freeze),
353
        .ex_freeze(ex_freeze),
354
        .wb_freeze(wb_freeze),
355
        .except_flushpipe(except_flushpipe),
356
        .if_insn(insn),
357
        .branch_op(branch_op),
358
        .rf_addra(rf_addra),
359
        .rf_addrb(rf_addrb),
360
        .alu_op(alu_op),
361
        .shrot_op(shrot_op),
362
        .comp_op(comp_op),
363
        .rf_addrw(rf_addrw),
364
        .rfwb_op(rfwb_op),
365
        .wb_insn(wb_insn),
366
        .simm(simm),
367
        .branch_addrofs(branch_addrofs),
368
        .lsu_addrofs(lsu_addrofs),
369
        .sel_a(sel_a),
370
        .sel_b(sel_b),
371
        .lsu_op(lsu_op),
372
        .multicycle(multicycle),
373
        .spr_addrimm(spr_addrimm),
374
        .wbforw_valid(wbforw_valid),
375
        .sig_syscall(sig_syscall),
376
        .sig_trap(sig_trap),
377
        .force_dslot_fetch(force_dslot_fetch),
378
        .id_macrc_op(id_macrc_op),
379
        .ex_macrc_op(ex_macrc_op)
380
);
381
 
382
//
383
// Instantiation of write-back muxes
384
//
385
wbmux wbmux(
386
        .clk(clk),
387
        .rst(rst),
388
        .wb_freeze(wb_freeze),
389
        .rfwb_op(rfwb_op),
390
        .muxin_a(alu_dataout),
391
        .muxin_b(lsu_dataout),
392
        .muxin_c(sprs_dataout),
393
        .muxin_d({lr_sav, 2'b0}),
394
        .muxout(rf_dataw),
395
        .muxreg(wb_forw),
396
        .muxreg_valid(wbforw_valid)
397
);
398
 
399
//
400
// Instantiation of register file
401
//
402
rf rf(
403
        .clk(clk),
404
        .rst(rst),
405
        .addrw(rf_addrw),
406
        .dataw(rf_dataw),
407
        .id_freeze(id_freeze),
408
        .we(rfwb_op[0]),
409
        .addra(rf_addra),
410
        .dataa(rf_dataa),
411
        .addrb(rf_addrb),
412
        .datab(rf_datab),
413
        .spr_cs(spr_cs[`SPR_GROUP_SYS]),
414
        .spr_write(spr_we),
415
        .spr_addr(spr_addr),
416
        .spr_dat_i(spr_dataout),
417
        .spr_dat_o(spr_dat_rf)
418
 
419
);
420
 
421
//
422
// Instantiation of operand muxes
423
//
424
operandmuxes operandmuxes(
425
        .clk(clk),
426
        .rst(rst),
427
        .ex_freeze(ex_freeze),
428
        .rf_dataa(rf_dataa),
429
        .rf_datab(rf_datab),
430
        .ex_forw(rf_dataw),
431
        .wb_forw(wb_forw),
432
        .simm(simm),
433
        .sel_a(sel_a),
434
        .sel_b(sel_b),
435
        .operand_a(operand_a),
436
        .operand_b(operand_b),
437
        .muxed_b(muxed_b)
438
);
439
 
440
//
441
// Instantiation of CPU's ALU
442
//
443
alu alu(
444
        .clk(clk),
445
        .rst(rst),
446
        .a(operand_a),
447
        .b(operand_b),
448
        .mult_mac_result(mult_mac_result),
449
        .macrc_op(ex_macrc_op),
450
        .alu_op(alu_op),
451
        .shrot_op(shrot_op),
452
        .comp_op(comp_op),
453
        .result(alu_dataout),
454
        .flag(flag)
455
);
456
 
457
//
458
// Instantiation of CPU's ALU
459
//
460
mult_mac mult_mac(
461
        .clk(clk),
462
        .rst(rst),
463
        .id_macrc_op(id_macrc_op),
464
        .macrc_op(ex_macrc_op),
465
        .a(operand_a),
466
        .b(operand_b),
467
        .alu_op(alu_op),
468
        .result(mult_mac_result),
469
        .mac_stall_r(mac_stall)
470
);
471
 
472
//
473
// Instantiation of CPU's SPRS block
474
//
475
sprs sprs(
476
        .clk(clk),
477
        .rst(rst),
478
        .addrbase(operand_a),
479
        .addrofs(spr_addrimm),
480
        .dat_i(operand_b),
481
        .alu_op(alu_op),
482
        .flag(flag),
483
        .to_wbmux(sprs_dataout),
484
 
485
        .du_addr(du_addr),
486
        .du_dat_du(du_dat_du),
487
        .du_read(du_read),
488
        .du_write(du_write),
489
 
490
        .spr_addr(spr_addr),
491
        .spr_dat_pic(spr_dat_pic),
492
        .spr_dat_tt(spr_dat_tt),
493
        .spr_dat_pm(spr_dat_pm),
494
        .spr_dat_cfgr(spr_dat_cfgr),
495
        .spr_dat_rf(spr_dat_rf),
496
        .spr_dat_pc(spr_dat_pc),
497
        .spr_dat_dmmu(spr_dat_dmmu),
498
        .spr_dat_immu(spr_dat_immu),
499
        .spr_dat_du(spr_dat_du),
500
        .spr_dataout(spr_dataout),
501
        .spr_cs(spr_cs),
502
        .spr_we(spr_we),
503
 
504
        .epcr_we(epcr_we),
505
        .eear_we(eear_we),
506
        .esr_we(esr_we),
507
        .pc_we(pc_we),
508
        .epcr(epcr),
509
        .eear(eear),
510
        .esr(esr),
511
        .except_start(except_start),
512
        .except_started(except_started),
513
 
514
        .sr(sr),
515
        .branch_op(branch_op)
516
);
517
 
518
//
519
// Instantiation of load/store unit
520
//
521
lsu lsu(
522
        .clk(clk),
523
        .rst(rst),
524
        .addrbase(operand_a),
525
        .addrofs(lsu_addrofs),
526
        .lsu_op(lsu_op),
527
        .lsu_datain(operand_b),
528
        .lsu_dataout(lsu_dataout),
529
        .lsu_stall(lsu_stall),
530
        .dc_stall(dclsu_stall),
531
        .dc_addr(dclsu_addr),
532
        .dc_datain(dclsu_datain),
533
        .dc_dataout(dclsu_dataout),
534
        .dc_lsuop(dclsu_lsuop)
535
);
536
 
537
//
538
// Instantiation of freeze logic
539
//
540
frz_logic frz_logic(
541
        .clk(clk),
542
        .rst(rst),
543
        .multicycle(multicycle),
544
        .except_flushpipe(except_flushpipe),
545
        .lsu_stall(lsu_stall),
546
        .if_stall(if_stall),
547
        .dclsu_unstall(dclsu_unstall),
548
        .branch_stall(branch_stall),
549
        .force_dslot_fetch(force_dslot_fetch),
550
        .du_stall(du_stall),
551
        .mac_stall(mac_stall),
552
        .if_freeze(if_freeze),
553
        .id_freeze(id_freeze),
554
        .ex_freeze(ex_freeze),
555
        .wb_freeze(wb_freeze)
556
);
557
 
558
//
559
// Instantiation of configuration registers
560
//
561
cfgr cfgr(
562
        .clk(clk),
563
        .rst(clk),
564
        .spr_addr(spr_addr),
565
        .spr_dat_o(spr_dat_cfgr)
566
);
567
 
568
endmodule

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