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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dc_ram.v] - Blame information for rev 1765

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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's DC RAMs                                            ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instatiation of DC RAM blocks.                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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module dc_ram(
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        // Reset and clock
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        clk, rst,
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        // Internal i/f
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        addr, en, we, datain, dataout
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);
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parameter dw = `OPERAND_WIDTH;
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parameter aw = 11;
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//
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// I/O
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//
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input                           clk;
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input                           rst;
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input   [aw-1:0]         addr;
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input                           en;
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input   [3:0]                    we;
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input   [dw-1:0]         datain;
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output  [dw-1:0]         dataout;
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`ifdef OR1200_NO_DC
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//
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// Data cache not implemented
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//
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assign dataout = {dw{1'b0}};
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`else
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//
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// Instantiation of RAM block 0
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//
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generic_spram_2048x8 dc_ram0(
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        .clk(clk),
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        .rst(rst),
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        .ce(en),
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        .we(we[0]),
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        .oe(1'b1),
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        .addr(addr),
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        .di(datain[7:0]),
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        .do(dataout[7:0])
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);
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//
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// Instantiation of RAM block 1
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//
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generic_spram_2048x8 dc_ram1(
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        .clk(clk),
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        .rst(rst),
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        .ce(en),
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        .we(we[1]),
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        .oe(1'b1),
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        .addr(addr),
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        .di(datain[15:8]),
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        .do(dataout[15:8])
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);
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//
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// Instantiation of RAM block 2
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//
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generic_spram_2048x8 dc_ram2(
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        .clk(clk),
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        .rst(rst),
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        .ce(en),
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        .we(we[2]),
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        .oe(1'b1),
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        .addr(addr),
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        .di(datain[23:16]),
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        .do(dataout[23:16])
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);
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//
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// Instantiation of RAM block 3
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//
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generic_spram_2048x8 dc_ram3(
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        .clk(clk),
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        .rst(rst),
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        .ce(en),
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        .we(we[3]),
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        .oe(1'b1),
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        .addr(addr),
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        .di(datain[31:24]),
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        .do(dataout[31:24])
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);
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`endif
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endmodule

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