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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dc_ram.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module dc_ram(
        // Reset and clock
        clk, rst,
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = 11;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
 
assign dataout = {dw{1'b0}};
 
`else
 
//
// Instantiation of RAM block 0
//
generic_spram_2048x8 dc_ram0(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[7:0]),
        .do(dataout[7:0])
);
 
//
// Instantiation of RAM block 1
//
generic_spram_2048x8 dc_ram1(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[1]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[15:8]),
        .do(dataout[15:8])
);
 
//
// Instantiation of RAM block 2
//
generic_spram_2048x8 dc_ram2(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[2]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[23:16]),
        .do(dataout[23:16])
);
 
//
// Instantiation of RAM block 3
//
generic_spram_2048x8 dc_ram3(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[3]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[31:24]),
        .do(dataout[31:24])
);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instatiation of DC RAM blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:03 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module dc_ram(`
64			`// Reset and clock`
65			`clk, rst,`
66
67			`// Internal i/f`
68			`addr, en, we, datain, dataout`
69			`);`
70
71			parameter dw = `OPERAND_WIDTH;
72			`parameter aw = 11;`
73
74			`//`
75			`// I/O`
76			`//`
77			`input clk;`
78			`input rst;`
79			`input [aw-1:0] addr;`
80			`input en;`
81			`input [3:0] we;`
82			`input [dw-1:0] datain;`
83			`output [dw-1:0] dataout;`
84
85			`ifdef OR1200_NO_DC
86
87			`//`
88			`// Data cache not implemented`
89			`//`
90
91			`assign dataout = {dw{1'b0}};`
92
93			`else
94
95			`//`
96			`// Instantiation of RAM block 0`
97			`//`
98			`generic_spram_2048x8 dc_ram0(`
99			`.clk(clk),`
100			`.rst(rst),`
101			`.ce(en),`
102			`.we(we[0]),`
103			`.oe(1'b1),`
104			`.addr(addr),`
105			`.di(datain[7:0]),`
106			`.do(dataout[7:0])`
107			`);`
108
109			`//`
110			`// Instantiation of RAM block 1`
111			`//`
112			`generic_spram_2048x8 dc_ram1(`
113			`.clk(clk),`
114			`.rst(rst),`
115			`.ce(en),`
116			`.we(we[1]),`
117			`.oe(1'b1),`
118			`.addr(addr),`
119			`.di(datain[15:8]),`
120			`.do(dataout[15:8])`
121			`);`
122
123			`//`
124			`// Instantiation of RAM block 2`
125			`//`
126			`generic_spram_2048x8 dc_ram2(`
127			`.clk(clk),`
128			`.rst(rst),`
129			`.ce(en),`
130			`.we(we[2]),`
131			`.oe(1'b1),`
132			`.addr(addr),`
133			`.di(datain[23:16]),`
134			`.do(dataout[23:16])`
135			`);`
136
137			`//`
138			`// Instantiation of RAM block 3`
139			`//`
140			`generic_spram_2048x8 dc_ram3(`
141			`.clk(clk),`
142			`.rst(rst),`
143			`.ce(en),`
144			`.we(we[3]),`
145			`.oe(1'b1),`
146			`.addr(addr),`
147			`.di(datain[31:24]),`
148			`.do(dataout[31:24])`
149			`);`
150
151			`endif
152
153			`endmodule`

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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dc_ram.v] - Blame information for rev 1765