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////  Generic 32x32 multiplier                                    ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Generic 32x32 multiplier with pipeline stages.              ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

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////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

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//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

//

// Revision 1.2  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.1  2001/07/20 00:46:03  lampret

// Development version of RTL. Libraries are missing.

//

//

`include "timescale.v"

`include "defines.v"

// 32x32 multiplier, no input/output registers

// Registers inside Wallace trees every 8 full adder levels,

// with first pipeline after level 4

`define W 32

`define WW 64

module multp2_32x32 ( X, Y, CLK, RST, P );

input   [`W-1:0]  X;

input   [`W-1:0]  Y;

input           CLK;

input           RST;

output  [`WW-1:0]  P;

reg     [`WW-1:0]  p0;

reg     [`WW-1:0]  p1;

always @(posedge CLK or posedge RST)

        if (RST)

                p0 <= `WW'b0;

        else

                p0 <= #1 X * Y;

always @(posedge CLK or posedge RST)

        if (RST)

                p1 <= `WW'b0;

        else

                p1 <= #1 p0;

assign P = p1;

endmodule