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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instruction cache state machine                             ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/17 08:01:19  lampret
// IC enable/disable.
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define ICFSM_IDLE      3'd0
`define ICFSM_DOLOAD    3'd1
`define ICFSM_LREFILL3  3'd2
 
//
// Insn cache FSM for cache line of 16 bytes (4x singleword)
//
module ic_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        fetch_op, miss, biudata_valid, start_addr, saved_addr, refill,
        refill_first, refill_prepare, icram_we, biu_read, refill_rest,
        cntrbusy
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           miss;
input                           biudata_valid;
input   [31:0]                   start_addr;
input   [`FETCHOP_WIDTH-1:0]     fetch_op;
output  [31:0]                   saved_addr;
output                          refill;
output                          refill_first;
output                          refill_prepare;
output  [3:0]                    icram_we;
output                          biu_read;
output                          refill_rest;
output                          cntrbusy;
 
//
// Internal wires and regs
//
wire                            icache_off = 1'b0;
reg     [31:0]                   saved_addr;
reg                             refill;
reg     [3:0]                    icram_we;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             refill_first;
reg                             refill_prepare;
reg                             biu_read;
reg                             refill_rest;
reg                             cntrbusy;
 
//
// Generate ICRAM's write enable
//
always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin
        if (refill_first || !refill)
                case(fetch_op)
                        `FETCHOP_LW : icram_we = 4'b0000 ^ {4{refill_first}};
                        default : icram_we = 4'b0000;
                endcase
        else
                icram_we = {4{refill & biudata_valid}};
end
 
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                refill <= #1 1'b0;
                state <= #1 `ICFSM_IDLE;
                biu_read <= #1 1'b0;
                saved_addr <= #1 32'b0;
                refill_first <= #1 1'b0;
                refill_prepare <= #1 1'b0;
                refill_rest <= #1 1'b0;
                cntrbusy <= #1 1'b0;
                cnt <= #1 3'b0;
        end
        else
        case (state)    // synopsys full_case parallel_case
                `ICFSM_IDLE :
                        case(fetch_op)
                                `FETCHOP_LW: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: IC_FSM Load op %h  start_addr %h", $time, fetch_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `ICFSM_DOLOAD;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                default: begin
                                        state <= #1 `ICFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                        endcase
                `ICFSM_DOLOAD:
                        if (icache_off) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: IC_FSM ICache off", $time);
// synopsys translate_on
`endif
                                state <= #1 `ICFSM_DOLOAD;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                biu_read <= #1 1'b1;
                                if (biudata_valid) begin
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                end
                        end else
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: IC_FSM Load miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `ICFSM_LREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: IC_FSM Load hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `ICFSM_DOLOAD;
                                saved_addr <= #1 start_addr;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;
                        end
                `ICFSM_LREFILL3 : begin
                        if (biudata_valid && cnt) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: IC_FSM Load refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: IC_FSM Load refill end", $time, cnt);
// synopsys translate_on
`endif
                                state <= #1 `ICFSM_DOLOAD;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b0;
                                biu_read <= #1 1'b0;
                                cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
        endcase
end
 
endmodule

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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [ic_fsm.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instruction cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.3 2001/08/17 08:01:19 lampret`
51			`// IC enable/disable.`
52			`//`
53			`// Revision 1.2 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:03 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`define ICFSM_IDLE 3'd0
67			`define ICFSM_DOLOAD 3'd1
68			`define ICFSM_LREFILL3 3'd2
69
70			`//`
71			`// Insn cache FSM for cache line of 16 bytes (4x singleword)`
72			`//`
73			`module ic_fsm(`
74			`// Clock and reset`
75			`clk, rst,`
76
77			`// Internal i/f`
78			`fetch_op, miss, biudata_valid, start_addr, saved_addr, refill,`
79			`refill_first, refill_prepare, icram_we, biu_read, refill_rest,`
80			`cntrbusy`
81			`);`
82
83			`//`
84			`// I/O`
85			`//`
86			`input clk;`
87			`input rst;`
88			`input miss;`
89			`input biudata_valid;`
90			`input [31:0] start_addr;`
91			input [`FETCHOP_WIDTH-1:0] fetch_op;
92			`output [31:0] saved_addr;`
93			`output refill;`
94			`output refill_first;`
95			`output refill_prepare;`
96			`output [3:0] icram_we;`
97			`output biu_read;`
98			`output refill_rest;`
99			`output cntrbusy;`
100
101			`//`
102			`// Internal wires and regs`
103			`//`
104			`wire icache_off = 1'b0;`
105			`reg [31:0] saved_addr;`
106			`reg refill;`
107			`reg [3:0] icram_we;`
108			`reg [2:0] state;`
109			`reg [2:0] cnt;`
110			`reg refill_first;`
111			`reg refill_prepare;`
112			`reg biu_read;`
113			`reg refill_rest;`
114			`reg cntrbusy;`
115
116			`//`
117			`// Generate ICRAM's write enable`
118			`//`
119			`always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin`
120			`if (refill_first \|\| !refill)`
121			`case(fetch_op)`
122			`FETCHOP_LW : icram_we = 4'b0000 ^ {4{refill_first}};
123			`default : icram_we = 4'b0000;`
124			`endcase`
125			`else`
126			`icram_we = {4{refill & biudata_valid}};`
127			`end`
128
129			`//`
130			`// Main IC FSM`
131			`//`
132			`always @(posedge clk or posedge rst) begin`
133			`if (rst) begin`
134			`refill <= #1 1'b0;`
135			state <= #1 `ICFSM_IDLE;
136			`biu_read <= #1 1'b0;`
137			`saved_addr <= #1 32'b0;`
138			`refill_first <= #1 1'b0;`
139			`refill_prepare <= #1 1'b0;`
140			`refill_rest <= #1 1'b0;`
141			`cntrbusy <= #1 1'b0;`
142			`cnt <= #1 3'b0;`
143			`end`
144			`else`
145			`case (state) // synopsys full_case parallel_case`
146			`ICFSM_IDLE :
147			`case(fetch_op)`
148			`FETCHOP_LW: begin
149			`ifdef OR1200_VERBOSE
150			`// synopsys translate_off`
151			`$display("%t: IC_FSM Load op %h start_addr %h", $time, fetch_op, start_addr);`
152			`// synopsys translate_on`
153			`endif
154			state <= #1 `ICFSM_DOLOAD;
155			`refill <= #1 1'b0;`
156			`saved_addr <= #1 start_addr;`
157			`refill_first <= #1 1'b0;`
158			`refill_prepare <= #1 1'b1;`
159			`biu_read <= #1 1'b0;`
160			`refill_rest <= #1 1'b0;`
161			`cntrbusy <= #1 1'b0;`
162			`end`
163			`default: begin`
164			state <= #1 `ICFSM_IDLE;
165			`refill <= #1 1'b0;`
166			`refill_first <= #1 1'b0;`
167			`refill_prepare <= #1 1'b0;`
168			`refill_rest <= #1 1'b0;`
169			`biu_read <= #1 1'b0;`
170			`cntrbusy <= #1 1'b0;`
171			`end`
172			`endcase`
173			`ICFSM_DOLOAD:
174			`if (icache_off) begin`
175			`ifdef OR1200_VERBOSE
176			`// synopsys translate_off`
177			`$display("%t: IC_FSM ICache off", $time);`
178			`// synopsys translate_on`
179			`endif
180			state <= #1 `ICFSM_DOLOAD;
181			`refill <= #1 1'b1;`
182			`refill_first <= #1 1'b1;`
183			`refill_prepare <= #1 1'b0;`
184			`refill_rest <= #1 1'b0;`
185			`biu_read <= #1 1'b1;`
186			`if (biudata_valid) begin`
187			`refill <= #1 1'b0;`
188			`refill_first <= #1 1'b0;`
189			`biu_read <= #1 1'b0;`
190			`saved_addr <= #1 start_addr;`
191			`end`
192			`end else`
193			`if (miss) begin`
194			`ifdef OR1200_VERBOSE
195			`// synopsys translate_off`
196			`$display("%t: IC_FSM Load miss", $time);`
197			`// synopsys translate_on`
198			`endif
199			state <= #1 `ICFSM_LREFILL3;
200			`refill <= #1 1'b1;`
201			`refill_first <= #1 1'b1;`
202			`refill_prepare <= #1 1'b0;`
203			`refill_rest <= #1 1'b0;`
204			`cnt <= #1 3'd3;`
205			`biu_read <= #1 1'b1;`
206			`end`
207			`else begin`
208			`ifdef OR1200_VERBOSE
209			`// synopsys translate_off`
210			`$display("%t: IC_FSM Load hit", $time);`
211			`// synopsys translate_on`
212			`endif
213			state <= #1 `ICFSM_DOLOAD;
214			`saved_addr <= #1 start_addr;`
215			`refill <= #1 1'b0;`
216			`refill_first <= #1 1'b0;`
217			`refill_prepare <= #1 1'b0;`
218			`refill_rest <= #1 1'b0;`
219			`cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;`
220			`end`
221			`ICFSM_LREFILL3 : begin
222			`if (biudata_valid && cnt) begin`
223			`ifdef OR1200_VERBOSE
224			`// synopsys translate_off`
225			`$display("%t: IC_FSM Load refill %d", $time, cnt);`
226			`// synopsys translate_on`
227			`endif
228			`cnt <= #1 cnt - 'd1;`
229			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
230			`refill_first <= #1 1'b0;`
231			`end`
232			`else if (biudata_valid) begin`
233			`ifdef OR1200_VERBOSE
234			`// synopsys translate_off`
235			`$display("%t: IC_FSM Load refill end", $time, cnt);`
236			`// synopsys translate_on`
237			`endif
238			state <= #1 `ICFSM_DOLOAD;
239			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
240			`refill <= #1 1'b1;`
241			`refill_first <= #1 1'b0;`
242			`biu_read <= #1 1'b0;`
243			`cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;`
244			`end`
245			`refill_rest <= #1 ~refill_first & refill;`
246			`end`
247			`endcase`
248			`end`
249
250			`endmodule`