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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [ic_fsm.v] - Blame information for rev 1765

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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's IC FSM                                             ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instruction cache state machine                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.3  2001/08/17 08:01:19  lampret
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// IC enable/disable.
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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`define ICFSM_IDLE      3'd0
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`define ICFSM_DOLOAD    3'd1
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`define ICFSM_LREFILL3  3'd2
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//
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// Insn cache FSM for cache line of 16 bytes (4x singleword)
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//
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module ic_fsm(
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        // Clock and reset
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        clk, rst,
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        // Internal i/f
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        fetch_op, miss, biudata_valid, start_addr, saved_addr, refill,
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        refill_first, refill_prepare, icram_we, biu_read, refill_rest,
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        cntrbusy
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);
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//
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// I/O
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//
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input                           clk;
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input                           rst;
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input                           miss;
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input                           biudata_valid;
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input   [31:0]                   start_addr;
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input   [`FETCHOP_WIDTH-1:0]     fetch_op;
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output  [31:0]                   saved_addr;
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output                          refill;
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output                          refill_first;
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output                          refill_prepare;
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output  [3:0]                    icram_we;
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output                          biu_read;
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output                          refill_rest;
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output                          cntrbusy;
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//
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// Internal wires and regs
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//
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wire                            icache_off = 1'b0;
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reg     [31:0]                   saved_addr;
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reg                             refill;
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reg     [3:0]                    icram_we;
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reg     [2:0]                    state;
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reg     [2:0]                    cnt;
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reg                             refill_first;
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reg                             refill_prepare;
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reg                             biu_read;
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reg                             refill_rest;
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reg                             cntrbusy;
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//
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// Generate ICRAM's write enable
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//
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always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin
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        if (refill_first || !refill)
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                case(fetch_op)
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                        `FETCHOP_LW : icram_we = 4'b0000 ^ {4{refill_first}};
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                        default : icram_we = 4'b0000;
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                endcase
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        else
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                icram_we = {4{refill & biudata_valid}};
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end
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//
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// Main IC FSM
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//
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always @(posedge clk or posedge rst) begin
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        if (rst) begin
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                refill <= #1 1'b0;
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                state <= #1 `ICFSM_IDLE;
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                biu_read <= #1 1'b0;
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                saved_addr <= #1 32'b0;
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                refill_first <= #1 1'b0;
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                refill_prepare <= #1 1'b0;
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                refill_rest <= #1 1'b0;
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                cntrbusy <= #1 1'b0;
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                cnt <= #1 3'b0;
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        end
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        else
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        case (state)    // synopsys full_case parallel_case
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                `ICFSM_IDLE :
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                        case(fetch_op)
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                                `FETCHOP_LW: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                        $display("%t: IC_FSM Load op %h  start_addr %h", $time, fetch_op, start_addr);
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// synopsys translate_on
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`endif
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                                        state <= #1 `ICFSM_DOLOAD;
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                                        refill <= #1 1'b0;
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                                        saved_addr <= #1 start_addr;
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                                        refill_first <= #1 1'b0;
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                                        refill_prepare <= #1 1'b1;
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                                        biu_read <= #1 1'b0;
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                                        refill_rest <= #1 1'b0;
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                                        cntrbusy <= #1 1'b0;
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                                end
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                                default: begin
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                                        state <= #1 `ICFSM_IDLE;
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                                        refill <= #1 1'b0;
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                                        refill_first <= #1 1'b0;
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                                        refill_prepare <= #1 1'b0;
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                                        refill_rest <= #1 1'b0;
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                                        biu_read <= #1 1'b0;
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                                        cntrbusy <= #1 1'b0;
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                                end
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                        endcase
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                `ICFSM_DOLOAD:
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                        if (icache_off) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: IC_FSM ICache off", $time);
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// synopsys translate_on
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`endif
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                                state <= #1 `ICFSM_DOLOAD;
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                                refill <= #1 1'b1;
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                                refill_first <= #1 1'b1;
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                                refill_prepare <= #1 1'b0;
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                                refill_rest <= #1 1'b0;
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                                biu_read <= #1 1'b1;
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                                if (biudata_valid) begin
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                                        refill <= #1 1'b0;
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                                        refill_first <= #1 1'b0;
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                                        biu_read <= #1 1'b0;
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                                        saved_addr <= #1 start_addr;
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                                end
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                        end else
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                        if (miss) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: IC_FSM Load miss", $time);
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// synopsys translate_on
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`endif
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                                state <= #1 `ICFSM_LREFILL3;
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                                refill <= #1 1'b1;
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                                refill_first <= #1 1'b1;
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                                refill_prepare <= #1 1'b0;
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                                refill_rest <= #1 1'b0;
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                                cnt <= #1 3'd3;
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                                biu_read <= #1 1'b1;
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                        end
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                        else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: IC_FSM Load hit", $time);
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// synopsys translate_on
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`endif
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                                state <= #1 `ICFSM_DOLOAD;
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                                saved_addr <= #1 start_addr;
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                                refill <= #1 1'b0;
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                                refill_first <= #1 1'b0;
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                                refill_prepare <= #1 1'b0;
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                                refill_rest <= #1 1'b0;
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                                cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;
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                        end
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                `ICFSM_LREFILL3 : begin
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                        if (biudata_valid && cnt) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: IC_FSM Load refill %d", $time, cnt);
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// synopsys translate_on
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`endif
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                                cnt <= #1 cnt - 'd1;
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                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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                                refill_first <= #1 1'b0;
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                        end
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                        else if (biudata_valid) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: IC_FSM Load refill end", $time, cnt);
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// synopsys translate_on
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`endif
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                                state <= #1 `ICFSM_DOLOAD;
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                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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                                refill <= #1 1'b1;
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                                refill_first <= #1 1'b0;
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                                biu_read <= #1 1'b0;
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                                cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;
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                        end
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                        refill_rest <= #1 ~refill_first & refill;
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                end
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        endcase
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end
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endmodule

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