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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [tt.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Tick Timer                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  TT according to OR1K architectural specification.           ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module tt(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          int;            // Interrupt output
 
`ifdef TT_IMPLEMENTED
 
//
// TT Mode Register bits (or no register)
//
`ifdef TT_TTMR
reg     [31:0]   ttmr;   // TTMR bits
`else
wire    [31:0]   ttmr;   // No TTMR register
`endif
 
//
// TT Count Register bits (or no register)
//
`ifdef TT_TTCR
reg     [31:0]   ttcr;   // TTCR bits
`else
wire    [31:0]   ttcr;   // No TTCR register
`endif
 
//
// Internal wires & regs
//
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
 
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef TT_TTMR
always @(posedge clk or posedge rst)
        if (rst)
                ttmr <= 32'b0;
        else if (ttmr_sel && spr_write)
                ttmr <= #1 spr_dat_i;
        else if (ttmr[`TT_TTMR_IE])
                ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] | int;
`else
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
`endif
 
//
// Write to or increment of TTCR
//
`ifdef TT_TTCR
always @(posedge clk or posedge restart)
        if (restart)
                ttcr <= 32'b0;
        else if (ttcr_sel && spr_write)
                ttcr <= #1 spr_dat_i;
        else if (!stop)
                ttcr <= #1 ttcr + 1'd1;
`else
assign ttcr = 32'b0;
`endif
 
//
// Read TT registers
//
always @(spr_addr or ttmr or ttcr)
        case (spr_addr[`TTOFS_BITS])    // synopsys full_case parallel_case
`ifdef TT_READREGS
                `TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
                default: spr_dat_o = ttcr;
        endcase
 
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
 
//
// Restart when match and TTMR[M]==0x1 or when rst is asserted
//
assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
 
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0
//
assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) || (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
 
//
// Generate an interrupt request
//
assign int = match & ttmr[`TT_TTMR_IE];
 
`else
 
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign int = 1'b0;
 
//
// Read TT registers
//
`ifdef TT_READREGS
assign spr_dat_o = 32'b0;
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Tick Timer ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// TT according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:23 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module tt(`
64			`// RISC Internal Interface`
65			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
66			`int`
67			`);`
68
69			`//`
70			`// RISC Internal Interface`
71			`//`
72			`input clk; // Clock`
73			`input rst; // Reset`
74			`input spr_cs; // SPR CS`
75			`input spr_write; // SPR Write`
76			`input [31:0] spr_addr; // SPR Address`
77			`input [31:0] spr_dat_i; // SPR Write Data`
78			`output [31:0] spr_dat_o; // SPR Read Data`
79			`output int; // Interrupt output`
80
81			`ifdef TT_IMPLEMENTED
82
83			`//`
84			`// TT Mode Register bits (or no register)`
85			`//`
86			`ifdef TT_TTMR
87			`reg [31:0] ttmr; // TTMR bits`
88			`else
89			`wire [31:0] ttmr; // No TTMR register`
90			`endif
91
92			`//`
93			`// TT Count Register bits (or no register)`
94			`//`
95			`ifdef TT_TTCR
96			`reg [31:0] ttcr; // TTCR bits`
97			`else
98			`wire [31:0] ttcr; // No TTCR register`
99			`endif
100
101			`//`
102			`// Internal wires & regs`
103			`//`
104			`wire ttmr_sel; // TTMR select`
105			`wire ttcr_sel; // TTCR select`
106			`wire match; // Asserted when TTMR[TP]`
107			`// is equal to TTCR[27:0]`
108			`wire restart; // Restart counter when asserted`
109			`wire stop; // Stop counter when asserted`
110			`reg [31:0] spr_dat_o; // SPR data out`
111
112			`//`
113			`// TT registers address decoder`
114			`//`
115			assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
116			assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
117
118			`//`
119			`// Write to TTMR or update of TTMR[IP] bit`
120			`//`
121			`ifdef TT_TTMR
122			`always @(posedge clk or posedge rst)`
123			`if (rst)`
124			`ttmr <= 32'b0;`
125			`else if (ttmr_sel && spr_write)`
126			`ttmr <= #1 spr_dat_i;`
127			else if (ttmr[`TT_TTMR_IE])
128			ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] \| int;
129			`else
130			`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`
131			`endif
132
133			`//`
134			`// Write to or increment of TTCR`
135			`//`
136			`ifdef TT_TTCR
137			`always @(posedge clk or posedge restart)`
138			`if (restart)`
139			`ttcr <= 32'b0;`
140			`else if (ttcr_sel && spr_write)`
141			`ttcr <= #1 spr_dat_i;`
142			`else if (!stop)`
143			`ttcr <= #1 ttcr + 1'd1;`
144			`else
145			`assign ttcr = 32'b0;`
146			`endif
147
148			`//`
149			`// Read TT registers`
150			`//`
151			`always @(spr_addr or ttmr or ttcr)`
152			case (spr_addr[`TTOFS_BITS]) // synopsys full_case parallel_case
153			`ifdef TT_READREGS
154			`TT_OFS_TTMR: spr_dat_o = ttmr;
155			`endif
156			`default: spr_dat_o = ttcr;`
157			`endcase`
158
159			`//`
160			`// A match when TTMR[TP] is equal to TTCR[27:0]`
161			`//`
162			assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
163
164			`//`
165			`// Restart when match and TTMR[M]==0x1 or when rst is asserted`
166			`//`
167			assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) \|\| rst) ? 1'b1 : 1'b0;
168
169			`//`
170			`// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0`
171			`//`
172			assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) \|\| (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
173
174			`//`
175			`// Generate an interrupt request`
176			`//`
177			assign int = match & ttmr[`TT_TTMR_IE];
178
179			`else
180
181			`//`
182			`// When TT is not implemented, drive all outputs as would when TT is disabled`
183			`//`
184			`assign int = 1'b0;`
185
186			`//`
187			`// Read TT registers`
188			`//`
189			`ifdef TT_READREGS
190			`assign spr_dat_o = 32'b0;`
191			`endif
192
193			`endif
194
195			`endmodule`

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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [tt.v] - Blame information for rev 1765