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[/] [or1k/] [trunk/] [mp3/] [sw/] [mmu/] [immu.S] - Blame information for rev 1765

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Line No. Rev Author Line
1 505 lampret 
/* Basic instruction set test */
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#include "../support/spr_defs.h"
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.global _main
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.global _buserr_except
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.global _dpf_except
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.global _ipf_except
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.global _lpint_except
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.global _align_except
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.global _illegal_except
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.global _hpint_except
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.global _dtlbmiss_except
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.global _itlbmiss_except
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.global _range_except
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.global _syscall_except
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.global _res1_except
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.global _trap_except
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.global _res2_except
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_buserr_except:
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_dpf_except:
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_lpint_except:
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_align_except:
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_illegal_except:
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_hpint_except:
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_dtlbmiss_except:
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_range_except:
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_syscall_except:
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_res1_except:
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_trap_except:
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_res2_except:
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        l.nop
33 564 lampret 
        l.ori   r3,r0,0xeeee
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        l.jal   _report
35 505 lampret 
        l.nop
36 564 lampret 
        l.jal   _exit
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        l.nop
38 505 lampret 
 
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_ipf_except:
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        // Valid entry 1, 1:1, full access
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        l.addi  r14,r0,64
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        l.movhi r5,hi(0x00002000|SPR_ITLBMR_V)
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        l.ori   r5,r5,lo(0x00002000|SPR_ITLBMR_V)
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        l.mtspr r0,r5,SPR_ITLBMR_BASE(0)+1
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        l.movhi r5,hi(0x00002000|SPR_ITLBTR_SXE|SPR_ITLBTR_UXE)
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        l.ori   r5,r5,lo(0x00002000|SPR_ITLBTR_SXE|SPR_ITLBTR_UXE)
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        l.mtspr r0,r5,SPR_ITLBTR_BASE(0)+1
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        l.rfe
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        l.nop
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_itlbmiss_except:
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        // Valid entry 1, but no execute access
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        l.addi  r13,r0,128
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        l.movhi r5,hi(0x00002000|SPR_ITLBMR_V)
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        l.ori   r5,r5,lo(0x00002000|SPR_ITLBMR_V)
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        l.mtspr r0,r5,SPR_ITLBMR_BASE(0)+1
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        l.ori   r5,r0,0
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        l.mtspr r0,r5,SPR_ITLBTR_BASE(0)+1
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        l.rfe
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        l.nop
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//
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// r4, r5       - used by exception handlers
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// r7, r8       - used by main for setting TLB
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// r11          - accumulator of magic words
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// r13, r14     - used ONLY by exception handlers for magic words
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_main:
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        l.nop
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        l.addi  r11,r0,1
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        // Valid entry 0, 1:1, full access
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        l.movhi r5,hi(0x00000000|SPR_ITLBMR_V)
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        l.ori   r5,r5,lo(0x00000000|SPR_ITLBMR_V)
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        l.mtspr r0,r5,SPR_ITLBMR_BASE(0)
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        l.movhi r5,hi(0x00000000|SPR_ITLBTR_UXE|SPR_ITLBTR_SXE)
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        l.ori   r5,r5,lo(0x00000000|SPR_ITLBTR_UXE|SPR_ITLBTR_SXE)
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        l.mtspr r0,r5,SPR_ITLBTR_BASE(0)
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        // Invalidate entry 1
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        l.movhi r7,hi(0x00002000)
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        l.mtspr r0,r7,SPR_ITLBMR_BASE(0)+1
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        l.ori   r7,r0,0
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        l.mtspr r0,r7,SPR_ITLBTR_BASE(0)+1
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        // Enable IMMU
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        l.ori   r8,r0,SPR_SR_IME
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        l.mfspr r7,r0,SPR_SR
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        l.or    r7,r7,r8
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        l.mtspr r0,r7,SPR_SR
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        l.nop
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        l.nop
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        l.addi  r11,r11,16
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        // Invoke ITLB miss and IPF exceptions
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        l.jal   _immu_test
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        l.addi  r11,r11,4
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        // Some more magic words
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        l.addi  r11,r11,8
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        l.add   r11,r11,r13
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        l.add   r11,r11,r14
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        // Disable IMMU
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        l.ori   r8,r0,SPR_SR_IME
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        l.mfspr r7,r0,SPR_SR
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        l.xor   r7,r7,r8
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        l.mtspr r0,r7,SPR_SR
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        l.nop
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111 
        // Exit
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        l.nop
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        l.movhi r12,hi(0xdeadde72)
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        l.ori   r12,r12,lo(0xdeadde72)
115 564 lampret 
        l.xor   r3,r11,r12
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        l.jal   _report
117 505 lampret 
        l.nop
118 564 lampret 
        l.jal   _exit
119 505 lampret 
        l.nop
120 
        l.nop
121 
 
122 
 
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.org 0x2000
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_immu_test:
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        l.addi  r11,r11,2
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        l.jr    r9
128 
        l.nop
129 
 

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