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[/] [or1k/] [trunk/] [mp3/] [sw/] [sim.cfg] - Blame information for rev 1765

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1 505 lampret
/* sim.cfg -- Simulator configuration script file
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   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
3
 
4
This file includes a lot of help about configurations and default one
5
 
6
This file is part of OpenRISC 1000 Architectural Simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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13
This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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18
You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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22
 
23
/* INTRODUCTION
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25
   The or1ksim have various parameters, which can be set in configuration
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   files.  Multiple configurations may be used and switched between at
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   or1ksim startup.
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   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
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   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
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   all parameters are not defined, default configuration is used.
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   Users should not rely on default configuration, but rather redefine all
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   critical settings, since default configuration may differ in newer
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   versions of the or1ksim.
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   If multiple configurations are used, user can switch between them by
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   supplying -f  option when starting simulator.
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   This file may contain (standard C) only comments - no // support.
38
 
39
   Like normal configuration file, this file is divided in sections,
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   where each section is described in detail also.
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42
   Some section also have subsections. One example of such subsection is
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   block:
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45
   device 
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     instance specific parameters...
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   enddevice
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49
   which creates a device instance.
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*/
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52
 
53
/* MEMORY SECTION
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55
   This section specifies how is initial memory generated and which blocks
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   it consist of.
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58
   type = random/unknown/pattern
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      specifies the initial memory values. 'random' parameter generate
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      random memory using seed 'random_seed' parameter. 'pattern' parameter
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      fills memory with 'pattern' parameter and 'unknown' does not specify
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      how memory should be generated - the fastest option.
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64
   random_seed = 
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      random seed for randomizer, used if type = random
66
 
67
   pattern = 
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      pattern to fill memory, used if type = pattern
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70
   nmemories = 
71
      number of memory instances connected
72
 
73
   instance specific:
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     baseaddr = 
75
        memory start address
76
 
77
     size = 
78
        memory size
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80
     name = ""
81
        memory block name
82
 
83
     ce = 
84
        chip enable index of the memory instance
85
 
86
     delayr = 
87
        cycles, required for read access, -1 if instance does not support reading
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89
     delayw = 
90
        cycles, required for write access, -1 if instance does not support writing
91
 
92
     16550 = 0/1
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        0, if this device is uart 16450 and 1, if it is 16550
94
 
95
     log = ""
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        filename, where to log memory accesses to, no log, if log command is not specified
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*/
98
 
99
section memory
100
  /*random_seed = 12345
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  type = random*/
102
  pattern = 0x00
103
  type = unknown /* Fastest */
104
 
105
  nmemories = 3
106
  device 0
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    name = "Flash"
108
    ce = 0
109
    baseaddr = 0x00000000
110
    size = 0x00200000
111
    delayr = 10
112
    delayw = -1
113
  enddevice
114
 
115
  device 1
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    name = "RAM1"
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    ce = 1
118
    baseaddr = 0x40000000
119
    size = 0x00200000
120
    delayr = 2
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    delayw = 4
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  enddevice
123
 
124
  device 2
125
    name = "RAM2"
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    ce = 2
127
    baseaddr = 0x80000000
128
    size = 0x00200000
129
    delayr = 2
130
    delayw = 4
131
  enddevice
132
 
133
end
134
 
135
 
136
/* IMMU SECTION
137
 
138
    This section configures Instruction Memory Menangement Unit
139
 
140
    enabled = 0/1
141
       whether IMMU is enabled
142
       (NOTE: UPR bit is set)
143
 
144
    nsets = 
145
       number of ITLB sets; must be power of two
146
 
147
    nways = 
148
       number of ITLB ways
149
 
150
    pagesize = 
151
       instruction page size; must be power of two
152
 
153
    entrysize = 
154
       instruction entry size in bytes
155
 
156
    ustates = 
157
       number of ITLB usage states (2, 3, 4 etc., max is 4)
158
*/
159
 
160
section immu
161
  enabled = 0
162
  nsets = 32
163
  nways = 1
164
  pagesize = 8192
165
end
166
 
167
 
168
/* DMMU SECTION
169
 
170
    This section configures Data Memory Menangement Unit
171
 
172
    enabled = 0/1
173
       whether DMMU is enabled
174
       (NOTE: UPR bit is set)
175
 
176
    nsets = 
177
       number of DTLB sets; must be power of two
178
 
179
    nways = 
180
       number of DTLB ways
181
 
182
    pagesize = 
183
       data page size; must be power of two
184
 
185
    entrysize = 
186
       data entry size in bytes
187
 
188
    ustates = 
189
       number of DTLB usage states (2, 3, 4 etc., max is 4)
190
*/
191
 
192
section dmmu
193
  enabled = 0
194
  nsets = 32
195
  nways = 1
196
  pagesize = 8192
197
end
198
 
199
 
200
/* IC SECTION
201
 
202
    This section configures Instruction Cache
203
 
204
    enabled = 0/1
205
       whether IC is enabled
206
       (NOTE: UPR bit is set)
207
 
208
    nsets = 
209
       number of IC sets; must be power of two
210
 
211
    nways = 
212
       number of IC ways
213
 
214
    blocksize = 
215
       IC block size in bytes; must be power of two
216
 
217
    ustates = 
218
       number of IC usage states (2, 3, 4 etc., max is 4)
219
*/
220
 
221
section ic
222
  enabled = 0
223
  nsets = 512
224
  nways = 1
225
  blocksize = 16
226
end
227
 
228
 
229
/* DC SECTION
230
 
231
    This section configures Data Cache
232
 
233
    enabled = 0/1
234
       whether DC is enabled
235
       (NOTE: UPR bit is set)
236
 
237
    nsets = 
238
       number of DC sets; must be power of two
239
 
240
    nways = 
241
       number of DC ways
242
 
243
    blocksize = 
244
       DC block size in bytes; must be power of two
245
 
246
    ustates = 
247
       number of DC usage states (2, 3, 4 etc., max is 4)
248
*/
249
 
250
section dc
251
  enabled = 0
252
  nsets = 512
253
  nways = 1
254
  blocksize = 16
255
end
256
 
257
/* SIM SECTION
258
 
259
  This section specifies how should sim behave.
260
 
261
  verbose = 0/1
262
      whether to print out extra messages
263
 
264
  debug = 0-9
265
      = 0 disabled debug messages
266
      1-9 level of sim debug information, greater the number more verbose is
267
          the output
268
 
269
  profile = 0/1
270
      whether to generate profiling file 'sim.profile'
271
 
272
  prof_fn = ""
273
      filename, where to generate profiling info, used
274
      only if 'profile' is set
275
 
276
  history = 0/1
277
      whether instruction execution flow is tracked for
278
      display by simulator hist command. Useful for
279
      back-trace debugging.
280
 
281
  iprompt = 0/1
282
      whether we strart in interactive prompt
283
 
284
  exe_log = 0/1
285
      whether execution log should be generated
286
 
287
  exe_log_fn = ""
288
      where to put execution log in, used only if 'exe_log'
289
      is set
290
 
291
  clkcycle = [ps|ns|us|ms]
292
      specifies time measurement for one cycle
293
*/
294
 
295
section sim
296
  /* verbose = 1 */
297
  debug = 0
298
  profile = 0
299
  prof_fn = "sim.profile"
300
 
301
  history = 1
302
  /* iprompt = 0 */
303
  exe_log = 1
304
  exe_log_fn = "executed.log"
305
  clkcycle = 4ns
306
end
307
 
308
 
309
/* SECTION VAPI
310
 
311
    This section configures Verification API, used for Advanced
312
    Core Verification.
313
 
314
    enabled = 0/1
315
        whether to start VAPI server
316
 
317
    server_port = 
318
        TCP/IP port to start VAPI server on
319
 
320
    log_enabled = 0/1
321
       whether logging of VAPI requests is enabled
322
 
323
    vapi_fn = 
324
       specifies filename where to log into, if log_enabled is selected
325
*/
326
 
327
section VAPI
328
  enabled = 0
329
  server_port = 9998
330
  log_enabled = 0
331
  vapi_log_fn = "vapi.log"
332
end
333
 
334
 
335
/* CPU SECTION
336
 
337
   This section specifies various CPU parameters.
338
 
339
   ver = 
340
   rev = 
341
      specifies version and revision of the CPU used
342
 
343
   upr = 
344
      changes the upr register
345
 
346
   superscalar = 0/1
347
      whether CPU is scalar or superscalar
348
      (modify cpu/or32/execute.c to tune superscalar model)
349
 
350
   hazards = 0/1
351
      whether data hazards are tracked in superscalar CPU
352
      and displayed by the simulator r command
353
 
354
   dependstats = 0/1
355
      whether inter-instruction dependencies are calculated
356
      and displayed by simulator stats command.
357
 
358
   slp = 0/1
359
      calculation of subroutine level parallelism. Displayed
360
      by simulator stats command.
361
 
362
   btic = 0/1
363
      enable branch target instruction cache model
364
 
365
   bpb = 0/1
366
      enable branch prediction buffer model
367
 
368
      parameters for CPU analysis
369
*/
370
 
371
section cpu
372
  ver = 0x1200
373
  rev = 0x0001
374
  /* upr = */
375
  superscalar = 0
376
  hazards = 0
377
  dependstats = 0
378
  slp = 0
379
  btic = 0
380
  bpb = 0
381
end
382
 
383
 
384
/* DEBUG SECTION
385
 
386
   This sections specifies how debug unit should behave.
387
 
388
   enabled = 0/1
389
      whether debug unit is enabled
390
 
391
   gdb_enabled = 0/1
392
      whether to start gdb server at 'server_port' port
393
 
394
   server_port = 
395
      TCP/IP port to start gdb server on, used only if gdb_enabled
396
      is set
397
 
398
section debug
399
  enabled = 0
400
  gdb_enabled = 0
401
  server_port = 9999
402
end
403
 
404
 
405
/* MC SECTION
406
 
407
   This section configures the memory controller
408
 
409
   enabled = 0/1
410
      whether memory controller is enabled
411
 
412
   baseaddr = 
413
      address of first MC register
414
 
415
   POC = 
416
      Power On Configuration register
417
*/
418
 
419
section mc
420
  enabled = 0
421
  baseaddr = 0xa0000000
422
  POC = 0x00000008                 /* Power on configuration register */
423
end
424
 
425
 
426
/* UART SECTION
427
 
428
   This section configures UARTs
429
 
430
   enabled = 0/1
431
      whether uarts are enabled
432
 
433
   nuarts = 
434
      make specified number of instances, configure each
435
      instance within device - enddevice construct.
436
 
437
   instance specific:
438
     baseaddr = 
439
        address of first UART register for this device
440
 
441
     rx_file = ""
442
        filename, where to read data from
443
 
444
     tx_file = ""
445
        filename, where to write data to
446
 
447
     irq = 
448
        irq number for this device
449
 
450
     16550 = 0/1
451
        0, if this device is uart 16450 and 1, if it is 16550
452
 
453
     jitter = 
454
        in msecs... time to block, -1 to disable it
455
 
456
     vapi_id = 
457
        VAPI id of this instance
458
*/
459
 
460
section uart
461
  enabled = 0
462
  nuarts = 1
463
 
464
  device 0
465
    baseaddr = 0x80000000
466
    irq = 2
467
    rxfile = "/tmp/uart0.rx"
468
    txfile = "/tmp/uart0.tx"
469
    jitter = -1                     /* async behaviour */
470
  enddevice
471
end
472
 
473
 
474
/* DMA SECTION
475
 
476
   This section configures DMAs
477
 
478
   enabled = 0/1
479
      whether DMAs are enabled
480
 
481
   ndmas = 
482
      make specified number of instances, configure each
483
      instance within device - enddevice construct.
484
 
485
   instance specific:
486
     baseaddr = 
487
        address of first DMA register for this device
488
 
489
     irq = 
490
        irq number for this device
491
 
492
     vapi_id = 
493
        VAPI id of this instance
494
*/
495
 
496
section dma
497
  enabled = 0
498
  ndmas = 1
499
 
500
  device 0
501
    baseaddr = 0x90000000
502
    irq = 4
503
  enddevice
504
end
505
 
506
 
507
/* ETHERNET SECTION
508
 
509
   This section configures ethernets
510
 
511
   enabled = 0/1
512
      whether ethernets are enabled
513
 
514
   nethernets = 
515
      make specified number of instances, configure each
516
      instance within device - enddevice construct.
517
 
518
   instance specific:
519
     baseaddr = 
520
        address of first ethernet register for this device
521
 
522
     dma = 
523
        which controller is this ethernet "connected" to
524
 
525
     rx_channel = 
526
        DMA channel used for RX
527
 
528
     tx_channel = 
529
        DMA channel used for TX
530
 
531
     rx_file = ""
532
        filename, where to read data from
533
 
534
     tx_file = ""
535
        filename, where to write data to
536
 
537
     vapi_id = 
538
        VAPI id of this instance
539
*/
540
 
541
section ethernet
542
  enabled = 0
543
  nethernets = 1
544
 
545
  device 0
546
    baseaddr = 0x88000000
547
    dma = 0
548
    tx_channel = 0
549
    rx_channel = 1
550
    rxfile = "/tmp/eth0.rx"
551
    txfile = "/tmp/eth0.tx"
552
  enddevice
553
end
554
 
555
/* TICK TIMER SECTION
556
 
557
    This section configures tick timer
558
 
559
    enabled = 0/1
560
      whether tick timer is enabled
561
 
562
    irq = 
563
      irq number
564
*/
565
 
566
section tick
567
  enabled = 0
568
  irq = 3
569
end

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