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[/] [or1k/] [trunk/] [mw/] [src/] [drivers/] [vgaplan4.h] - Blame information for rev 1773

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1 673 markom 
/*
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 * Copyright (c) 1999 Greg Haerr <greg@censoft.com>
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 *
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 * Header file for EGA/VGA 16 color 4 planes screen driver
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 * Added functions for Hercules access
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 *
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 */
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#define SLOWVGA         0        /* =1 for outb rather than outw instructions*/
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#ifdef __PACIFIC__
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#define HAVEBLIT        0
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#else
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#define HAVEBLIT        1       /* =0 to exclude blitting in vgaplan4 drivers*/
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#endif
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#if UNIX & !ELKS
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#define HAVEFARPTR      1
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#define FAR
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#endif
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#if LINUX
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#ifdef __GLIBC__
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#include <sys/io.h>             /* for outb def's, requires -O */
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#else
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#include <asm/io.h>             /* for outb def's on 2.3.x*/
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#endif
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#include <unistd.h>
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#define HAVEFARPTR      1
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#define FAR
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#define HAVEIOPERM      1       /* has ioperm() system call*/
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#endif
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#if MSDOS
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#define HAVEFARPTR      1       /* compiler has _far extension*/
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#ifdef __PACIFIC__
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#include <dos.h>
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#define FAR             far
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#else
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#define FAR             _far
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#endif
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#endif
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#if __rtems__
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#define HAVEFARPTR      1
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#define FAR
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#include <i386_io.h>
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#endif
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#if MSDOS | ELKS
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/* make far ptr*/
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#define MK_FP(seg,ofs)  ((FARADDR)(((unsigned long)(seg) << 16) | (unsigned)(ofs)))
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#define EGA_BASE        MK_FP(0xa000, 0)
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#else
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#define EGA_BASE        ((unsigned char *)0xa0000)
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#endif
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#if HAVEFARPTR
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/* far ptr access to screen*/
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typedef volatile unsigned char FAR * FARADDR;
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#if _MINIX
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/* get byte at address*/
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extern unsigned char GETBYTE_FP(FARADDR);
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/* put byte at address*/
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extern void PUTBYTE_FP(FARADDR,unsigned char);
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/* read-modify-write at address*/
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extern void RMW_FP(FARADDR);
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#else
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/* get byte at address*/
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#define GETBYTE_FP(addr)        (*(FARADDR)(addr))
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/* put byte at address*/
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#define PUTBYTE_FP(addr,val)    ((*(FARADDR)(addr)) = (val))
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/* read-modify-write at address*/
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#define RMW_FP(addr)            ((*(FARADDR)(addr)) |= 1)
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/* or byte at address*/
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#define ORBYTE_FP(addr,val)     ((*(FARADDR)(addr)) |= (val))
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/* and byte at address*/
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#define ANDBYTE_FP(addr,val)    ((*(FARADDR)(addr)) &= (val))
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#endif
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#else
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/* for bcc with no _far extension*/
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typedef unsigned long   FARADDR;
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/* get byte at address*/
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extern unsigned char GETBYTE_FP(FARADDR);
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/* put byte at address*/
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extern void PUTBYTE_FP(FARADDR,unsigned char);
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/* read-modify-write at address*/
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extern void RMW_FP(FARADDR);
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/* or byte at address*/
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extern void ORBYTE_FP(FARADDR,unsigned char);
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/* and byte at address*/
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extern void ANDBYTE_FP(FARADDR,unsigned char);
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#endif
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#if MSDOS
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#define outb(val,port)  outp(port,val)
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#endif
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#if ELKS
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#define outb(val,port)  outportb(port,val)
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#define outw(val,port)  outport(port,val)
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extern int  inportb(int port);
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extern void outportb(int port,unsigned char data);
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extern void outport(int port,int data);
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#endif
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/* external routines*/
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FARADDR         int10(int ax,int bx);
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/* external routines implementing planar ega/vga access*/
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/* vgaplan4.c portable C, asmplan4.s asm, or ELKS asm elkplan4.c driver*/
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int             ega_init(PSD psd);
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void            ega_drawpixel(PSD psd,unsigned int x,unsigned int y,
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                        MWPIXELVAL c);
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MWPIXELVAL      ega_readpixel(PSD psd,unsigned int x,unsigned int y);
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void            ega_drawhorzline(PSD psd,unsigned int x1,unsigned int x2,
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                        unsigned int y,MWPIXELVAL c);
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void            ega_drawvertline(PSD psd,unsigned int x,unsigned int y1,
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                        unsigned int y2, MWPIXELVAL c);
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#if HAVEBLIT
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/* memplan4.c*/
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void            ega_blit(PSD dstpsd, MWCOORD dstx, MWCOORD dsty, MWCOORD w,
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                        MWCOORD h,PSD srcpsd,MWCOORD srcx,MWCOORD srcy,long op);
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#endif
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/* vgainit.c - direct hw init*/
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void            ega_hwinit(void);
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void            ega_hwterm(void);
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#if _MINIX
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#define outb(v, p)      outb(p, v)
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#define outw(v, p)      outw(p, v)
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#endif
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#if SLOWVGA
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/* use outb rather than outw instructions for older, slower VGA's*/
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/* Program the Set/Reset Register for drawing in color COLOR for write
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   mode 0. */
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#define set_color(c)            { outb (0, 0x3ce); outb (c, 0x3cf); }
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/* Set the Enable Set/Reset Register. */
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#define set_enable_sr(mask) { outb (1, 0x3ce); outb (mask, 0x3cf); }
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/* Select the Bit Mask Register on the Graphics Controller. */
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#define select_mask()           { outb (8, 0x3ce); }
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/* Program the Bit Mask Register to affect only the pixels selected in
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   MASK.  The Bit Mask Register must already have been selected with
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   select_mask (). */
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#define set_mask(mask)          { outb (mask, 0x3cf); }
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#define select_and_set_mask(mask) { outb (8, 0x3ce); outb (mask, 0x3cf); }
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/* Set the Data Rotate Register.  Bits 0-2 are rotate count, bits 3-4
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   are logical operation (0=NOP, 1=AND, 2=OR, 3=XOR). */
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#define set_op(op)              { outb (3, 0x3ce); outb (op, 0x3cf); }
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/* Set the Memory Plane Write Enable register. */
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#define set_write_planes(mask) { outb (2, 0x3c4); outb (mask, 0x3c5); }
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/* Set the Read Map Select register. */
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#define set_read_plane(plane)   { outb (4, 0x3ce); outb (plane, 0x3cf); }
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/* Set the Graphics Mode Register.  The write mode is in bits 0-1, the
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   read mode is in bit 3. */
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#define set_mode(mode)          { outb (5, 0x3ce); outb (mode, 0x3cf); }
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#else /* !SLOWVGA*/
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/* use outw rather than outb instructions for new VGAs*/
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/* Program the Set/Reset Register for drawing in color COLOR for write
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   mode 0. */
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#define set_color(c)            { outw ((c)<<8, 0x3ce); }
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/* Set the Enable Set/Reset Register. */
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#define set_enable_sr(mask)     { outw (1|((mask)<<8), 0x3ce); }
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/* Select the Bit Mask Register on the Graphics Controller. */
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#define select_mask()           { outb (8, 0x3ce); }
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/* Program the Bit Mask Register to affect only the pixels selected in
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   MASK.  The Bit Mask Register must already have been selected with
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   select_mask (). */
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#define set_mask(mask)          { outb (mask, 0x3cf); }
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#define select_and_set_mask(mask) { outw (8|((mask)<<8), 0x3ce); }
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/* Set the Data Rotate Register.  Bits 0-2 are rotate count, bits 3-4
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   are logical operation (0=NOP, 1=AND, 2=OR, 3=XOR). */
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#define set_op(op)              { outw (3|((op)<<8), 0x3ce); }
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/* Set the Memory Plane Write Enable register. */
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#define set_write_planes(mask) { outw (2|((mask)<<8), 0x3c4); }
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/* Set the Read Map Select register. */
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#define set_read_plane(plane)   { outw (4|((plane)<<8), 0x3ce); }
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/* Set the Graphics Mode Register.  The write mode is in bits 0-1, the
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   read mode is in bit 3. */
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#define set_mode(mode)          { outw (5|((mode)<<8), 0x3ce); }
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#endif /* SLOWVGA*/

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