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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Blame information for rev 1765

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1 504 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Data Cache top level                               ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all IC blocks.                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
47 1267 lampret
// Revision 1.7.4.2  2003/12/09 11:46:48  simons
48
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
49
//
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// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
51
// Added embedded memory QMEM.
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//
53 1200 markom
// Revision 1.7  2002/10/17 20:04:40  lampret
54
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
55
//
56 1063 lampret
// Revision 1.6  2002/03/29 15:16:55  lampret
57
// Some of the warnings fixed.
58
//
59 788 lampret
// Revision 1.5  2002/02/11 04:33:17  lampret
60
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
61
//
62 660 lampret
// Revision 1.4  2002/02/01 19:56:54  lampret
63
// Fixed combinational loops.
64
//
65 636 lampret
// Revision 1.3  2002/01/28 01:16:00  lampret
66
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
67
//
68 617 lampret
// Revision 1.2  2002/01/14 06:18:22  lampret
69
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
70
//
71 562 lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
72
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
73
//
74 504 lampret
// Revision 1.10  2001/10/21 17:57:16  lampret
75
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
76
//
77
// Revision 1.9  2001/10/14 13:12:09  lampret
78
// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
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// Revision 1.4  2001/08/13 03:36:20  lampret
84
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3  2001/08/09 13:39:33  lampret
87
// Major clean-up.
88
//
89
// Revision 1.2  2001/07/22 03:31:53  lampret
90
// Fixed RAM's oen bug. Cache bypass under development.
91
//
92
// Revision 1.1  2001/07/20 00:46:03  lampret
93
// Development version of RTL. Libraries are missing.
94
//
95
//
96
 
97
// synopsys translate_off
98
`include "timescale.v"
99
// synopsys translate_on
100
`include "or1200_defines.v"
101
 
102
//
103
// Data cache
104
//
105
module or1200_ic_top(
106
        // Rst, clk and clock control
107
        clk, rst,
108
 
109
        // External i/f
110
        icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
111
        icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
112
 
113
        // Internal i/f
114
        ic_en,
115 1267 lampret
        icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
116
        icqmem_sel_i, icqmem_tag_i,
117
        icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
118 504 lampret
 
119 1063 lampret
`ifdef OR1200_BIST
120
        // RAM BIST
121 1200 markom
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
122 1063 lampret
`endif
123
 
124 504 lampret
        // SPRs
125
        spr_cs, spr_write, spr_dat_i
126
);
127
 
128
parameter dw = `OR1200_OPERAND_WIDTH;
129
 
130
//
131
// I/O
132
//
133
 
134
//
135
// Clock and reset
136
//
137
input                           clk;
138
input                           rst;
139
 
140
//
141
// External I/F
142
//
143
output  [dw-1:0]         icbiu_dat_o;
144
output  [31:0]                   icbiu_adr_o;
145
output                          icbiu_cyc_o;
146
output                          icbiu_stb_o;
147
output                          icbiu_we_o;
148
output  [3:0]                    icbiu_sel_o;
149
output                          icbiu_cab_o;
150
input   [dw-1:0]         icbiu_dat_i;
151
input                           icbiu_ack_i;
152
input                           icbiu_err_i;
153
 
154
//
155
// Internal I/F
156
//
157
input                           ic_en;
158 1267 lampret
input   [31:0]                   icqmem_adr_i;
159
input                           icqmem_cycstb_i;
160
input                           icqmem_ci_i;
161
input   [3:0]                    icqmem_sel_i;
162
input   [3:0]                    icqmem_tag_i;
163
output  [dw-1:0]         icqmem_dat_o;
164
output                          icqmem_ack_o;
165
output                          icqmem_rty_o;
166
output                          icqmem_err_o;
167
output  [3:0]                    icqmem_tag_o;
168 504 lampret
 
169 1063 lampret
`ifdef OR1200_BIST
170 504 lampret
//
171 1063 lampret
// RAM BIST
172
//
173 1267 lampret
input mbist_si_i;
174
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
175
output mbist_so_o;
176 1063 lampret
`endif
177
 
178
//
179 504 lampret
// SPR access
180
//
181
input                           spr_cs;
182
input                           spr_write;
183
input   [31:0]                   spr_dat_i;
184
 
185
//
186
// Internal wires and regs
187
//
188
wire                            tag_v;
189
wire    [`OR1200_ICTAG_W-2:0]    tag;
190
wire    [dw-1:0]         to_icram;
191
wire    [dw-1:0]         from_icram;
192
wire    [31:0]                   saved_addr;
193
wire    [3:0]                    icram_we;
194
wire                            ictag_we;
195
wire    [31:0]                   ic_addr;
196
wire                            icfsm_biu_read;
197
reg                             tagcomp_miss;
198
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
199
wire                            ictag_en;
200
wire                            ictag_v;
201
wire                            ic_inv;
202
wire                            icfsm_first_hit_ack;
203
wire                            icfsm_first_miss_ack;
204
wire                            icfsm_first_miss_err;
205
wire                            icfsm_burst;
206 660 lampret
wire                            icfsm_tag_we;
207 1063 lampret
`ifdef OR1200_BIST
208
//
209
// RAM BIST
210
//
211 1200 markom
wire                            mbist_ram_so;
212
wire                            mbist_tag_so;
213
wire                            mbist_ram_si = mbist_si_i;
214
wire                            mbist_tag_si = mbist_ram_so;
215
assign                          mbist_so_o = mbist_tag_so;
216 1063 lampret
`endif
217 504 lampret
 
218
//
219
// Simple assignments
220
//
221
assign icbiu_adr_o = ic_addr;
222
assign ic_inv = spr_cs & spr_write;
223 660 lampret
assign ictag_we = icfsm_tag_we | ic_inv;
224 504 lampret
assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
225
assign ictag_en = ic_inv | ic_en;
226
assign ictag_v = ~ic_inv;
227
 
228
//
229
// Data to BIU is from ICRAM when IC is enabled or from LSU when
230
// IC is disabled
231
//
232
assign icbiu_dat_o = 32'h00000000;
233
 
234
//
235
// Bypases of the IC when IC is disabled
236
//
237 1267 lampret
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
238
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
239 504 lampret
assign icbiu_we_o = 1'b0;
240 1267 lampret
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
241 504 lampret
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
242 1267 lampret
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
243
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
244 504 lampret
 
245
//
246
// CPU normal and error termination
247
//
248 1267 lampret
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
249
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
250 504 lampret
 
251
//
252
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
253
//
254 1267 lampret
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
255 504 lampret
 
256
//
257
// Select between input data generated by LSU or by BIU
258
//
259
assign to_icram = icbiu_dat_i;
260
 
261
//
262
// Select between data generated by ICRAM or passed by BIU
263
//
264 1267 lampret
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
265 504 lampret
 
266
//
267
// Tag comparison
268
//
269
always @(tag or saved_addr or tag_v) begin
270
        if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
271
                tagcomp_miss = 1'b1;
272
        else
273
                tagcomp_miss = 1'b0;
274
end
275
 
276
//
277
// Instantiation of IC Finite State Machine
278
//
279
or1200_ic_fsm or1200_ic_fsm(
280
        .clk(clk),
281
        .rst(rst),
282
        .ic_en(ic_en),
283 1267 lampret
        .icqmem_cycstb_i(icqmem_cycstb_i),
284
        .icqmem_ci_i(icqmem_ci_i),
285 504 lampret
        .tagcomp_miss(tagcomp_miss),
286
        .biudata_valid(icbiu_ack_i),
287
        .biudata_error(icbiu_err_i),
288 1267 lampret
        .start_addr(icqmem_adr_i),
289 504 lampret
        .saved_addr(saved_addr),
290
        .icram_we(icram_we),
291
        .biu_read(icfsm_biu_read),
292
        .first_hit_ack(icfsm_first_hit_ack),
293
        .first_miss_ack(icfsm_first_miss_ack),
294
        .first_miss_err(icfsm_first_miss_err),
295 660 lampret
        .burst(icfsm_burst),
296
        .tag_we(icfsm_tag_we)
297 504 lampret
);
298
 
299
//
300
// Instantiation of IC main memory
301
//
302
or1200_ic_ram or1200_ic_ram(
303
        .clk(clk),
304
        .rst(rst),
305 1063 lampret
`ifdef OR1200_BIST
306
        // RAM BIST
307 1200 markom
        .mbist_si_i(mbist_ram_si),
308
        .mbist_so_o(mbist_ram_so),
309
        .mbist_ctrl_i(mbist_ctrl_i),
310 1063 lampret
`endif
311 504 lampret
        .addr(ic_addr[`OR1200_ICINDXH:2]),
312
        .en(ic_en),
313
        .we(icram_we),
314
        .datain(to_icram),
315
        .dataout(from_icram)
316
);
317
 
318
//
319
// Instantiation of IC TAG memory
320
//
321
or1200_ic_tag or1200_ic_tag(
322
        .clk(clk),
323
        .rst(rst),
324 1063 lampret
`ifdef OR1200_BIST
325
        // RAM BIST
326 1200 markom
        .mbist_si_i(mbist_tag_si),
327
        .mbist_so_o(mbist_tag_so),
328
        .mbist_ctrl_i(mbist_ctrl_i),
329 1063 lampret
`endif
330 504 lampret
        .addr(ictag_addr),
331
        .en(ictag_en),
332
        .we(ictag_we),
333
        .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
334
        .tag_v(tag_v),
335
        .tag(tag)
336
);
337
 
338
endmodule

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