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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////                                                              ////
////  To Do:                                                      ////
////   - add support for other RAM's                              ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_128x32(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({1'b0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({1'b0, addr}),
        .DI(di[31:16]),
        .EN(ce),
        .WE(we),
        .DO(doq[31:16])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(rst),
        .ADDR({2'b00, addr}),
        .DI(di),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO(doq),
        .DOP()
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	1273	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// ////`
20			`//// Supported FPGA RAMs are: ////`
21	1582	jcastillo	`//// - Xilinx Virtex RAMB16 ////`
22			`//// - Xilinx Virtex RAMB4 ////`
23	1273	simont	`//// ////`
24			`//// To Do: ////`
25			`//// - add support for other RAM's ////`
26			`//// - xilinx rams need external tri-state logic ////`
27			`//// - fix avant! two-port ram ////`
28			`//// - add additional RAMs ////`
29			`//// ////`
30			`//// Author(s): ////`
31			`//// - Damjan Lampret, lampret@opencores.org ////`
32			`//// ////`
33			`//////////////////////////////////////////////////////////////////////`
34			`//// ////`
35			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
36			`//// ////`
37			`//// This source file may be used and distributed without ////`
38			`//// restriction provided that this copyright statement is not ////`
39			`//// removed from the file and that any derivative work contains ////`
40			`//// the original copyright notice and the associated disclaimer. ////`
41			`//// ////`
42			`//// This source file is free software; you can redistribute it ////`
43			`//// and/or modify it under the terms of the GNU Lesser General ////`
44			`//// Public License as published by the Free Software Foundation; ////`
45			`//// either version 2.1 of the License, or (at your option) any ////`
46			`//// later version. ////`
47			`//// ////`
48			`//// This source is distributed in the hope that it will be ////`
49			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
50			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
51			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
52			`//// details. ////`
53			`//// ////`
54			`//// You should have received a copy of the GNU Lesser General ////`
55			`//// Public License along with this source; if not, download it ////`
56			`//// from http://www.opencores.org/lgpl.shtml ////`
57			`//// ////`
58			`//////////////////////////////////////////////////////////////////////`
59			`//`
60			`// CVS Revision History`
61			`//`
62			`// $Log: not supported by cvs2svn $`
63	1582	jcastillo	`// Revision 1.2 2004/06/08 18:15:32 lampret`
64			`// Changed behavior of the simulation generic models`
65			`//`
66	1291	lampret	`// Revision 1.1 2004/04/08 11:00:46 simont`
67			`// Add support for 512B instruction cache.`
68	1273	simont	`//`
69			`//`
70	1291	lampret	`//`
71	1273	simont
72			`// synopsys translate_off`
73			`include "timescale.v"
74			`// synopsys translate_on`
75			`include "or1200_defines.v"
76
77			`module or1200_spram_128x32(`
78			`ifdef OR1200_BIST
79			`// RAM BIST`
80			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
81			`endif
82			`// Generic synchronous single-port RAM interface`
83	1291	lampret	`clk, rst, ce, we, oe, addr, di, doq`
84	1273	simont	`);`
85
86			`//`
87			`// Default address and data buses width`
88			`//`
89			`parameter aw = 7;`
90			`parameter dw = 32;`
91
92			`ifdef OR1200_BIST
93			`//`
94			`// RAM BIST`
95			`//`
96			`input mbist_si_i;`
97			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
98			`output mbist_so_o;`
99			`endif
100
101			`//`
102			`// Generic synchronous single-port RAM interface`
103			`//`
104			`input clk; // Clock`
105			`input rst; // Reset`
106			`input ce; // Chip enable input`
107			`input we; // Write enable input`
108			`input oe; // Output enable input`
109			`input [aw-1:0] addr; // address bus inputs`
110			`input [dw-1:0] di; // input data bus`
111	1291	lampret	`output [dw-1:0] doq; // output data bus`
112	1273	simont
113			`//`
114			`// Internal wires and registers`
115			`//`
116
117			`ifdef OR1200_ARTISAN_SSP
118			`else
119			`ifdef OR1200_VIRTUALSILICON_SSP
120			`else
121			`ifdef OR1200_BIST
122			`endif
123			`endif
124			`endif
125
126			`ifdef OR1200_ARTISAN_SSP
127
128			`//`
129			`// Instantiation of ASIC memory:`
130			`//`
131			`// Artisan Synchronous Single-Port RAM (ra1sh)`
132			`//`
133			`ifdef UNUSED
134			`else
135			`ifdef OR1200_BIST
136			`else
137			`endif
138			`endif
139			`ifdef OR1200_BIST
140			`endif
141			`else
142
143			`ifdef OR1200_AVANT_ATP
144
145			`//`
146			`// Instantiation of ASIC memory:`
147			`//`
148			`// Avant! Asynchronous Two-Port RAM`
149			`//`
150
151			`else
152
153			`ifdef OR1200_VIRAGE_SSP
154
155			`//`
156			`// Instantiation of ASIC memory:`
157			`//`
158			`// Virage Synchronous 1-port R/W RAM`
159			`//`
160
161			`else
162
163			`ifdef OR1200_VIRTUALSILICON_SSP
164
165			`//`
166			`// Instantiation of ASIC memory:`
167			`//`
168			`// Virtual Silicon Single-Port Synchronous SRAM`
169			`//`
170			`ifdef UNUSED
171			`else
172			`ifdef OR1200_BIST
173			`else
174			`endif
175			`endif
176			`ifdef OR1200_BIST
177			`// RAM BIST`
178			`endif
179
180			`else
181
182			`ifdef OR1200_XILINX_RAMB4
183
184			`//`
185			`// Instantiation of FPGA memory:`
186			`//`
187			`// Virtex/Spartan2`
188			`//`
189
190			`//`
191			`// Block 0`
192			`//`
193			`RAMB4_S16 ramb4_s16_0(`
194			`.CLK(clk),`
195			`.RST(rst),`
196			`.ADDR({1'b0, addr}),`
197			`.DI(di[15:0]),`
198			`.EN(ce),`
199			`.WE(we),`
200	1291	lampret	`.DO(doq[15:0])`
201	1273	simont	`);`
202
203			`//`
204			`// Block 1`
205			`//`
206			`RAMB4_S16 ramb4_s16_1(`
207			`.CLK(clk),`
208			`.RST(rst),`
209			`.ADDR({1'b0, addr}),`
210			`.DI(di[31:16]),`
211			`.EN(ce),`
212			`.WE(we),`
213	1291	lampret	`.DO(doq[31:16])`
214	1273	simont	`);`
215
216			`else
217
218	1582	jcastillo	`ifdef OR1200_XILINX_RAMB16
219	1273	simont
220			`//`
221			`// Instantiation of FPGA memory:`
222			`//`
223	1582	jcastillo	`// Virtex4/Spartan3E`
224	1273	simont	`//`
225	1582	jcastillo	`// Added By Nir Mor`
226	1273	simont	`//`
227
228	1582	jcastillo	`RAMB16_S36 ramb16_s36(`
229			`.CLK(clk),`
230			`.SSR(rst),`
231			`.ADDR({2'b00, addr}),`
232			`.DI(di),`
233			`.DIP(4'h0),`
234			`.EN(ce),`
235			`.WE(we),`
236			`.DO(doq),`
237			`.DOP()`
238			`);`
239	1273	simont
240			`else
241
242			`//`
243			`// Generic single-port synchronous RAM model`
244			`//`
245
246			`//`
247			`// Generic RAM's registers and wires`
248			`//`
249			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
250	1291	lampret	`reg [aw-1:0] addr_reg; // RAM address register`
251	1273	simont
252			`//`
253			`// Data output drivers`
254			`//`
255	1291	lampret	`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
256	1273	simont
257			`//`
258	1291	lampret	`// RAM address register`
259	1273	simont	`//`
260	1291	lampret	`always @(posedge clk or posedge rst)`
261			`if (rst)`
262			`addr_reg <= #1 {aw{1'b0}};`
263			`else if (ce)`
264			`addr_reg <= #1 addr;`
265
266			`//`
267			`// RAM write`
268			`//`
269	1273	simont	`always @(posedge clk)`
270	1291	lampret	`if (ce && we)`
271	1273	simont	`mem[addr] <= #1 di;`
272
273	1582	jcastillo	`endif // !OR1200_XILINX_RAMB16
274			`endif // !OR1200_XILINX_RAMB4
275	1273	simont	`endif // !OR1200_VIRTUALSILICON_SSP
276			`endif // !OR1200_VIRAGE_SSP
277	1582	jcastillo	`endif // !OR1200_AVANT_ATP
278	1273	simont	`endif // !OR1200_ARTISAN_SSP
279
280			`endmodule`

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Blame information for rev 1582