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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/08/11 13:32:19  simons
// BIST interface added for Artisan memory instances.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_256x21(
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 21;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   scanb_rst,
                        scanb_si,
                        scanb_en,
                        scanb_clk;
output                  scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
wire    [10:0]           unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_256x21_bist artisan_ssp(
`else
art_hssp_256x21 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_256x21_bist vs_ssp(
`else
vs_hdsp_256x21 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(do[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({11'b00000000000, di[20:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, do[20:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(do)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26	1129	lampret	`//// - Altera LPM ////`
27	504	lampret	`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31	1129	lampret	`//// - add additional RAMs ////`
32	504	lampret	`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1184	simons	`// Revision 1.4 2003/08/11 13:32:19 simons`
67			`// BIST interface added for Artisan memory instances.`
68			`//`
69	1179	simons	`// Revision 1.3 2003/04/07 01:19:07 lampret`
70			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
71			`//`
72	1129	lampret	`// Revision 1.2 2002/10/17 20:04:40 lampret`
73			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
74			`//`
75	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
76			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
77			`//`
78	504	lampret	`// Revision 1.10 2001/11/27 21:24:04 lampret`
79			`// Changed instantiation name of VS RAMs.`
80			`//`
81			`// Revision 1.9 2001/11/27 19:45:04 lampret`
82			`// Fixed VS RAM instantiation - again.`
83			`//`
84			`// Revision 1.8 2001/11/23 21:42:31 simons`
85			`// Program counter divided to PPC and NPC.`
86			`//`
87			`// Revision 1.6 2001/10/21 17:57:16 lampret`
88			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
89			`//`
90			`// Revision 1.5 2001/10/14 13:12:09 lampret`
91			`// MP3 version.`
92			`//`
93			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
94			`// no message`
95			`//`
96			`// Revision 1.1 2001/08/09 13:39:33 lampret`
97			`// Major clean-up.`
98			`//`
99			`// Revision 1.2 2001/07/30 05:38:02 lampret`
100			`// Adding empty directories required by HDL coding guidelines`
101			`//`
102			`//`
103
104			`// synopsys translate_off`
105			`include "timescale.v"
106			`// synopsys translate_on`
107			`include "or1200_defines.v"
108
109			`module or1200_spram_256x21(`
110	1063	lampret	`ifdef OR1200_BIST
111			`// RAM BIST`
112			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
113			`endif
114	504	lampret	`// Generic synchronous single-port RAM interface`
115			`clk, rst, ce, we, oe, addr, di, do`
116			`);`
117
118			`//`
119			`// Default address and data buses width`
120			`//`
121			`parameter aw = 8;`
122			`parameter dw = 21;`
123
124	1063	lampret	`ifdef OR1200_BIST
125	504	lampret	`//`
126	1063	lampret	`// RAM BIST`
127			`//`
128			`input scanb_rst,`
129			`scanb_si,`
130			`scanb_en,`
131			`scanb_clk;`
132			`output scanb_so;`
133			`endif
134
135			`//`
136	504	lampret	`// Generic synchronous single-port RAM interface`
137			`//`
138			`input clk; // Clock`
139			`input rst; // Reset`
140			`input ce; // Chip enable input`
141			`input we; // Write enable input`
142			`input oe; // Output enable input`
143			`input [aw-1:0] addr; // address bus inputs`
144			`input [dw-1:0] di; // input data bus`
145			`output [dw-1:0] do; // output data bus`
146
147			`//`
148			`// Internal wires and registers`
149			`//`
150			`wire [10:0] unconnected;`
151
152	1184	simons	`ifdef OR1200_ARTISAN_SSP
153			`else
154			`ifdef OR1200_VIRTUALSILICON_SSP
155			`else
156	1063	lampret	`ifdef OR1200_BIST
157			`assign scanb_so = scanb_si;`
158			`endif
159	1184	simons	`endif
160			`endif
161	1063	lampret
162	1184	simons
163	504	lampret	`ifdef OR1200_ARTISAN_SSP
164
165			`//`
166			`// Instantiation of ASIC memory:`
167			`//`
168			`// Artisan Synchronous Single-Port RAM (ra1sh)`
169			`//`
170			`ifdef UNUSED
171			`art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(`
172			`else
173	1179	simons	`ifdef OR1200_BIST
174			`art_hssp_256x21_bist artisan_ssp(`
175			`else
176	504	lampret	`art_hssp_256x21 artisan_ssp(`
177			`endif
178	1179	simons	`endif
179			`ifdef OR1200_BIST
180			`// RAM BIST`
181			`.scanb_rst(scanb_rst),`
182			`.scanb_si(scanb_si),`
183			`.scanb_so(scanb_so),`
184			`.scanb_en(scanb_en),`
185			`.scanb_clk(scanb_clk),`
186			`endif
187			`.CLK(clk),`
188			`.CEN(~ce),`
189			`.WEN(~we),`
190			`.A(addr),`
191			`.D(di),`
192			`.OEN(~oe),`
193			`.Q(do)`
194	504	lampret	`);`
195
196			`else
197
198			`ifdef OR1200_AVANT_ATP
199
200			`//`
201			`// Instantiation of ASIC memory:`
202			`//`
203			`// Avant! Asynchronous Two-Port RAM`
204			`//`
205			`avant_atp avant_atp(`
206			`.web(~we),`
207			`.reb(),`
208			`.oeb(~oe),`
209			`.rcsb(),`
210			`.wcsb(),`
211			`.ra(addr),`
212			`.wa(addr),`
213			`.di(di),`
214			`.do(do)`
215			`);`
216
217			`else
218
219			`ifdef OR1200_VIRAGE_SSP
220
221			`//`
222			`// Instantiation of ASIC memory:`
223			`//`
224			`// Virage Synchronous 1-port R/W RAM`
225			`//`
226			`virage_ssp virage_ssp(`
227			`.clk(clk),`
228			`.adr(addr),`
229			`.d(di),`
230			`.we(we),`
231			`.oe(oe),`
232			`.me(ce),`
233			`.q(do)`
234			`);`
235
236			`else
237
238			`ifdef OR1200_VIRTUALSILICON_SSP
239
240			`//`
241			`// Instantiation of ASIC memory:`
242			`//`
243			`// Virtual Silicon Single-Port Synchronous SRAM`
244			`//`
245			`ifdef UNUSED
246			`vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(`
247			`else
248	1063	lampret	`ifdef OR1200_BIST
249			`vs_hdsp_256x21_bist vs_ssp(`
250			`else
251	504	lampret	`vs_hdsp_256x21 vs_ssp(`
252			`endif
253	1063	lampret	`endif
254			`ifdef OR1200_BIST
255			`// RAM BIST`
256			`.scanb_rst(scanb_rst),`
257			`.scanb_si(scanb_si),`
258			`.scanb_so(scanb_so),`
259			`.scanb_en(scanb_en),`
260			`.scanb_clk(scanb_clk),`
261			`endif
262	504	lampret	`.CK(clk),`
263			`.ADR(addr),`
264			`.DI(di),`
265			`.WEN(~we),`
266			`.CEN(~ce),`
267			`.OEN(~oe),`
268			`.DOUT(do)`
269			`);`
270
271			`else
272
273			`ifdef OR1200_XILINX_RAMB4
274
275			`//`
276			`// Instantiation of FPGA memory:`
277			`//`
278			`// Virtex/Spartan2`
279			`//`
280
281			`//`
282			`// Block 0`
283			`//`
284			`RAMB4_S16 ramb4_s16_0(`
285			`.CLK(clk),`
286			`.RST(rst),`
287			`.ADDR(addr),`
288			`.DI(di[15:0]),`
289			`.EN(ce),`
290			`.WE(we),`
291			`.DO(do[15:0])`
292			`);`
293
294			`//`
295			`// Block 1`
296			`//`
297			`RAMB4_S16 ramb4_s16_1(`
298			`.CLK(clk),`
299			`.RST(rst),`
300			`.ADDR(addr),`
301			`.DI({11'b00000000000, di[20:16]}),`
302			`.EN(ce),`
303			`.WE(we),`
304			`.DO({unconnected, do[20:16]})`
305			`);`
306
307			`else
308
309	1129	lampret	`ifdef OR1200_ALTERA_LPM
310
311	504	lampret	`//`
312	1129	lampret	`// Instantiation of FPGA memory:`
313			`//`
314			`// Altera LPM`
315			`//`
316			`// Added By Jamil Khatib`
317			`//`
318
319			`wire wr;`
320
321			`assign wr = ce & we;`
322
323			`initial $display("Using Altera LPM.");`
324
325			`lpm_ram_dq lpm_ram_dq_component (`
326			`.address(addr),`
327			`.inclock(clk),`
328			`.outclock(clk),`
329			`.data(di),`
330			`.we(wr),`
331			`.q(do)`
332			`);`
333
334			`defparam lpm_ram_dq_component.lpm_width = dw,`
335			`lpm_ram_dq_component.lpm_widthad = aw,`
336			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
337			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
338			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
339			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
340			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
341
342			`else
343
344			`//`
345	504	lampret	`// Generic single-port synchronous RAM model`
346			`//`
347
348			`//`
349			`// Generic RAM's registers and wires`
350			`//`
351			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
352			`reg [dw-1:0] do_reg; // RAM data output register`
353
354			`//`
355			`// Data output drivers`
356			`//`
357	1129	lampret	`assign do = (oe) ? do_reg : {dw{1'b0}};`
358	504	lampret
359			`//`
360			`// RAM read and write`
361			`//`
362			`always @(posedge clk)`
363			`if (ce && !we)`
364			`do_reg <= #1 mem[addr];`
365			`else if (ce && we)`
366			`mem[addr] <= #1 di;`
367
368	1129	lampret	`endif // !OR1200_ALTERA_LPM
369	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16
370			`endif // !OR1200_VIRTUALSILICON_SSP
371			`endif // !OR1200_VIRAGE_SSP
372			`endif // !OR1200_AVANT_ATP
373			`endif // !OR1200_ARTISAN_SSP
374
375			`endmodule`

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