URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1765

Details | Compare with Previous | View Log


/* abstract.c -- Abstract entities
 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
   Copyright (C) 2008 Embecosm Limited
 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */
 
/* Abstract memory and routines that go with this. I need to add all sorts of
   other abstract entities. Currently we have only memory. */
 
 
/* Autoconf and/or portability configuration */
#include "config.h"
#include "port.h"
 
/* System includes */
#include <stdlib.h>
 
/* Package includes */
#include "abstract.h"
#include "except.h"
#include "support/profile.h"
#include "debug-unit.h"
#include "icache-model.h"
#include "dcache-model.h"
#include "labels.h"
#include "opcode/or32.h"
#include "dmmu.h"
#include "immu.h"
 
#if DYNAMIC_EXECUTION
#include "dyn-rec.h"
#endif
 
 
/*! Global temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Glboal variables set by MMU if cache inhibit bit is set for current
   access.  */
int  data_ci;                   /*!< Global var: data cache inhibit bit set */
int  insn_ci;                   /*!< Global var: instr cache inhibit bit set */
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
static struct dev_memarea *dev_list;
 
/* Pointer to memory controller device descriptor.  */
static struct dev_memarea *mc_area = NULL;
 
/* Virtual address of current access. */
static oraddr_t cur_vadd;
 
/* Forward declarations */
static uint32_t eval_mem_32_inv (oraddr_t, void *);
static uint16_t eval_mem_16_inv (oraddr_t, void *);
static uint8_t  eval_mem_8_inv (oraddr_t, void *);
static uint32_t eval_mem_32_inv_direct (oraddr_t, void *);
static uint16_t eval_mem_16_inv_direct (oraddr_t, void *);
static uint8_t  eval_mem_8_inv_direct (oraddr_t, void *);
static void     set_mem_32_inv (oraddr_t, uint32_t, void *);
static void     set_mem_16_inv (oraddr_t, uint16_t, void *);
static void     set_mem_8_inv (oraddr_t, uint8_t, void *);
static void     set_mem_32_inv_direct (oraddr_t, uint32_t, void *);
static void     set_mem_16_inv_direct (oraddr_t, uint16_t, void *);
static void     set_mem_8_inv_direct (oraddr_t, uint8_t, void *);
 
/* Calculates bit mask to fit the data */
static unsigned int
bit_mask (uint32_t data)
{
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
static struct dev_memarea *
register_memoryarea_mask (oraddr_t addr_mask,
                          oraddr_t addr_compare,
                          uint32_t size, unsigned mc_dev)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  /* Go to the end of the list. */
  for (pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if (((addr_compare >= (*pptmp)->addr_compare) &&
         (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) ||
        ((addr_compare + size > (*pptmp)->addr_compare) &&
         (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)))
      {
        if (!found_error)
          {
            fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
            fprintf (stderr,
                     "\taddr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR
                     ", size %08" PRIx32 "\n", addr_mask, addr_compare,
                     addr_compare | bit_mask (size), size);
          }
        found_error = 1;
        fprintf (stderr,
                 "and\taddr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR
                 ", size %08" PRIx32 "\n", (*pptmp)->addr_mask,
                 (*pptmp)->addr_compare,
                 (*pptmp)->addr_compare | (*pptmp)->size_mask,
                 (*pptmp)->size);
      }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp =
    (struct dev_memarea *) malloc (sizeof (struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->log = NULL;
  (*pptmp)->valid = 1;
  (*pptmp)->next = NULL;
 
  return *pptmp;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this device will be checked first for a match
   and will be accessed in case of overlaping memory areas.
   Only one device can have this set to 1 (used for memory controller) */
struct dev_memarea *
reg_mem_area (oraddr_t addr, uint32_t size, unsigned mc_dev,
              struct mem_ops *ops)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  struct dev_memarea *mem;
 
  mem = register_memoryarea_mask (addr_mask, addr & addr_mask, size_mask + 1,
                                  mc_dev);
 
  memcpy (&mem->ops, ops, sizeof (struct mem_ops));
  memcpy (&mem->direct_ops, ops, sizeof (struct mem_ops));
 
  if (!ops->readfunc32)
    {
      mem->ops.readfunc32 = eval_mem_32_inv;
      mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
      mem->direct_ops.read_dat32 = mem;
    }
  if (!ops->readfunc16)
    {
      mem->ops.readfunc16 = eval_mem_16_inv;
      mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
      mem->direct_ops.read_dat16 = mem;
    }
  if (!ops->readfunc8)
    {
      mem->ops.readfunc8 = eval_mem_8_inv;
      mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
      mem->direct_ops.read_dat8 = mem;
    }
 
  if (!ops->writefunc32)
    {
      mem->ops.writefunc32 = set_mem_32_inv;
      mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
      mem->direct_ops.write_dat32 = mem;
    }
  if (!ops->writefunc16)
    {
      mem->ops.writefunc16 = set_mem_16_inv;
      mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
      mem->direct_ops.write_dat16 = mem;
    }
  if (!ops->writefunc8)
    {
      mem->ops.writefunc8 = set_mem_8_inv;
      mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
      mem->direct_ops.write_dat8 = mem;
    }
 
  if (!ops->writeprog8)
    {
      mem->ops.writeprog8 = mem->ops.writefunc8;
      mem->ops.writeprog8_dat = mem->ops.write_dat8;
    }
 
  if (!ops->writeprog32)
    {
      mem->ops.writeprog32 = mem->ops.writefunc32;
      mem->ops.writeprog32_dat = mem->ops.write_dat32;
    }
 
  if (ops->log)
    {
      if (!(mem->log = fopen (ops->log, "w")))
        PRINTF ("ERR: Unable to open %s to log memory acesses to\n",
                ops->log);
    }
 
  return mem;
}
 
/* Check if access is to registered area of memory. */
struct dev_memarea *
verify_memoryarea (oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area
      && (addr & mc_area->addr_mask) ==
      (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area
      && (addr & cur_area->addr_mask) ==
      (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is
     nonzero */
  /* Check list of registered devices. */
  for (ptmp = dev_list; ptmp; ptmp = ptmp->next)
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask)
        && ptmp->valid)
      return cur_area = ptmp;
  return cur_area = NULL;
}
 
/* Sets the valid bit (Used only by memory controllers) */
void
set_mem_valid (struct dev_memarea *mem, int valid)
{
  mem->valid = valid;
}
 
/* Adjusts the read and write delays for the memory area pointed to by mem. */
void
adjust_rw_delay (struct dev_memarea *mem, int delayr, int delayw)
{
  mem->ops.delayr = delayr;
  mem->ops.delayw = delayw;
}
 
static uint8_t
eval_mem_8_inv (oraddr_t memaddr, void *dat)
{
  except_handle (EXCEPT_BUSERR, cur_vadd);
  return 0;
}
 
static uint16_t
eval_mem_16_inv (oraddr_t memaddr, void *dat)
{
  except_handle (EXCEPT_BUSERR, cur_vadd);
  return 0;
}
 
static uint32_t
eval_mem_32_inv (oraddr_t memaddr, void *dat)
{
  except_handle (EXCEPT_BUSERR, cur_vadd);
  return 0;
}
 
static void
set_mem_8_inv (oraddr_t memaddr, uint8_t val, void *dat)
{
  except_handle (EXCEPT_BUSERR, cur_vadd);
}
 
static void
set_mem_16_inv (oraddr_t memaddr, uint16_t val, void *dat)
{
  except_handle (EXCEPT_BUSERR, cur_vadd);
}
 
static void
set_mem_32_inv (oraddr_t memaddr, uint32_t val, void *dat)
{
  except_handle (EXCEPT_BUSERR, cur_vadd);
}
 
uint8_t
eval_mem_8_inv_direct (oraddr_t memaddr, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF ("ERROR: Invalid 8-bit direct read from memory %" PRIxADDR "\n",
          mem->addr_compare | memaddr);
  return 0;
}
 
uint16_t
eval_mem_16_inv_direct (oraddr_t memaddr, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF ("ERROR: Invalid 16-bit direct read from memory %" PRIxADDR "\n",
          mem->addr_compare | memaddr);
  return 0;
}
 
uint32_t
eval_mem_32_inv_direct (oraddr_t memaddr, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF ("ERROR: Invalid 32-bit direct read from memory %" PRIxADDR "\n",
          mem->addr_compare | memaddr);
  return 0;
}
 
void
set_mem_8_inv_direct (oraddr_t memaddr, uint8_t val, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF ("ERROR: Invalid 32-bit direct write to memory %" PRIxADDR "\n",
          mem->addr_compare | memaddr);
}
 
void
set_mem_16_inv_direct (oraddr_t memaddr, uint16_t val, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF ("ERROR: Invalid 16-bit direct write to memory %" PRIxADDR "\n",
          mem->addr_compare | memaddr);
}
 
void
set_mem_32_inv_direct (oraddr_t memaddr, uint32_t val, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF ("ERROR: Invalid 32-bit direct write to memory %" PRIxADDR "\n",
          mem->addr_compare | memaddr);
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from eval_mem32 below and
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
 */
uint32_t
evalsim_mem32 (oraddr_t memaddr, oraddr_t vaddr)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      runtime.sim.mem_cycles += mem->ops.delayr;
      return mem->ops.readfunc32 (memaddr & mem->size_mask,
                                  mem->ops.read_dat32);
    }
  else
    {
      PRINTF ("EXCEPTION: read out of memory (32-bit access to %" PRIxADDR
              ")\n", memaddr);
      except_handle (EXCEPT_BUSERR, vaddr);
    }
 
  return 0;
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from eval_mem16 below and
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
 */
uint16_t
evalsim_mem16 (oraddr_t memaddr, oraddr_t vaddr)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      runtime.sim.mem_cycles += mem->ops.delayr;
      return mem->ops.readfunc16 (memaddr & mem->size_mask,
                                  mem->ops.read_dat16);
    }
  else
    {
      PRINTF ("EXCEPTION: read out of memory (16-bit access to %" PRIxADDR
              ")\n", memaddr);
      except_handle (EXCEPT_BUSERR, vaddr);
    }
 
  return 0;
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from eval_mem8 below and
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
 */
uint8_t
evalsim_mem8 (oraddr_t memaddr, oraddr_t vaddr)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      runtime.sim.mem_cycles += mem->ops.delayr;
      return mem->ops.readfunc8 (memaddr & mem->size_mask,
                                 mem->ops.read_dat8);
    }
  else
    {
      PRINTF ("EXCEPTION: read out of memory (8-bit access to %" PRIxADDR
              ")\n", memaddr);
      except_handle (EXCEPT_BUSERR, vaddr);
    }
 
  return 0;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t
eval_mem32 (oraddr_t memaddr, int *breakpoint)
{
  uint32_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3)
    {
      except_handle (EXCEPT_ALIGN, memaddr);
      return 0;
    }
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);        /* 28/05/01 CZ */
 
  phys_memaddr = dmmu_translate (memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read (phys_memaddr, memaddr, 4);
  else
    temp = evalsim_mem32 (phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);      /* MM170901 */
 
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t
eval_direct32 (oraddr_t memaddr, int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 3)
    {
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
              __FUNCTION__);
      return 0;
    }
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
 
  if (through_dc)
    return dc_simulate_read (phys_memaddr, memaddr, 4);
  else
    {
      if ((mem = verify_memoryarea (phys_memaddr)))
        return mem->direct_ops.readfunc32 (phys_memaddr & mem->size_mask,
                                           mem->direct_ops.read_dat32);
      else
        PRINTF ("ERR: 32-bit read out of memory area: %" PRIxADDR
                " (physical: %" PRIxADDR ")\n", memaddr, phys_memaddr);
    }
 
  return 0;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t
eval_insn (oraddr_t memaddr, int *breakpoint)
{
  uint32_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
 
  phys_memaddr = memaddr;
#if !(DYNAMIC_EXECUTION)
  phys_memaddr = immu_translate (memaddr);
 
  if (except_pending)
    return 0;
#endif
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
 
  if ((NULL != ic_state) && ic_state->enabled)
    temp = ic_simulate_fetch (phys_memaddr, memaddr);
  else
    temp = evalsim_mem32 (phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t
eval_mem16 (oraddr_t memaddr, int *breakpoint)
{
  uint16_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1)
    {
      except_handle (EXCEPT_ALIGN, memaddr);
      return 0;
    }
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);        /* 28/05/01 CZ */
 
  phys_memaddr = dmmu_translate (memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read (phys_memaddr, memaddr, 2);
  else
    temp = evalsim_mem16 (phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);      /* MM170901 */
 
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t
eval_direct16 (oraddr_t memaddr, int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 1)
    {
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
              __FUNCTION__);
      return 0;
    }
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
 
  if (through_dc)
    return dc_simulate_read (phys_memaddr, memaddr, 2);
  else
    {
      if ((mem = verify_memoryarea (phys_memaddr)))
        return mem->direct_ops.readfunc16 (phys_memaddr & mem->size_mask,
                                           mem->direct_ops.read_dat16);
      else
        PRINTF ("ERR: 16-bit read out of memory area: %" PRIxADDR
                " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
    }
 
  return 0;
}
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t
eval_mem8 (oraddr_t memaddr, int *breakpoint)
{
  uint8_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);        /* 28/05/01 CZ */
 
  phys_memaddr = dmmu_translate (memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read (phys_memaddr, memaddr, 1);
  else
    temp = evalsim_mem8 (phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);      /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t
eval_direct8 (oraddr_t memaddr, int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
 
  if (through_dc)
    return dc_simulate_read (phys_memaddr, memaddr, 1);
  else
    {
      if ((mem = verify_memoryarea (phys_memaddr)))
        return mem->direct_ops.readfunc8 (phys_memaddr & mem->size_mask,
                                          mem->direct_ops.read_dat8);
      else
        PRINTF ("ERR: 8-bit read out of memory area: %" PRIxADDR
                " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
    }
 
  return 0;
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from set_mem32 below and
 * dc_simulate_write.  _Don't_ call it from anywere else.
 */
void
setsim_mem32 (oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      cur_vadd = vaddr;
      runtime.sim.mem_cycles += mem->ops.delayw;
      mem->ops.writefunc32 (memaddr & mem->size_mask, value,
                            mem->ops.write_dat32);
#if DYNAMIC_EXECUTION
      dyn_checkwrite (memaddr);
#endif
    }
  else
    {
      PRINTF ("EXCEPTION: write out of memory (32-bit access to %" PRIxADDR
              ")\n", memaddr);
      except_handle (EXCEPT_BUSERR, vaddr);
    }
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from set_mem16 below and
 * dc_simulate_write.  _Don't_ call it from anywere else.
 */
void
setsim_mem16 (oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      cur_vadd = vaddr;
      runtime.sim.mem_cycles += mem->ops.delayw;
      mem->ops.writefunc16 (memaddr & mem->size_mask, value,
                            mem->ops.write_dat16);
#if DYNAMIC_EXECUTION
      dyn_checkwrite (memaddr);
#endif
    }
  else
    {
      PRINTF ("EXCEPTION: write out of memory (16-bit access to %" PRIxADDR
              ")\n", memaddr);
      except_handle (EXCEPT_BUSERR, vaddr);
    }
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from set_mem8 below and
 * dc_simulate_write.  _Don't_ call it from anywere else.
 */
void
setsim_mem8 (oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      cur_vadd = vaddr;
      runtime.sim.mem_cycles += mem->ops.delayw;
      mem->ops.writefunc8 (memaddr & mem->size_mask, value,
                           mem->ops.write_dat8);
#if DYNAMIC_EXECUTION
      dyn_checkwrite (memaddr);
#endif
    }
  else
    {
      PRINTF ("EXCEPTION: write out of memory (8-bit access to %" PRIxADDR
              ")\n", memaddr);
      except_handle (EXCEPT_BUSERR, vaddr);
    }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void
set_mem32 (oraddr_t memaddr, uint32_t value, int *breakpoint)
{
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3)
    {
      except_handle (EXCEPT_ALIGN, memaddr);
      return;
    }
 
  phys_memaddr = dmmu_translate (memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled)
    {
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreData, value);
    }
 
  if (config.dc.enabled)
    dc_simulate_write (phys_memaddr, memaddr, value, 4);
  else
    setsim_mem32 (phys_memaddr, memaddr, value);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%" PRIxADDR "] -> write %08" PRIx32 "\n",
             memaddr, value);
}
 
/*
 * STATISTICS NOT OK.
 */
void
set_direct32 (oraddr_t memaddr, uint32_t value, int through_mmu,
              int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 3)
    {
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
              __FUNCTION__);
      return;
    }
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    {
      /* 0 - no write access, we do not want a DPF exception do we ;)
       */
      phys_memaddr = peek_into_dtlb (memaddr, 1, through_dc);
    }
 
  if (through_dc)
    dc_simulate_write (memaddr, memaddr, value, 4);
  else
    {
      if ((mem = verify_memoryarea (phys_memaddr)))
        mem->direct_ops.writefunc32 (phys_memaddr & mem->size_mask, value,
                                     mem->direct_ops.write_dat32);
      else
        PRINTF ("ERR: 32-bit write out of memory area: %" PRIxADDR
                " (physical: %" PRIxADDR ")\n", memaddr, phys_memaddr);
    }
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%" PRIxADDR "] -> DIRECT write %08" PRIx32 "\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void
set_mem16 (oraddr_t memaddr, uint16_t value, int *breakpoint)
{
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1)
    {
      except_handle (EXCEPT_ALIGN, memaddr);
      return;
    }
 
  phys_memaddr = dmmu_translate (memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled)
    {
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreData, value);
    }
 
  if (config.dc.enabled)
    dc_simulate_write (phys_memaddr, memaddr, value, 2);
  else
    setsim_mem16 (phys_memaddr, memaddr, value);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%" PRIxADDR "] -> write %04" PRIx16 "\n",
             memaddr, value);
}
 
/*
 * STATISTICS NOT OK.
 */
void
set_direct16 (oraddr_t memaddr, uint16_t value, int through_mmu,
              int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 1)
    {
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
              __FUNCTION__);
      return;
    }
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    {
      /* 0 - no write access, we do not want a DPF exception do we ;)
       */
      phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
    }
 
  if (through_dc)
    dc_simulate_write (memaddr, memaddr, value, 2);
  else
    {
      if ((mem = verify_memoryarea (phys_memaddr)))
        mem->direct_ops.writefunc16 (phys_memaddr & mem->size_mask, value,
                                     mem->direct_ops.write_dat16);
      else
        PRINTF ("ERR: 16-bit write out of memory area: %" PRIxADDR
                " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
    }
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%" PRIxADDR "] -> DIRECT write %04" PRIx16 "\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
void
set_mem8 (oraddr_t memaddr, uint8_t value, int *breakpoint)
{
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  phys_memaddr = memaddr;
 
  phys_memaddr = dmmu_translate (memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled)
    {
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreData, value);
    }
 
  if (config.dc.enabled)
    dc_simulate_write (phys_memaddr, memaddr, value, 1);
  else
    setsim_mem8 (phys_memaddr, memaddr, value);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%" PRIxADDR "] -> write %02" PRIx8 "\n",
             memaddr, value);
}
 
/*
 * STATISTICS NOT OK.
 */
void
set_direct8 (oraddr_t memaddr, uint8_t value, int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    {
      /* 0 - no write access, we do not want a DPF exception do we ;)
       */
      phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
    }
 
  if (through_dc)
    dc_simulate_write (phys_memaddr, memaddr, value, 1);
  else
    {
      if ((mem = verify_memoryarea (phys_memaddr)))
        mem->direct_ops.writefunc8 (phys_memaddr & mem->size_mask, value,
                                    mem->direct_ops.write_dat8);
      else
        PRINTF ("ERR: 8-bit write out of memory area: %" PRIxADDR
                " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
    }
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%" PRIxADDR "] -> DIRECT write %02" PRIx8 "\n",
             memaddr, value);
}
 
 
/* set_program32 - same as set_direct32, but it also writes to memory that is
 *                 non-writeable to the rest of the sim.  Used to do program
 *                 loading.
 */
void
set_program32 (oraddr_t memaddr, uint32_t value)
{
  struct dev_memarea *mem;
 
  if (memaddr & 3)
    {
      PRINTF ("%s(): ERR unaligned 32-bit program write\n", __FUNCTION__);
      return;
    }
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      mem->ops.writeprog32 (memaddr & mem->size_mask, value,
                            mem->ops.writeprog32_dat);
    }
  else
    PRINTF ("ERR: 32-bit program load out of memory area: %" PRIxADDR "\n",
            memaddr);
}
 
/* set_program8 - same as set_direct8, but it also writes to memory that is
 *                non-writeable to the rest of the sim.  Used to do program
 *                loading.
 */
void
set_program8 (oraddr_t memaddr, uint8_t value)
{
  struct dev_memarea *mem;
 
  if ((mem = verify_memoryarea (memaddr)))
    {
      mem->ops.writeprog8 (memaddr & mem->size_mask, value,
                           mem->ops.writeprog8_dat);
    }
  else
    PRINTF ("ERR: 8-bit program load out of memory area: %" PRIxADDR "\n",
            memaddr);
}
 
 
/*---------------------------------------------------------------------------*/
/*!Dump memory to the current output
 
   Output format is hex bytes, 16 bytes per line. Start each line with its
   address and (optionally) its symbolic name. Always end with a newline.
 
   There are all sorts of ways to trip this up, but they are unlikely. The
   validity of a memory area is taken from the address of the start of a line
   to be printed, so assumes the following 15 bytes are present. This could be
   fooled by ridiculous memory declarations.
 
   @param[in] from    Start address of the area of memory
   @param[in] to      End address of the area of memory                      */
/*---------------------------------------------------------------------------*/
void
dump_memory (oraddr_t from, oraddr_t to)
{
  const int ROW_LEN = 16;
  oraddr_t i;                   /* Row counter */
 
  for (i = from; i < to; i += ROW_LEN)
    {
      struct label_entry *entry = get_label (i);
      oraddr_t j;               /* Index in row */
 
      PRINTF ("%" PRIxADDR, i);
 
      if (NULL != entry)
        {
          int padding = 11 - strlen (entry->name);
 
          PRINTF (" <%s>: ", entry->name);
          PRINTF ("%*s ", padding < 0 ? 0 : padding, " ");
        }
      else
        {
          PRINTF (":                ");
        }
 
 
      for (j = 0; j < ROW_LEN; j++)
        {
          if (verify_memoryarea (i + j))
            {
              PRINTF ("%02" PRIx8 " ", eval_direct8 (i + j, 0, 0));
            }
          else
            {
              /* Not a valid memory area. Print Xs as required */
              PRINTF ("XX ");
            }
        }
 
      PRINTF ("\n");
    }
}                               /* dump_memory() */
 
 
/*---------------------------------------------------------------------------*/
/*!Disassemble memory to the current output
 
   Output format is symbolic disassembly, one instruction per line. Start each
   line with its address and (optionally) its symbolic name.
 
   There are all sorts of ways to trip this up, but they are unlikely. The
   validity of a memory area is taken from the address of the start of a line
   to be printed, so assumes the following 3 bytes are present. This could be
   fooled by ridiculous memory declarations.
 
   @param[in] from    Start address of the area of memory
   @param[in] to      End address of the area of memory
   @param[in] nl      If non-zero (true) print a newline at the end of each
                      line                                                   */
/*---------------------------------------------------------------------------*/
void
disassemble_memory (oraddr_t from, oraddr_t to, int nl)
{
  const int INSTR_LEN = 4;
  oraddr_t i;                   /* Row counter */
 
  for (i = from; i < to; i += INSTR_LEN)
    {
      struct label_entry *entry = get_label (i);
 
      PRINTF ("%" PRIxADDR, i);
 
      if (NULL != entry)
        {
          int padding = 11 - strlen (entry->name);
 
          PRINTF (" <%s>: ", entry->name);
          PRINTF ("%*s ", padding < 0 ? 0 : padding, " ");
        }
      else
        {
          PRINTF (":                ");
        }
 
      if (verify_memoryarea (i))
        {
          uint32_t insn = eval_direct32 (i, 0, 0);
          int index = insn_decode (insn);
 
          PRINTF ("%08" PRIx32 " ", insn);
 
          if (index >= 0)
            {
              disassemble_insn (insn);
              PRINTF (" %s", disassembled);
            }
          else
            {
              PRINTF ("<invalid>");
            }
 
        }
      else
        {
          /* Not a valid memory area. Print Xs as required */
          PRINTF ("XXXXXXXX");
        }
 
      if (nl)
        {
          PRINTF ("\n");
        }
    }
}                               /* disassemble_memory() */
 
 
/* Closes files, etc. */
 
void
done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for (ptmp = dev_list; ptmp; ptmp = ptmp->next)
    {
      if (ptmp->log)
        fclose (ptmp->log);
    }
}
 
/* Displays current memory configuration */
 
void
memory_table_status (void)
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for (ptmp = dev_list; ptmp; ptmp = ptmp->next)
    {
      PRINTF ("addr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR ", size %"
              PRIx32 "\n", ptmp->addr_mask, ptmp->addr_compare,
              ptmp->addr_compare | bit_mask (ptmp->size), ptmp->size);
      PRINTF ("\t");
      if (ptmp->ops.delayr >= 0)
        PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
      else
        PRINTF ("reads not possible, ");
 
      if (ptmp->ops.delayw >= 0)
        PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
      else
        PRINTF ("writes not possible");
 
      if (ptmp->log)
        PRINTF (", (logged)\n");
      else
        PRINTF ("\n");
    }
}
 
/* Outputs time in pretty form to dest string */
 
char *
generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps)
    {
      while ((time_ps % 1000) == 0)
        {
          time_ps /= 1000;
          exp3++;
        }
    }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2	1743	jeremybenn
3	2	cvs	`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
4	1486	nogj	Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
5	1743	jeremybenn	`Copyright (C) 2008 Embecosm Limited`
6
7			`Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see <http://www.gnu.org/licenses/>. */`
23	2	cvs
24	1748	jeremybenn	`/* This program is commented throughout in a fashion suitable for processing`
25			`with Doxygen. */`
26
27	1743	jeremybenn	`/* Abstract memory and routines that go with this. I need to add all sorts of`
28			`other abstract entities. Currently we have only memory. */`
29	2	cvs
30
31	1748	jeremybenn	`/* Autoconf and/or portability configuration */`
32	6	lampret	`#include "config.h"`
33	1748	jeremybenn	`#include "port.h"`
34	1350	nogj
35	1748	jeremybenn	`/* System includes */`
36			`#include <stdlib.h>`
37	1350	nogj
38	1748	jeremybenn	`/* Package includes */`
39	2	cvs	`#include "abstract.h"`
40	1748	jeremybenn	`#include "except.h"`
41			`#include "support/profile.h"`
42			`#include "debug-unit.h"`
43			`#include "icache-model.h"`
44			`#include "dcache-model.h"`
45	261	markom	`#include "labels.h"`
46	134	markom	`#include "opcode/or32.h"`
47	1308	phoenix	`#include "dmmu.h"`
48	1446	nogj	`#include "immu.h"`
49	2	cvs
50	1452	nogj	`#if DYNAMIC_EXECUTION`
51	1751	jeremybenn	`#include "dyn-rec.h"`
52	1452	nogj	`#endif`
53
54	2	cvs
55	1748	jeremybenn	`/! Global temporary variable to increase speed. /`
56			`struct dev_memarea *cur_area;`
57
58			`/* Glboal variables set by MMU if cache inhibit bit is set for current`
59			`access. */`
60			`int data_ci; /!< Global var: data cache inhibit bit set /`
61			`int insn_ci; /!< Global var: instr cache inhibit bit set /`
62
63	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
64			`peripheral devices. */`
65	1748	jeremybenn	`static struct dev_memarea *dev_list;`
66	30	lampret
67	970	simons	`/* Pointer to memory controller device descriptor. */`
68	1748	jeremybenn	`static struct dev_memarea *mc_area = NULL;`
69	970	simons
70	525	simons	`/* Virtual address of current access. */`
71	1486	nogj	`static oraddr_t cur_vadd;`
72	525	simons
73	1748	jeremybenn	`/* Forward declarations */`
74			`static uint32_t eval_mem_32_inv (oraddr_t, void *);`
75			`static uint16_t eval_mem_16_inv (oraddr_t, void *);`
76			`static uint8_t eval_mem_8_inv (oraddr_t, void *);`
77			`static uint32_t eval_mem_32_inv_direct (oraddr_t, void *);`
78			`static uint16_t eval_mem_16_inv_direct (oraddr_t, void *);`
79			`static uint8_t eval_mem_8_inv_direct (oraddr_t, void *);`
80			`static void set_mem_32_inv (oraddr_t, uint32_t, void *);`
81			`static void set_mem_16_inv (oraddr_t, uint16_t, void *);`
82			`static void set_mem_8_inv (oraddr_t, uint8_t, void *);`
83			`static void set_mem_32_inv_direct (oraddr_t, uint32_t, void *);`
84			`static void set_mem_16_inv_direct (oraddr_t, uint16_t, void *);`
85			`static void set_mem_8_inv_direct (oraddr_t, uint8_t, void *);`
86	1486	nogj
87	261	markom	`/* Calculates bit mask to fit the data */`
88	1748	jeremybenn	`static unsigned int`
89			`bit_mask (uint32_t data)`
90			`{`
91	261	markom	`int i = 0;`
92			`data--;`
93	382	markom	`while (data >> i)`
94	261	markom	`data \|= 1 << i++;`
95			`return data;`
96			`}`
97
98			`/* Register read and write function for a memory area.`
99			`addr is inside the area, if addr & addr_mask == addr_compare`
100			`(used also by peripheral devices like 16450 UART etc.) */`
101	1748	jeremybenn	`static struct dev_memarea *`
102			`register_memoryarea_mask (oraddr_t addr_mask,`
103			`oraddr_t addr_compare,`
104			`uint32_t size, unsigned mc_dev)`
105	30	lampret	`{`
106	239	markom	`struct dev_memarea **pptmp;`
107	1350	nogj	`unsigned int size_mask = bit_mask (size);`
108	261	markom	`int found_error = 0;`
109			`addr_compare &= addr_mask;`
110	221	markom
111	239	markom	`/* Go to the end of the list. */`
112	1748	jeremybenn	`for (pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
113	1557	nogj	`if (((addr_compare >= (*pptmp)->addr_compare) &&`
114	1748	jeremybenn	`(addr_compare < (pptmp)->addr_compare + (pptmp)->size)) \|\|`
115			`((addr_compare + size > (*pptmp)->addr_compare) &&`
116			`(addr_compare < (pptmp)->addr_compare + (pptmp)->size)))`
117			`{`
118			`if (!found_error)`
119			`{`
120			`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
121			`fprintf (stderr,`
122			`"\taddr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR`
123			`", size %08" PRIx32 "\n", addr_mask, addr_compare,`
124			`addr_compare \| bit_mask (size), size);`
125			`}`
126			`found_error = 1;`
127			`fprintf (stderr,`
128			`"and\taddr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR`
129			`", size %08" PRIx32 "\n", (*pptmp)->addr_mask,`
130			`(*pptmp)->addr_compare,`
131			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
132			`(*pptmp)->size);`
133	262	markom	`}`
134	1748	jeremybenn
135	261	markom	`if (found_error)`
136			`exit (-1);`
137	537	markom
138	1748	jeremybenn	`cur_area = *pptmp =`
139			`(struct dev_memarea *) malloc (sizeof (struct dev_memarea));`
140	970	simons
141			`if (mc_dev)`
142			`mc_area = *pptmp;`
143
144	261	markom	`(*pptmp)->addr_mask = addr_mask;`
145			`(*pptmp)->addr_compare = addr_compare;`
146	239	markom	`(*pptmp)->size = size;`
147	261	markom	`(*pptmp)->size_mask = size_mask;`
148	1486	nogj	`(*pptmp)->log = NULL;`
149			`(*pptmp)->valid = 1;`
150	239	markom	`(*pptmp)->next = NULL;`
151	1486	nogj
152			`return *pptmp;`
153	261	markom	`}`
154	221	markom
155	261	markom	`/* Register read and write function for a memory area.`
156			`Memory areas should be aligned. Memory area is rounded up to`
157			`fit the nearest 2^n aligment.`
158	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
159	1486	nogj	`If mc_dev is 1, this device will be checked first for a match`
160			`and will be accessed in case of overlaping memory areas.`
161	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
162	1748	jeremybenn	`struct dev_memarea *`
163			`reg_mem_area (oraddr_t addr, uint32_t size, unsigned mc_dev,`
164			`struct mem_ops *ops)`
165	261	markom	`{`
166	1350	nogj	`unsigned int size_mask = bit_mask (size);`
167			`unsigned int addr_mask = ~size_mask;`
168	1486	nogj	`struct dev_memarea *mem;`
169
170	1748	jeremybenn	`mem = register_memoryarea_mask (addr_mask, addr & addr_mask, size_mask + 1,`
171			`mc_dev);`
172	1486	nogj
173	1748	jeremybenn	`memcpy (&mem->ops, ops, sizeof (struct mem_ops));`
174			`memcpy (&mem->direct_ops, ops, sizeof (struct mem_ops));`
175	1486	nogj
176	1748	jeremybenn	`if (!ops->readfunc32)`
177			`{`
178			`mem->ops.readfunc32 = eval_mem_32_inv;`
179			`mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;`
180			`mem->direct_ops.read_dat32 = mem;`
181			`}`
182			`if (!ops->readfunc16)`
183			`{`
184			`mem->ops.readfunc16 = eval_mem_16_inv;`
185			`mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;`
186			`mem->direct_ops.read_dat16 = mem;`
187			`}`
188			`if (!ops->readfunc8)`
189			`{`
190			`mem->ops.readfunc8 = eval_mem_8_inv;`
191			`mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;`
192			`mem->direct_ops.read_dat8 = mem;`
193			`}`
194	1486	nogj
195	1748	jeremybenn	`if (!ops->writefunc32)`
196			`{`
197			`mem->ops.writefunc32 = set_mem_32_inv;`
198			`mem->direct_ops.writefunc32 = set_mem_32_inv_direct;`
199			`mem->direct_ops.write_dat32 = mem;`
200			`}`
201			`if (!ops->writefunc16)`
202			`{`
203			`mem->ops.writefunc16 = set_mem_16_inv;`
204			`mem->direct_ops.writefunc16 = set_mem_16_inv_direct;`
205			`mem->direct_ops.write_dat16 = mem;`
206			`}`
207			`if (!ops->writefunc8)`
208			`{`
209			`mem->ops.writefunc8 = set_mem_8_inv;`
210			`mem->direct_ops.writefunc8 = set_mem_8_inv_direct;`
211			`mem->direct_ops.write_dat8 = mem;`
212			`}`
213	1486	nogj
214	1748	jeremybenn	`if (!ops->writeprog8)`
215			`{`
216			`mem->ops.writeprog8 = mem->ops.writefunc8;`
217			`mem->ops.writeprog8_dat = mem->ops.write_dat8;`
218			`}`
219	1486	nogj
220	1748	jeremybenn	`if (!ops->writeprog32)`
221			`{`
222			`mem->ops.writeprog32 = mem->ops.writefunc32;`
223			`mem->ops.writeprog32_dat = mem->ops.write_dat32;`
224			`}`
225	1556	nogj
226	1748	jeremybenn	`if (ops->log)`
227			`{`
228			`if (!(mem->log = fopen (ops->log, "w")))`
229			`PRINTF ("ERR: Unable to open %s to log memory acesses to\n",`
230			`ops->log);`
231			`}`
232	1486	nogj
233			`return mem;`
234	30	lampret	`}`
235
236			`/* Check if access is to registered area of memory. */`
237	1748	jeremybenn	`struct dev_memarea *`
238			`verify_memoryarea (oraddr_t addr)`
239	30	lampret	`{`
240	239	markom	`struct dev_memarea *ptmp;`
241	221	markom
242	970	simons	`/* Check memory controller space first */`
243	1748	jeremybenn	`if (mc_area`
244			`&& (addr & mc_area->addr_mask) ==`
245			`(mc_area->addr_compare & mc_area->addr_mask))`
246	970	simons	`return cur_area = mc_area;`
247
248			`/* Check cached value */`
249	1748	jeremybenn	`if (cur_area`
250			`&& (addr & cur_area->addr_mask) ==`
251			`(cur_area->addr_compare & cur_area->addr_mask))`
252	560	markom	`return cur_area;`
253
254	1748	jeremybenn	`/* When mc is enabled, we must check valid also, otherwise we assume it is`
255			`nonzero */`
256	1375	nogj	`/* Check list of registered devices. */`
257	1748	jeremybenn	`for (ptmp = dev_list; ptmp; ptmp = ptmp->next)`
258			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask)`
259			`&& ptmp->valid)`
260	1375	nogj	`return cur_area = ptmp;`
261	239	markom	`return cur_area = NULL;`
262	30	lampret	`}`
263
264	1486	nogj	`/* Sets the valid bit (Used only by memory controllers) */`
265	1748	jeremybenn	`void`
266			`set_mem_valid (struct dev_memarea *mem, int valid)`
267	882	simons	`{`
268	1486	nogj	`mem->valid = valid;`
269	882	simons	`}`
270
271	1486	nogj	`/* Adjusts the read and write delays for the memory area pointed to by mem. */`
272	1748	jeremybenn	`void`
273			`adjust_rw_delay (struct dev_memarea *mem, int delayr, int delayw)`
274	560	markom	`{`
275	1486	nogj	`mem->ops.delayr = delayr;`
276			`mem->ops.delayw = delayw;`
277	1319	phoenix	`}`
278	560	markom
279	1748	jeremybenn	`static uint8_t`
280			`eval_mem_8_inv (oraddr_t memaddr, void *dat)`
281	1319	phoenix	`{`
282	1748	jeremybenn	`except_handle (EXCEPT_BUSERR, cur_vadd);`
283	1486	nogj	`return 0;`
284	1319	phoenix	`}`
285
286	1748	jeremybenn	`static uint16_t`
287			`eval_mem_16_inv (oraddr_t memaddr, void *dat)`
288	1319	phoenix	`{`
289	1748	jeremybenn	`except_handle (EXCEPT_BUSERR, cur_vadd);`
290	1486	nogj	`return 0;`
291			`}`
292	1319	phoenix
293	1748	jeremybenn	`static uint32_t`
294			`eval_mem_32_inv (oraddr_t memaddr, void *dat)`
295	1486	nogj	`{`
296	1748	jeremybenn	`except_handle (EXCEPT_BUSERR, cur_vadd);`
297	1486	nogj	`return 0;`
298	560	markom	`}`
299
300	1748	jeremybenn	`static void`
301			`set_mem_8_inv (oraddr_t memaddr, uint8_t val, void *dat)`
302	560	markom	`{`
303	1748	jeremybenn	`except_handle (EXCEPT_BUSERR, cur_vadd);`
304	1319	phoenix	`}`
305	560	markom
306	1748	jeremybenn	`static void`
307			`set_mem_16_inv (oraddr_t memaddr, uint16_t val, void *dat)`
308	1319	phoenix	`{`
309	1748	jeremybenn	`except_handle (EXCEPT_BUSERR, cur_vadd);`
310	1319	phoenix	`}`
311
312	1748	jeremybenn	`static void`
313			`set_mem_32_inv (oraddr_t memaddr, uint32_t val, void *dat)`
314	1319	phoenix	`{`
315	1748	jeremybenn	`except_handle (EXCEPT_BUSERR, cur_vadd);`
316	1486	nogj	`}`
317	1319	phoenix
318	1748	jeremybenn	`uint8_t`
319			`eval_mem_8_inv_direct (oraddr_t memaddr, void *dat)`
320	1486	nogj	`{`
321			`struct dev_memarea *mem = dat;`
322
323	1748	jeremybenn	`PRINTF ("ERROR: Invalid 8-bit direct read from memory %" PRIxADDR "\n",`
324			`mem->addr_compare \| memaddr);`
325	1486	nogj	`return 0;`
326	560	markom	`}`
327
328	1748	jeremybenn	`uint16_t`
329			`eval_mem_16_inv_direct (oraddr_t memaddr, void *dat)`
330	560	markom	`{`
331	1486	nogj	`struct dev_memarea *mem = dat;`
332
333	1748	jeremybenn	`PRINTF ("ERROR: Invalid 16-bit direct read from memory %" PRIxADDR "\n",`
334			`mem->addr_compare \| memaddr);`
335	1486	nogj	`return 0;`
336	1319	phoenix	`}`
337	560	markom
338	1748	jeremybenn	`uint32_t`
339			`eval_mem_32_inv_direct (oraddr_t memaddr, void *dat)`
340	1319	phoenix	`{`
341	1486	nogj	`struct dev_memarea *mem = dat;`
342
343	1748	jeremybenn	`PRINTF ("ERROR: Invalid 32-bit direct read from memory %" PRIxADDR "\n",`
344			`mem->addr_compare \| memaddr);`
345	1486	nogj	`return 0;`
346	1319	phoenix	`}`
347
348	1748	jeremybenn	`void`
349			`set_mem_8_inv_direct (oraddr_t memaddr, uint8_t val, void *dat)`
350	1319	phoenix	`{`
351	1486	nogj	`struct dev_memarea *mem = dat;`
352	1319	phoenix
353	1748	jeremybenn	`PRINTF ("ERROR: Invalid 32-bit direct write to memory %" PRIxADDR "\n",`
354			`mem->addr_compare \| memaddr);`
355	1486	nogj	`}`
356
357	1748	jeremybenn	`void`
358			`set_mem_16_inv_direct (oraddr_t memaddr, uint16_t val, void *dat)`
359	1486	nogj	`{`
360			`struct dev_memarea *mem = dat;`
361
362	1748	jeremybenn	`PRINTF ("ERROR: Invalid 16-bit direct write to memory %" PRIxADDR "\n",`
363			`mem->addr_compare \| memaddr);`
364	1486	nogj	`}`
365
366	1748	jeremybenn	`void`
367			`set_mem_32_inv_direct (oraddr_t memaddr, uint32_t val, void *dat)`
368	1486	nogj	`{`
369			`struct dev_memarea *mem = dat;`
370
371	1748	jeremybenn	`PRINTF ("ERROR: Invalid 32-bit direct write to memory %" PRIxADDR "\n",`
372			`mem->addr_compare \| memaddr);`
373	1486	nogj	`}`
374
375			`/* For cpu accesses`
376			`*`
377			`* NOTE: This function _is_ only called from eval_mem32 below and`
378			`* {i,d}c_simulate_read. _Don't_ call it from anywere else.`
379			`*/`
380	1748	jeremybenn	`uint32_t`
381			`evalsim_mem32 (oraddr_t memaddr, oraddr_t vaddr)`
382	1486	nogj	`{`
383			`struct dev_memarea *mem;`
384
385	1748	jeremybenn	`if ((mem = verify_memoryarea (memaddr)))`
386			`{`
387			`runtime.sim.mem_cycles += mem->ops.delayr;`
388			`return mem->ops.readfunc32 (memaddr & mem->size_mask,`
389			`mem->ops.read_dat32);`
390			`}`
391			`else`
392			`{`
393			`PRINTF ("EXCEPTION: read out of memory (32-bit access to %" PRIxADDR`
394			`")\n", memaddr);`
395			`except_handle (EXCEPT_BUSERR, vaddr);`
396			`}`
397	1486	nogj
398			`return 0;`
399	560	markom	`}`
400
401	1486	nogj	`/* For cpu accesses`
402			`*`
403			`* NOTE: This function _is_ only called from eval_mem16 below and`
404			`* {i,d}c_simulate_read. _Don't_ call it from anywere else.`
405			`*/`
406	1748	jeremybenn	`uint16_t`
407			`evalsim_mem16 (oraddr_t memaddr, oraddr_t vaddr)`
408	1486	nogj	`{`
409			`struct dev_memarea *mem;`
410
411	1748	jeremybenn	`if ((mem = verify_memoryarea (memaddr)))`
412			`{`
413			`runtime.sim.mem_cycles += mem->ops.delayr;`
414			`return mem->ops.readfunc16 (memaddr & mem->size_mask,`
415			`mem->ops.read_dat16);`
416			`}`
417			`else`
418			`{`
419			`PRINTF ("EXCEPTION: read out of memory (16-bit access to %" PRIxADDR`
420			`")\n", memaddr);`
421			`except_handle (EXCEPT_BUSERR, vaddr);`
422			`}`
423	1486	nogj
424			`return 0;`
425			`}`
426
427			`/* For cpu accesses`
428			`*`
429			`* NOTE: This function _is_ only called from eval_mem8 below and`
430			`* {i,d}c_simulate_read. _Don't_ call it from anywere else.`
431			`*/`
432	1748	jeremybenn	`uint8_t`
433			`evalsim_mem8 (oraddr_t memaddr, oraddr_t vaddr)`
434	1486	nogj	`{`
435			`struct dev_memarea *mem;`
436
437	1748	jeremybenn	`if ((mem = verify_memoryarea (memaddr)))`
438			`{`
439			`runtime.sim.mem_cycles += mem->ops.delayr;`
440			`return mem->ops.readfunc8 (memaddr & mem->size_mask,`
441			`mem->ops.read_dat8);`
442			`}`
443			`else`
444			`{`
445			`PRINTF ("EXCEPTION: read out of memory (8-bit access to %" PRIxADDR`
446			`")\n", memaddr);`
447			`except_handle (EXCEPT_BUSERR, vaddr);`
448			`}`
449	1486	nogj
450			`return 0;`
451			`}`
452
453	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
454			`*`
455			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
456			`*/`
457	1748	jeremybenn	`uint32_t`
458			`eval_mem32 (oraddr_t memaddr, int *breakpoint)`
459	2	cvs	`{`
460	1350	nogj	`uint32_t temp;`
461	1486	nogj	`oraddr_t phys_memaddr;`
462	123	markom
463	547	markom	`if (config.sim.mprofile)`
464			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
465
466	1748	jeremybenn	`if (memaddr & 3)`
467			`{`
468			`except_handle (EXCEPT_ALIGN, memaddr);`
469			`return 0;`
470			`}`
471	557	markom
472	631	simons	`if (config.debug.enabled)`
473	1748	jeremybenn	`breakpoint += check_debug_unit (DebugLoadAddress, memaddr); / 28/05/01 CZ */`
474	631	simons
475	1748	jeremybenn	`phys_memaddr = dmmu_translate (memaddr, 0);`
476	1386	nogj	`if (except_pending)`
477	574	markom	`return 0;`
478
479	1748	jeremybenn	`if (config.dc.enabled)`
480			`temp = dc_simulate_read (phys_memaddr, memaddr, 4);`
481	1486	nogj	`else`
482	1748	jeremybenn	`temp = evalsim_mem32 (phys_memaddr, memaddr);`
483	611	simons
484	550	markom	`if (config.debug.enabled)`
485	1748	jeremybenn	`breakpoint += check_debug_unit (DebugLoadData, temp); / MM170901 */`
486	1486	nogj
487	239	markom	`return temp;`
488	66	lampret	`}`
489
490	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
491			`*`
492			`* STATISTICS OK`
493			`*/`
494	1748	jeremybenn	`uint32_t`
495			`eval_direct32 (oraddr_t memaddr, int through_mmu, int through_dc)`
496	1240	phoenix	`{`
497	1486	nogj	`oraddr_t phys_memaddr;`
498			`struct dev_memarea *mem;`
499	1240	phoenix
500	1748	jeremybenn	`if (memaddr & 3)`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1765