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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "spr_defs.h"
#include "execute.h"
#include "sprs.h"
#include "support/profile.h"
#include "dmmu.h"
#include "immu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
#if DYNAMIC_EXECUTION
#include "dyn_rec.h"
#endif
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = NULL;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
static oraddr_t cur_vadd;
 
/* Read functions */
uint32_t eval_mem_32_inv(oraddr_t, void *);
uint16_t eval_mem_16_inv(oraddr_t, void *);
uint8_t eval_mem_8_inv(oraddr_t, void *);
uint32_t eval_mem_32_inv_direct(oraddr_t, void *);
uint16_t eval_mem_16_inv_direct(oraddr_t, void *);
uint8_t eval_mem_8_inv_direct(oraddr_t, void *);
 
/* Write functions */
void set_mem_32_inv(oraddr_t, uint32_t, void *);
void set_mem_16_inv(oraddr_t, uint16_t, void *);
void set_mem_8_inv(oraddr_t, uint8_t, void *);
void set_mem_32_inv_direct(oraddr_t, uint32_t, void *);
void set_mem_16_inv_direct(oraddr_t, uint16_t, void *);
void set_mem_8_inv_direct(oraddr_t, uint8_t, void *);
 
/* Calculates bit mask to fit the data */
static unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask,
                                             oraddr_t addr_compare,
                                             uint32_t size, unsigned mc_dev)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32"\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32"\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask, (*pptmp)->size);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->log = NULL;
  (*pptmp)->valid = 1;
  (*pptmp)->next = NULL;
 
  return *pptmp;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this device will be checked first for a match
   and will be accessed in case of overlaping memory areas.
   Only one device can have this set to 1 (used for memory controller) */
struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev,
                                 struct mem_ops *ops)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  struct dev_memarea *mem;
 
  mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1,
                                 mc_dev);
 
  memcpy(&mem->ops, ops, sizeof(struct mem_ops));
  memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops));
 
  if(!ops->readfunc32) {
    mem->ops.readfunc32 = eval_mem_32_inv;
    mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
    mem->direct_ops.read_dat32 = mem;
  }
  if(!ops->readfunc16) {
    mem->ops.readfunc16 = eval_mem_16_inv;
    mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
    mem->direct_ops.read_dat16 = mem;
  }
  if(!ops->readfunc8) {
    mem->ops.readfunc8 = eval_mem_8_inv;
    mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
    mem->direct_ops.read_dat8 = mem;
  }
 
  if(!ops->writefunc32) {
    mem->ops.writefunc32 = set_mem_32_inv;
    mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
    mem->direct_ops.write_dat32 = mem;
  }
  if(!ops->writefunc16) {
    mem->ops.writefunc16 = set_mem_16_inv;
    mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
    mem->direct_ops.write_dat16 = mem;
  }
  if(!ops->writefunc8) {
    mem->ops.writefunc8 = set_mem_8_inv;
    mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
    mem->direct_ops.write_dat8 = mem;
  }
 
  if(!ops->writeprog) {
    mem->ops.writeprog = mem->ops.writefunc32;
    mem->ops.writeprog_dat = mem->ops.write_dat32;
  }
 
  if(ops->log) {
    if(!(mem->log = fopen(ops->log, "w")))
      PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log);
  }
 
  return mem;
}
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
      return cur_area = ptmp;
  return cur_area = NULL;
}
 
/* Sets the valid bit (Used only by memory controllers) */
void set_mem_valid(struct dev_memarea *mem, int valid)
{
  mem->valid = valid;
}
 
/* Adjusts the read and write delays for the memory area pointed to by mem. */
void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw)
{
  mem->ops.delayr = delayr;
  mem->ops.delayw = delayw;
}
 
uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat)
{
  except_handle(EXCEPT_BUSERR, cur_vadd);
  return 0;
}
 
uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat)
{
  except_handle(EXCEPT_BUSERR, cur_vadd);
  return 0;
}
 
uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat)
{
  except_handle(EXCEPT_BUSERR, cur_vadd);
  return 0;
}
 
void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat)
{
  except_handle(EXCEPT_BUSERR, cur_vadd);
}
 
void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat)
{
  except_handle(EXCEPT_BUSERR, cur_vadd);
}
 
void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat)
{
  except_handle(EXCEPT_BUSERR, cur_vadd);
}
 
uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n",
         mem->addr_compare | memaddr);
  return 0;
}
 
uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n",
         mem->addr_compare | memaddr);
  return 0;
}
 
uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n",
         mem->addr_compare | memaddr);
  return 0;
}
 
void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
         mem->addr_compare | memaddr);
}
 
void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n",
         mem->addr_compare | memaddr);
}
 
void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat)
{
  struct dev_memarea *mem = dat;
 
  PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
         mem->addr_compare | memaddr);
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from eval_mem32 below and
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr)
{
  struct dev_memarea *mem;
 
  if((mem = verify_memoryarea(memaddr))) {
    runtime.sim.mem_cycles += mem->ops.delayr;
    return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32);
  } else {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, vaddr);
  }
 
  return 0;
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from eval_mem16 below and
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
 */
inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr)
{
  struct dev_memarea *mem;
 
  if((mem = verify_memoryarea(memaddr))) {
    runtime.sim.mem_cycles += mem->ops.delayr;
    return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16);
  } else {
    PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, vaddr);
  }
 
  return 0;
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from eval_mem8 below and
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
 */
inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr)
{
  struct dev_memarea *mem;
 
  if((mem = verify_memoryarea(memaddr))) {
    runtime.sim.mem_cycles += mem->ops.delayr;
    return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8);
  } else {
    PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, vaddr);
  }
 
  return 0;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  phys_memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(phys_memaddr, memaddr, 4);
  else
    temp = evalsim_mem32(phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
 
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return 0;
  }
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    return dc_simulate_read(phys_memaddr, memaddr, 4);
  else {
    if((mem = verify_memoryarea(phys_memaddr)))
      return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask,
                                        mem->direct_ops.read_dat32);
    else
      PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %"
             PRIxADDR"\n", memaddr, phys_memaddr);
  }
 
  return 0;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
 
  phys_memaddr = memaddr;
#if !(DYNAMIC_EXECUTION)
  phys_memaddr = immu_translate(memaddr);
 
  if (except_pending)
    return 0;
#endif
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(phys_memaddr, memaddr);
  else
    temp = evalsim_mem32(phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK
 */
uint32_t eval_insn_direct(oraddr_t memaddr, int* breakpoint, int through_mmu)
{
  uint32_t temp;
  int brk;
 
  if(through_mmu)
    memaddr = peek_into_itlb(memaddr);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress, memaddr);
 
  temp = eval_direct32(memaddr, &brk, 0, 0);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData, temp);
 
  return temp;
}
 
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  phys_memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(phys_memaddr, memaddr, 2);
  else
    temp = evalsim_mem16(phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
 
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return 0;
  }
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    return dc_simulate_read(phys_memaddr, memaddr, 2);
  else {
    if((mem = verify_memoryarea(phys_memaddr)))
      return mem->direct_ops.readfunc16(phys_memaddr & mem->size_mask,
                                        mem->direct_ops.read_dat16);
    else
      PRINTF("ERR: 16-bit read out of memory area: %"PRIxADDR" (physical: %"
             PRIxADDR"\n", memaddr, phys_memaddr);
  }
 
  return 0;
}
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  phys_memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(phys_memaddr, memaddr, 1);
  else
    temp = evalsim_mem8(phys_memaddr, memaddr);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  phys_memaddr = memaddr;
 
  if (through_mmu)
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    return dc_simulate_read(phys_memaddr, memaddr, 1);
  else {
    if((mem = verify_memoryarea(phys_memaddr)))
      return mem->direct_ops.readfunc8(phys_memaddr & mem->size_mask,
                                       mem->direct_ops.read_dat8);
    else
      PRINTF("ERR: 8-bit read out of memory area: %"PRIxADDR" (physical: %"
             PRIxADDR"\n", memaddr, phys_memaddr);
  }
 
  return 0;
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from set_mem32 below and
 * dc_simulate_write.  _Don't_ call it from anywere else.
 */
inline void setsim_mem32(oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
{
  struct dev_memarea *mem;
 
  if((mem = verify_memoryarea(memaddr))) {
    cur_vadd = vaddr;
    runtime.sim.mem_cycles += mem->ops.delayw;
    mem->ops.writefunc32(memaddr & mem->size_mask, value, mem->ops.write_dat32);
#if DYNAMIC_EXECUTION
    dyn_checkwrite(memaddr);
#endif
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, vaddr);
  }
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from set_mem16 below and
 * dc_simulate_write.  _Don't_ call it from anywere else.
 */
inline void setsim_mem16(oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
{
  struct dev_memarea *mem;
 
  if((mem = verify_memoryarea(memaddr))) {
    cur_vadd = vaddr;
    runtime.sim.mem_cycles += mem->ops.delayw;
    mem->ops.writefunc16(memaddr & mem->size_mask, value, mem->ops.write_dat16);
#if DYNAMIC_EXECUTION
    dyn_checkwrite(memaddr);
#endif
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, vaddr);
  }
}
 
/* For cpu accesses
 *
 * NOTE: This function _is_ only called from set_mem8 below and
 * dc_simulate_write.  _Don't_ call it from anywere else.
 */
inline void setsim_mem8(oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
{
  struct dev_memarea *mem;
 
  if((mem = verify_memoryarea(memaddr))) {
    cur_vadd = vaddr;
    runtime.sim.mem_cycles += mem->ops.delayw;
    mem->ops.writefunc8(memaddr & mem->size_mask, value, mem->ops.write_dat8);
#if DYNAMIC_EXECUTION
    dyn_checkwrite(memaddr);
#endif
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, vaddr);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  phys_memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  if(config.dc.enabled)
    dc_simulate_write(phys_memaddr, memaddr, value, 4);
  else
    setsim_mem32(phys_memaddr, memaddr, value);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  phys_memaddr = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    phys_memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
  if(through_dc)
    dc_simulate_write(memaddr, memaddr, value, 4);
  else {
    if((mem = verify_memoryarea(phys_memaddr)))
      mem->direct_ops.writefunc32(phys_memaddr & mem->size_mask, value,
                                  mem->direct_ops.write_dat32);
    else
      PRINTF("ERR: 32-bit write out of memory area: %"PRIxADDR" (physical: %"
             PRIxADDR")\n", memaddr, phys_memaddr);
  }
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  phys_memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  if(config.dc.enabled)
    dc_simulate_write(phys_memaddr, memaddr, value, 2);
  else
    setsim_mem16(phys_memaddr, memaddr, value);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  phys_memaddr = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  if(through_dc)
    dc_simulate_write(memaddr, memaddr, value, 2);
  else {
    if((mem = verify_memoryarea(phys_memaddr)))
      mem->direct_ops.writefunc16(phys_memaddr & mem->size_mask, value,
                                  mem->direct_ops.write_dat16);
    else
      PRINTF("ERR: 16-bit write out of memory area: %"PRIxADDR" (physical: %"
             PRIxADDR"\n", memaddr, phys_memaddr);
  }
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  oraddr_t phys_memaddr;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  phys_memaddr = memaddr;
 
  phys_memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  if(config.dc.enabled)
    dc_simulate_write(phys_memaddr, memaddr, value, 1);
  else
    setsim_mem8(phys_memaddr, memaddr, value);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
  oraddr_t phys_memaddr;
  struct dev_memarea *mem;
 
  phys_memaddr = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  if(through_dc)
    dc_simulate_write(phys_memaddr, memaddr, value, 1);
  else {
    if((mem = verify_memoryarea(phys_memaddr)))
      mem->direct_ops.writefunc8(phys_memaddr & mem->size_mask, value,
                                 mem->direct_ops.write_dat8);
    else
      PRINTF("ERR: 8-bit write out of memory area: %"PRIxADDR" (physical: %"
             PRIxADDR"\n", memaddr, phys_memaddr);
  }
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
/* set_program32 - same as set_direct32, but it also writes to memory that is
 *                 non-writeable to the rest of the sim.  Used to do program
 *                 loading.
 */
void set_program32(oraddr_t memaddr, uint32_t value)
{
  struct dev_memarea *mem;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  if((mem = verify_memoryarea(memaddr))) {
    mem->ops.writeprog(memaddr & mem->size_mask, value, mem->ops.writeprog_dat);
  } else
    PRINTF("ERR: 32-bit program load out of memory area: %"PRIxADDR"\n",
           memaddr);
}
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
  int breakpoint;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", eval_direct8(i + j, &breakpoint, 0, 0));
        } else PRINTF("XX ");
        j++;
      } else {
        uint32_t _insn = eval_direct32(i, &breakpoint, 0, 0);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
/* Closes files, etc. */
 
void done_memory_table (void)
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status (void)
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32"\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size);
    PRINTF ("\t");
    if (ptmp->ops.delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->ops.delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3	1486	nogj	Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
4	2	cvs
5			`This file is part of OpenRISC 1000 Architectural Simulator.`
6
7			`This program is free software; you can redistribute it and/or modify`
8			`it under the terms of the GNU General Public License as published by`
9			`the Free Software Foundation; either version 2 of the License, or`
10			`(at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
20
21	66	lampret	`/* Abstract memory and routines that go with this. I need to`
22	2	cvs	`add all sorts of other abstract entities. Currently we have`
23			`only memory. */`
24
25	221	markom	`#include <stdlib.h>`
26	2	cvs	`#include <stdio.h>`
27			`#include <ctype.h>`
28			`#include <string.h>`
29
30	6	lampret	`#include "config.h"`
31	1350	nogj
32			`#ifdef HAVE_INTTYPES_H`
33			`#include <inttypes.h>`
34			`#endif`
35
36			`#include "port.h"`
37	6	lampret
38	1350	nogj	`#include "arch.h"`
39	2	cvs	`#include "parse.h"`
40			`#include "abstract.h"`
41	1358	nogj	`#include "sim-config.h"`
42	261	markom	`#include "labels.h"`
43	32	lampret	`#include "except.h"`
44	123	markom	`#include "debug_unit.h"`
45	134	markom	`#include "opcode/or32.h"`
46	1432	nogj	`#include "spr_defs.h"`
47			`#include "execute.h"`
48			`#include "sprs.h"`
49	547	markom	`#include "support/profile.h"`
50	1308	phoenix	`#include "dmmu.h"`
51	1446	nogj	`#include "immu.h"`
52	1308	phoenix	`#include "dcache_model.h"`
53			`#include "icache_model.h"`
54			`#include "debug.h"`
55	1344	nogj	`#include "stats.h"`
56	2	cvs
57	1452	nogj	`#if DYNAMIC_EXECUTION`
58			`#include "dyn_rec.h"`
59			`#endif`
60
61	138	markom	`extern char *disassembled;`
62	2	cvs
63	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
64			`peripheral devices. */`
65			`struct dev_memarea *dev_list;`
66
67	221	markom	`/* Temporary variable to increase speed. */`
68			`struct dev_memarea *cur_area;`
69
70	970	simons	`/* Pointer to memory controller device descriptor. */`
71	1486	nogj	`struct dev_memarea *mc_area = NULL;`
72	970	simons
73	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
74			`int data_ci, insn_ci;`
75
76	525	simons	`/* Virtual address of current access. */`
77	1486	nogj	`static oraddr_t cur_vadd;`
78	525	simons
79	1486	nogj	`/* Read functions */`
80			`uint32_t eval_mem_32_inv(oraddr_t, void *);`
81			`uint16_t eval_mem_16_inv(oraddr_t, void *);`
82			`uint8_t eval_mem_8_inv(oraddr_t, void *);`
83			`uint32_t eval_mem_32_inv_direct(oraddr_t, void *);`
84			`uint16_t eval_mem_16_inv_direct(oraddr_t, void *);`
85			`uint8_t eval_mem_8_inv_direct(oraddr_t, void *);`
86
87			`/* Write functions */`
88			`void set_mem_32_inv(oraddr_t, uint32_t, void *);`
89			`void set_mem_16_inv(oraddr_t, uint16_t, void *);`
90			`void set_mem_8_inv(oraddr_t, uint8_t, void *);`
91			`void set_mem_32_inv_direct(oraddr_t, uint32_t, void *);`
92			`void set_mem_16_inv_direct(oraddr_t, uint16_t, void *);`
93			`void set_mem_8_inv_direct(oraddr_t, uint8_t, void *);`
94
95	261	markom	`/* Calculates bit mask to fit the data */`
96	1486	nogj	`static unsigned int bit_mask (uint32_t data) {`
97	261	markom	`int i = 0;`
98			`data--;`
99	382	markom	`while (data >> i)`
100	261	markom	`data \|= 1 << i++;`
101			`return data;`
102			`}`
103
104			`/* Register read and write function for a memory area.`
105			`addr is inside the area, if addr & addr_mask == addr_compare`
106			`(used also by peripheral devices like 16450 UART etc.) */`
107	1486	nogj	`struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask,`
108			`oraddr_t addr_compare,`
109			`uint32_t size, unsigned mc_dev)`
110	30	lampret	`{`
111	239	markom	`struct dev_memarea **pptmp;`
112	1350	nogj	`unsigned int size_mask = bit_mask (size);`
113	261	markom	`int found_error = 0;`
114			`addr_compare &= addr_mask;`
115	221	markom
116	1486	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n",`
117			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size);`
118	239	markom	`/* Go to the end of the list. */`
119	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
120			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
121			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
122	262	markom	`if (!found_error) {`
123	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
124	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
125	1486	nogj	`", size %08"PRIx32"\n",`
126			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size);`
127	262	markom	`}`
128	261	markom	`found_error = 1;`
129	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
130	1486	nogj	`", size %08"PRIx32"\n",`
131	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
132	1486	nogj	`(pptmp)->addr_compare \| (pptmp)->size_mask, (*pptmp)->size);`
133	261	markom	`}`
134
135			`if (found_error)`
136			`exit (-1);`
137	537	markom
138	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
139	970	simons
140			`if (mc_dev)`
141			`mc_area = *pptmp;`
142
143	261	markom	`(*pptmp)->addr_mask = addr_mask;`
144			`(*pptmp)->addr_compare = addr_compare;`
145	239	markom	`(*pptmp)->size = size;`
146	261	markom	`(*pptmp)->size_mask = size_mask;`
147	1486	nogj	`(*pptmp)->log = NULL;`
148			`(*pptmp)->valid = 1;`
149	239	markom	`(*pptmp)->next = NULL;`
150	1486	nogj
151			`return *pptmp;`
152	261	markom	`}`
153	221	markom
154	261	markom	`/* Register read and write function for a memory area.`
155			`Memory areas should be aligned. Memory area is rounded up to`
156			`fit the nearest 2^n aligment.`
157	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
158	1486	nogj	`If mc_dev is 1, this device will be checked first for a match`
159			`and will be accessed in case of overlaping memory areas.`
160	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
161	1486	nogj	`struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev,`
162			`struct mem_ops *ops)`
163	261	markom	`{`
164	1350	nogj	`unsigned int size_mask = bit_mask (size);`
165			`unsigned int addr_mask = ~size_mask;`
166	1486	nogj	`struct dev_memarea *mem;`
167
168			`mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1,`
169			`mc_dev);`
170
171			`memcpy(&mem->ops, ops, sizeof(struct mem_ops));`
172			`memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops));`
173
174			`if(!ops->readfunc32) {`
175			`mem->ops.readfunc32 = eval_mem_32_inv;`
176			`mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;`
177			`mem->direct_ops.read_dat32 = mem;`
178			`}`
179			`if(!ops->readfunc16) {`
180			`mem->ops.readfunc16 = eval_mem_16_inv;`
181			`mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;`
182			`mem->direct_ops.read_dat16 = mem;`
183			`}`
184			`if(!ops->readfunc8) {`
185			`mem->ops.readfunc8 = eval_mem_8_inv;`
186			`mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;`
187			`mem->direct_ops.read_dat8 = mem;`
188			`}`
189
190			`if(!ops->writefunc32) {`
191			`mem->ops.writefunc32 = set_mem_32_inv;`
192			`mem->direct_ops.writefunc32 = set_mem_32_inv_direct;`
193			`mem->direct_ops.write_dat32 = mem;`
194			`}`
195			`if(!ops->writefunc16) {`
196			`mem->ops.writefunc16 = set_mem_16_inv;`
197			`mem->direct_ops.writefunc16 = set_mem_16_inv_direct;`
198			`mem->direct_ops.write_dat16 = mem;`
199			`}`
200			`if(!ops->writefunc8) {`
201			`mem->ops.writefunc8 = set_mem_8_inv;`
202			`mem->direct_ops.writefunc8 = set_mem_8_inv_direct;`
203			`mem->direct_ops.write_dat8 = mem;`
204			`}`
205
206			`if(!ops->writeprog) {`
207			`mem->ops.writeprog = mem->ops.writefunc32;`
208			`mem->ops.writeprog_dat = mem->ops.write_dat32;`
209			`}`
210
211			`if(ops->log) {`
212			`if(!(mem->log = fopen(ops->log, "w")))`
213			`PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log);`
214			`}`
215
216			`return mem;`
217	30	lampret	`}`
218
219			`/* Check if access is to registered area of memory. */`
220	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
221	30	lampret	`{`
222	239	markom	`struct dev_memarea *ptmp;`
223	221	markom
224	970	simons	`/* Check memory controller space first */`
225			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
226			`return cur_area = mc_area;`
227
228			`/* Check cached value */`
229	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
230			`return cur_area;`
231
232			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
233	1375	nogj	`/* Check list of registered devices. */`
234			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
235			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
236			`return cur_area = ptmp;`
237	239	markom	`return cur_area = NULL;`
238	30	lampret	`}`
239
240	1486	nogj	`/* Sets the valid bit (Used only by memory controllers) */`
241			`void set_mem_valid(struct dev_memarea *mem, int valid)`
242	882	simons	`{`
243	1486	nogj	`mem->valid = valid;`
244	882	simons	`}`
245
246	1486	nogj	`/* Adjusts the read and write delays for the memory area pointed to by mem. */`
247			`void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw)`
248	560	markom	`{`
249	1486	nogj	`mem->ops.delayr = delayr;`
250			`mem->ops.delayw = delayw;`
251	1319	phoenix	`}`
252	560	markom
253	1486	nogj	`uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat)`
254	1319	phoenix	`{`
255	1486	nogj	`except_handle(EXCEPT_BUSERR, cur_vadd);`
256			`return 0;`
257	1319	phoenix	`}`
258
259	1486	nogj	`uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat)`
260	1319	phoenix	`{`
261	1486	nogj	`except_handle(EXCEPT_BUSERR, cur_vadd);`
262			`return 0;`
263			`}`
264	1319	phoenix
265	1486	nogj	`uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat)`
266			`{`
267			`except_handle(EXCEPT_BUSERR, cur_vadd);`
268			`return 0;`
269	560	markom	`}`
270
271	1486	nogj	`void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat)`
272	560	markom	`{`
273	1486	nogj	`except_handle(EXCEPT_BUSERR, cur_vadd);`
274	1319	phoenix	`}`
275	560	markom
276	1486	nogj	`void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat)`
277	1319	phoenix	`{`
278	1486	nogj	`except_handle(EXCEPT_BUSERR, cur_vadd);`
279	1319	phoenix	`}`
280
281	1486	nogj	`void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat)`
282	1319	phoenix	`{`
283	1486	nogj	`except_handle(EXCEPT_BUSERR, cur_vadd);`
284			`}`
285	1319	phoenix
286	1486	nogj	`uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat)`
287			`{`
288			`struct dev_memarea *mem = dat;`
289
290			`PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n",`
291			`mem->addr_compare \| memaddr);`
292			`return 0;`
293	560	markom	`}`
294
295	1486	nogj	`uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat)`
296	560	markom	`{`
297	1486	nogj	`struct dev_memarea *mem = dat;`
298
299			`PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n",`
300			`mem->addr_compare \| memaddr);`
301			`return 0;`
302	1319	phoenix	`}`
303	560	markom
304	1486	nogj	`uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat)`
305	1319	phoenix	`{`
306	1486	nogj	`struct dev_memarea *mem = dat;`
307
308			`PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n",`
309			`mem->addr_compare \| memaddr);`
310			`return 0;`
311	1319	phoenix	`}`
312
313	1486	nogj	`void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat)`
314	1319	phoenix	`{`
315	1486	nogj	`struct dev_memarea *mem = dat;`
316	1319	phoenix
317	1486	nogj	`PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",`
318			`mem->addr_compare \| memaddr);`
319			`}`
320
321			`void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat)`
322			`{`
323			`struct dev_memarea *mem = dat;`
324
325			`PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n",`
326			`mem->addr_compare \| memaddr);`
327			`}`
328
329			`void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat)`
330			`{`
331			`struct dev_memarea *mem = dat;`
332
333			`PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",`
334			`mem->addr_compare \| memaddr);`
335			`}`
336
337			`/* For cpu accesses`
338			`*`
339			`* NOTE: This function _is_ only called from eval_mem32 below and`
340			`* {i,d}c_simulate_read. _Don't_ call it from anywere else.`
341			`*/`
342			`inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr)`
343			`{`
344			`struct dev_memarea *mem;`
345
346			`if((mem = verify_memoryarea(memaddr))) {`
347			`runtime.sim.mem_cycles += mem->ops.delayr;`
348			`return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32);`
349			`} else {`
350			`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
351			`memaddr);`
352			`except_handle(EXCEPT_BUSERR, vaddr);`
353	560	markom	`}`
354	1486	nogj
355			`return 0;`
356	560	markom	`}`
357
358	1486	nogj	`/* For cpu accesses`
359			`*`
360			`* NOTE: This function _is_ only called from eval_mem16 below and`
361			`* {i,d}c_simulate_read. _Don't_ call it from anywere else.`
362			`*/`
363			`inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr)`
364			`{`
365			`struct dev_memarea *mem;`
366
367			`if((mem = verify_memoryarea(memaddr))) {`
368			`runtime.sim.mem_cycles += mem->ops.delayr;`
369			`return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16);`
370			`} else {`
371			`PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",`
372			`memaddr);`
373			`except_handle(EXCEPT_BUSERR, vaddr);`
374			`}`
375
376			`return 0;`
377			`}`
378
379			`/* For cpu accesses`
380			`*`
381			`* NOTE: This function _is_ only called from eval_mem8 below and`
382			`* {i,d}c_simulate_read. _Don't_ call it from anywere else.`
383			`*/`
384			`inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr)`
385			`{`
386			`struct dev_memarea *mem;`
387
388			`if((mem = verify_memoryarea(memaddr))) {`
389			`runtime.sim.mem_cycles += mem->ops.delayr;`
390			`return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8);`
391			`} else {`
392			`PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",`
393			`memaddr);`
394			`except_handle(EXCEPT_BUSERR, vaddr);`
395			`}`
396
397			`return 0;`
398			`}`
399
400	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
401			`*`
402			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
403			`*/`
404	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
405	2	cvs	`{`
406	1350	nogj	`uint32_t temp;`
407	1486	nogj	`oraddr_t phys_memaddr;`
408	123	markom
409	547	markom	`if (config.sim.mprofile)`
410			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
411
412	538	markom	`if (memaddr & 3) {`
413			`except_handle (EXCEPT_ALIGN, memaddr);`
414			`return 0;`
415			`}`
416	557	markom
417	631	simons	`if (config.debug.enabled)`
418			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
419
420	1486	nogj	`phys_memaddr = dmmu_translate(memaddr, 0);`
421	1386	nogj	`if (except_pending)`
422	574	markom	`return 0;`
423
424	992	simons	`if (config.dc.enabled)`
425	1486	nogj	`temp = dc_simulate_read(phys_memaddr, memaddr, 4);`
426			`else`
427			`temp = evalsim_mem32(phys_memaddr, memaddr);`
428	611	simons
429	550	markom	`if (config.debug.enabled)`
430	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
431	1486	nogj
432	239	markom	`return temp;`
433	66	lampret	`}`
434
435	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
436			`*`
437			`* STATISTICS OK`
438			`*/`
439	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
440			`int through_dc)`
441	1240	phoenix	`{`
442	1486	nogj	`oraddr_t phys_memaddr;`
443			`struct dev_memarea *mem;`
444	1240	phoenix
445			`if (memaddr & 3) {`
446			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
447	1486	nogj	`return 0;`
448	1240	phoenix	`}`
449
450	1486	nogj	`phys_memaddr = memaddr;`
451	1240	phoenix
452			`if (through_mmu)`
453	1486	nogj	`phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
454	1240	phoenix
455			`if (through_dc)`
456	1486	nogj	`return dc_simulate_read(phys_memaddr, memaddr, 4);`
457	1240	phoenix	`else {`
458	1486	nogj	`if((mem = verify_memoryarea(phys_memaddr)))`
459			`return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask,`
460			`mem->direct_ops.read_dat32);`
461			`else`
462			`PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %"`
463			`PRIxADDR"\n", memaddr, phys_memaddr);`
464	1240	phoenix	`}`
465
466	1486	nogj	`return 0;`
467	1240	phoenix	`}`
468
469
470	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
471			`*`
472			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
473			`*/`
474	1386	nogj	`uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)`
475	349	simons	`{`
476	1350	nogj	`uint32_t temp;`
477	1486	nogj	`oraddr_t phys_memaddr;`
478	349	simons
479	547	markom	`if (config.sim.mprofile)`
480			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
481	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
482	1244	hpanther
483	1486	nogj	`phys_memaddr = memaddr;`
484	1452	nogj	`#if !(DYNAMIC_EXECUTION)`
485	1486	nogj	`phys_memaddr = immu_translate(memaddr);`
486	1386	nogj
487			`if (except_pending)`
488			`return 0;`
489	1452	nogj	`#endif`
490	1386	nogj
491			`if (config.debug.enabled)`
492			`*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);`
493
494	631	simons	`if (config.ic.enabled)`
495	1486	nogj	`temp = ic_simulate_fetch(phys_memaddr, memaddr);`
496			`else`
497			`temp = evalsim_mem32(phys_memaddr, memaddr);`
498	611	simons
499	1386	nogj	`if (config.debug.enabled)`
500			`*breakpoint += CheckDebugUnit(DebugLoadData,temp);`

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