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/* except.c -- Simulation of OR1K exceptions

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include "config.h"

#ifdef HAVE_INTTYPES_H

#include <inttypes.h>

#endif

#include "port.h"

#include "arch.h"

#include "abstract.h"

#include "except.h"

#include "sim-config.h"

#include "debug_unit.h"

#include "opcode/or32.h"

#include "spr_defs.h"

#include "execute.h"

#include "sprs.h"

extern oraddr_t pcprev;

int except_pending = 0;

static const char *except_names[] = {

 NULL,

 "Reset",

 "Bus Error",

 "Data Page Fault",

 "Insn Page Fault",

 "Tick timer",

 "Alignment",

 "Illegal instruction",

 "Interrupt",

 "Data TLB Miss",

 "Insn TLB Miss",

 "Range",

 "System Call",

 "Trap" };

static const char *except_name(oraddr_t except)

{

  return except_names[except >> 8];

}

/* Asserts OR1K exception. */

void except_handle(oraddr_t except, oraddr_t ea)

{

  if(debug_ignore_exception (except))

    return;

  except_pending = 1;

  if (config.sim.verbose)

    PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR

           ", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR

           ", cycles %lld, #%lld\n",

           except, except_name(except), pcprev, ea, cpu_state.pc, pcnext,

           cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions);

  pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);

  cpu_state.sprs[SPR_EEAR_BASE] =  ea;

  cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR];

  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE;   /* Disable overflow flag exception. */

  cpu_state.sprs[SPR_SR] |= SPR_SR_SM;    /* SUPV mode */

  cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE);   /* Disable interrupts. */

  /* Address translation is always disabled when starting exception. */

  cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;

  cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME;

  switch(except) {

  /* EPCR is irrelevent */

  case EXCEPT_RESET:

    break;

  /* EPCR is loaded with address of instruction that caused the exception */

  /* All these exceptions happen during a simulated instruction */

  case EXCEPT_BUSERR:

  case EXCEPT_DPF:

  case EXCEPT_IPF:

  case EXCEPT_ALIGN:

  case EXCEPT_ILLEGAL:

  case EXCEPT_DTLBMISS:

  case EXCEPT_ITLBMISS:

  case EXCEPT_RANGE:

  case EXCEPT_TRAP:

    mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));

    break;

  /* EPCR is loaded with address of next not-yet-executed instruction */

  case EXCEPT_SYSCALL:

    mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0));

    break;

  /* These exceptions happen AFTER (or before) an instruction has been

   * simulated, therefore the pc already points to the *next* instruction */

  case EXCEPT_TICK:

  case EXCEPT_INT:

    mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));

    /* If we don't update the pc now, then it will only happen *after* the next

     * instruction (There would be serious problems if the next instruction just

     * happens to be a branch), when it should happen NOW. */

    cpu_state.pc = pcnext;

    pcnext += 4;

    break;

  }

  cpu_state.delay_insn = 0;

}