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/* execute.c -- OR1K architecture dependent simulation

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* Most of the OR1K simulation is done in here.

   When SIMPLE_EXECUTION is defined below a file insnset.c is included!

*/

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <ctype.h>

#include "config.h"

#ifdef HAVE_INTTYPES_H

#include <inttypes.h>

#endif

#include "port.h"

#include "arch.h"

#include "branch_predict.h"

#include "abstract.h"

#include "labels.h"

#include "parse.h"

#include "execute.h"

#include "except.h"

#include "sprs.h"

#include "sim-config.h"

#include "debug_unit.h"

#include "opcode/or32.h"

#include "immu.h"

#include "dmmu.h"

#include "debug.h"

#include "stats.h"

/* General purpose registers. */

uorreg_t reg[MAX_GPRS];

/* Instruction queue */

struct iqueue_entry iqueue[20];

/* Is current insn in execution a delay insn? */

int delay_insn;

/* Benchmark multi issue execution */

int multissue[20];

int issued_per_cycle = 4;

/* Whether break was hit - so we can step over a break */

static int break_just_hit = 0;

/* Completition queue */

struct iqueue_entry icomplet[20];

/* Program counter (and translated PC) */

oraddr_t pc;

oraddr_t pc_phy;

/* Previous program counter */

oraddr_t pcprev = 0;

/* Temporary program counter */

oraddr_t pcnext;

/* Delay instruction effective address register */

oraddr_t pcdelay;

/* CCR */

int flag;

/* CCR (for dependency calculation) */

char ccr_flag[10] = "flag";

/* Store buffer analysis - stores are accumulated and commited when IO is idle */

static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;

static int sbuf_buf[MAX_SBUF_LEN] = {0};

static int sbuf_prev_cycles = 0;

/* Num cycles waiting for stores to complete */

int sbuf_wait_cyc = 0;

/* Number of total store cycles */

int sbuf_total_cyc = 0;

/* Whether we are doing statistical analysis */

int do_stats = 0;

/* Local data needed for execution.  */

static int next_delay_insn;

static int breakpoint;

/* Effective address of instructions that have an effective address.  This is

 * only used to get dump_exe_log correct */

static oraddr_t insn_ea;

/* Implementation specific.

   Get an actual value of a specific register. */

uorreg_t evalsim_reg(unsigned int regno)

{

  if (regno < MAX_GPRS) {

    return reg[regno];

  } else {

    PRINTF("\nABORT: read out of registers\n");

    runtime.sim.cont_run = 0;

    return 0;

  }

}

/* Implementation specific.

   Set a specific register with value. */

void setsim_reg(unsigned int regno, uorreg_t value)

{

  if (regno == 0)               /* gpr0 is always zero */

    value = 0;

  if (regno < MAX_GPRS) {

    reg[regno] = value;

  } else {

    PRINTF("\nABORT: write out of registers\n");

    runtime.sim.cont_run = 0;

  }

}

/* Implementation specific.

   Set a specific register with value. */

inline static void set_reg(int regno, uorreg_t value)

{

#if 0   

  if (strcmp(regstr, FRAME_REG) == 0) {

    PRINTF("FP (%s) modified by insn at %x. ", FRAME_REG, pc);

    PRINTF("Old:%.8lx  New:%.8lx\n", eval_reg(regno), value);

  }

  if (strcmp(regstr, STACK_REG) == 0) {

    PRINTF("SP (%s) modified by insn at %x. ", STACK_REG, pc);

    PRINTF("Old:%.8lx  New:%.8lx\n", eval_reg(regno), value);

  }

#endif

  if (regno < MAX_GPRS) {

    reg[regno] = value;

#if RAW_RANGE_STATS

    raw_stats.reg[regno] = runtime.sim.cycles;

#endif /* RAW_RANGE */

  } else {

    PRINTF("\nABORT: write out of registers\n");

    runtime.sim.cont_run = 0;

  }

}

/* Implementation specific.

   Evaluates source operand opd. */

static uorreg_t eval_operand_val(uint32_t insn, struct insn_op_struct *opd)

{

  unsigned long operand = 0;

  unsigned long sbit;

  unsigned int nbits = 0;

  while(1) {

    operand |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;

    nbits += opd->data;

    if(opd->type & OPTYPE_OP)

      break;

    opd++;

  }

  if(opd->type & OPTYPE_SIG) {

    sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;

    if(operand & (1 << sbit)) operand |= ~REG_C(0) << sbit;

  }

  return operand;

}

/* Does source operand depend on computation of dstoperand? Return

   non-zero if yes.

 Cycle t                 Cycle t+1

dst: irrelevant         src: immediate                  always 0

dst: reg1 direct        src: reg2 direct                0 if reg1 != reg2

dst: reg1 disp          src: reg2 direct                always 0

dst: reg1 direct        src: reg2 disp                  0 if reg1 != reg2

dst: reg1 disp          src: reg2 disp                  always 1 (store must

                                                        finish before load)

dst: flag               src: flag                       always 1

*/

int depend_operands(prev, next)

     struct iqueue_entry *prev;

     struct iqueue_entry *next;

{

  /* Find destination type. */

  unsigned long type = 0;

  int prev_dis, next_dis;

  orreg_t prev_reg_val = 0;

  struct insn_op_struct *opd;

  if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG

      && or32_opcodes[next->insn_index].flags & OR32_R_FLAG)

    return 1;

  opd = op_start[prev->insn_index];

  prev_dis = 0;

  while (1) {

    if (opd->type & OPTYPE_DIS)

      prev_dis = 1;

    if (opd->type & OPTYPE_DST) {

      type = opd->type;

      if (prev_dis)

        type |= OPTYPE_DIS;

      /* Destination is always a register */

      prev_reg_val = eval_operand_val (prev->insn, opd);

      break;

    }

    if (opd->type & OPTYPE_LAST)

      return 0; /* Doesn't have a destination operand */

    if (opd->type & OPTYPE_OP)

      prev_dis = 0;

    opd++;

  }

  /* We search all source operands - if we find confict => return 1 */

  opd = op_start[next->insn_index];

  next_dis = 0;

  while (1) {

    if (opd->type & OPTYPE_DIS)

      next_dis = 1;

    /* This instruction sequence also depends on order of execution:

     * l.lw r1, k(r1)

     * l.sw k(r1), r4

     * Here r1 is a destination in l.sw */

    /* FIXME: This situation is not handeld here when r1 == r2:

     * l.sw k(r1), r4

     * l.lw r3, k(r2)

     */

    if (!(opd->type & OPTYPE_DST) || (next_dis && (opd->type & OPTYPE_DST))) {

      if (opd->type & OPTYPE_REG)

        if (eval_operand_val (next->insn, opd) == prev_reg_val)

          return 1;

    }

    if (opd->type & OPTYPE_LAST)

      break;

    opd++;

  }

  return 0;

}

/* Sets a new SPR_SR_OV value, based on next register value */

#if SET_OV_FLAG

#define set_ov_flag(value) if((value) & 0x80000000) setsprbits (SPR_SR, SPR_SR_OV, 1); else setsprbits (SPR_SR, SPR_SR_OV, 0)

#else

#define set_ov_flag(value)

#endif

/* Modified by CZ 26/05/01 for new mode execution */

/* Fetch returns nonzero if instruction should NOT be executed.  */

static inline int fetch()

{

  /* Update the pc for pending exceptions, or get physical pc */

  if (!pending.valid)

    pc_phy = immu_translate(pc);

  if(pending.valid)

    except_handle_backend(pending.type, pending.address, pending.saved);

  if (CHECK_BREAKPOINTS) {

    /* MM: Check for breakpoint.  This has to be done in fetch cycle,

       because of peripheria.

       MM1709: if we cannot access the memory entry, we could not set the

       breakpoint earlier, so just chech the breakpoint list.  */

    if (has_breakpoint (pc_phy) && !break_just_hit) {

      break_just_hit = 1;

      return 1; /* Breakpoint set. */

    }

    break_just_hit = 0;

  }

  pc_phy &= ~ADDR_C(0x3);

  runtime.cpu.instructions++;

  /* Fetch instruction. */

  iqueue[0].insn_addr = pc;

  iqueue[0].insn = eval_insn (pc_phy, &breakpoint);

  /* update_pc will be called after execution */

  return 0;

}

/* This code actually updates the PC value.  */

static inline void update_pc ()

{

  delay_insn = next_delay_insn;

  pcprev = pc; /* Store value for later */

  pc = pcnext;

  pcnext = delay_insn ? pcdelay : pcnext + 4;

}

#if SIMPLE_EXECUTION

static inline

#endif

void analysis (struct iqueue_entry *current)

{

  if (config.cpu.dependstats) {

    /* Dynamic, dependency stats. */

    adddstats(icomplet[0].insn_index, current->insn_index, 1, check_depend());

    /* Dynamic, functional units stats. */

    addfstats(or32_opcodes[icomplet[0].insn_index].func_unit,

              or32_opcodes[current->insn_index].func_unit, 1, check_depend());

    /* Dynamic, single stats. */

    addsstats(current->insn_index, 1);

  }

  if (config.cpu.superscalar) {

    if ((or32_opcodes[current->insn_index].func_unit == it_branch) ||

        (or32_opcodes[current->insn_index].func_unit == it_jump))

      runtime.sim.storecycles += 0;

    if (or32_opcodes[current->insn_index].func_unit == it_store)

      runtime.sim.storecycles += 1;

    if (or32_opcodes[current->insn_index].func_unit == it_load)

      runtime.sim.loadcycles += 1;

#if 0        

    if ((icomplet[0].func_unit == it_load) && check_depend())

      runtime.sim.loadcycles++;

#endif

    /* Pseudo multiple issue benchmark */

    if ((multissue[or32_opcodes[current->insn_index].func_unit] < 1) ||

        (check_depend()) || (issued_per_cycle < 1)) {

      int i;

      for (i = 0; i < 20; i++)

        multissue[i] = 2;

      issued_per_cycle = 2;

      runtime.cpu.supercycles++;

      if (check_depend())

        runtime.cpu.hazardwait++;

      multissue[it_unknown] = 2;

      multissue[it_shift] = 2;

      multissue[it_compare] = 1;

      multissue[it_branch] = 1;

      multissue[it_jump] = 1;

      multissue[it_extend] = 2;

      multissue[it_nop] = 2;

      multissue[it_move] = 2;

      multissue[it_movimm] = 2;

      multissue[it_arith] = 2;

      multissue[it_store] = 2;

      multissue[it_load] = 2;

    }

    multissue[or32_opcodes[current->insn_index].func_unit]--;

    issued_per_cycle--;

  }

  if (config.cpu.dependstats)

    /* Instruction waits in completition buffer until retired. */

    memcpy (&icomplet[0], current, sizeof (struct iqueue_entry));

  if (config.sim.history) {

    int i;

    /* History of execution */

    for (i = HISTEXEC_LEN - 1; i; i--)

      histexec[i] = histexec[i - 1];

    histexec[0] = icomplet[0].insn_addr;        /* add last insn */

  }

  if (config.sim.exe_log) dump_exe_log();

}

/* Store buffer analysis - stores are accumulated and commited when IO is idle */

static inline void sbuf_store (int cyc) {

  int delta = runtime.sim.cycles - sbuf_prev_cycles;

  sbuf_total_cyc += cyc;

  sbuf_prev_cycles = runtime.sim.cycles;

  //PRINTF (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

  //PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);

  /* Take stores from buffer, that occured meanwhile */

  while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {

    delta -= sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  if (sbuf_count)

    sbuf_buf[sbuf_tail] -= delta;

  /* Store buffer is full, take one out */

  if (sbuf_count >= config.cpu.sbuf_len) {

    sbuf_wait_cyc += sbuf_buf[sbuf_tail];

    runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];

    sbuf_prev_cycles += sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  /* Put newest store in the buffer */

  sbuf_buf[sbuf_head] = cyc;

  sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;

  sbuf_count++;

  //PRINTF ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

}

/* Store buffer analysis - previous stores should commit, before any load */

static inline void sbuf_load () {

  int delta = runtime.sim.cycles - sbuf_prev_cycles;

  sbuf_prev_cycles = runtime.sim.cycles;

  //PRINTF (">LOAD  %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

  //PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);

  /* Take stores from buffer, that occured meanwhile */

  while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {

    delta -= sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  if (sbuf_count)

    sbuf_buf[sbuf_tail] -= delta;

  /* Wait for all stores to complete */

  while (sbuf_count > 0) {

    sbuf_wait_cyc += sbuf_buf[sbuf_tail];

    runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];

    sbuf_prev_cycles += sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  //PRINTF ("|LOAD  %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

}

/* Outputs dissasembled instruction */

void dump_exe_log ()

{

  oraddr_t insn_addr = iqueue[0].insn_addr;

  unsigned int i, j;

  uorreg_t operand;

  if (insn_addr == 0xffffffff) return;

  if ((config.sim.exe_log_start <= runtime.cpu.instructions) &&

      ((config.sim.exe_log_end <= 0) ||

       (runtime.cpu.instructions <= config.sim.exe_log_end))) {

    if (config.sim.exe_log_marker &&

        !(runtime.cpu.instructions % config.sim.exe_log_marker)) {

      fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions);

    }

    switch (config.sim.exe_log_type) {

    case EXE_LOG_HARDWARE:

      fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %"PRIxADDR":  ",

               runtime.cpu.instructions, insn_addr);

      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(insn_addr),

               evalsim_mem8_void(insn_addr + 1));

      fprintf (runtime.sim.fexe_log, "%.2x%.2x",

               evalsim_mem8_void(insn_addr + 2),

               evalsim_mem8_void(insn_addr + 3));

      for(i = 0; i < MAX_GPRS; i++) {

        if (i % 4 == 0)

          fprintf(runtime.sim.fexe_log, "\n");

        fprintf (runtime.sim.fexe_log, "GPR%2u: %"PRIxREG"  ", i, reg[i]);

      }

      fprintf (runtime.sim.fexe_log, "\n");

      fprintf (runtime.sim.fexe_log, "SR   : %.8lx  ", mfspr(SPR_SR));

      fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx  ", mfspr(SPR_EPCR_BASE));

      fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx  ", mfspr(SPR_EEAR_BASE));

      fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));

      break;

    case EXE_LOG_SIMPLE:

    case EXE_LOG_SOFTWARE:

      {

        extern char *disassembled;

        disassemble_index (iqueue[0].insn, iqueue[0].insn_index);

        {

          struct label_entry *entry;

          entry = get_label(insn_addr);

          if (entry)

            fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);

        }

        if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {

          struct insn_op_struct *opd = op_start[iqueue[0].insn_index];

          j = 0;

          while (1) {

            operand = eval_operand_val (iqueue[0].insn, opd);

            while (!(opd->type & OPTYPE_OP))

              opd++;

            if (opd->type & OPTYPE_DIS) {

              fprintf (runtime.sim.fexe_log, "EA =%"PRIxADDR" PA =%"PRIxADDR" ",

                       insn_ea, peek_into_dtlb(insn_ea,0,0));

              opd++; /* Skip of register operand */

              j++;

            } else if ((opd->type & OPTYPE_REG) && operand) {

              fprintf (runtime.sim.fexe_log, "r%-2i=%"PRIxREG" ",

                       (int)operand, evalsim_reg (operand));

            } else

              fprintf (runtime.sim.fexe_log, "             ");

            j++;

            if(opd->type & OPTYPE_LAST)

              break;

            opd++;

          }

          while(j < 3) {

            fprintf (runtime.sim.fexe_log, "             ");

            j++;

          }

        }

        fprintf (runtime.sim.fexe_log, "%"PRIxADDR" ", insn_addr);

        fprintf (runtime.sim.fexe_log, "%s\n", disassembled);

      }

    }

  }

}

/* Dump registers - 'r' or 't' command */

void dumpreg()

{

  int i;

  oraddr_t physical_pc;

  if ((physical_pc = peek_into_itlb(iqueue[0].insn_addr))) {

    /*

     * PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", iqueue[0].insn_addr, physical_pc);

     */

    dumpmemory(physical_pc, physical_pc + 4, 1, 0);

  }

  else {

    PRINTF("INTERNAL SIMULATOR ERROR:\n");

    PRINTF("no translation for currently executed instruction\n");

  }

  // generate_time_pretty (temp, runtime.sim.cycles * config.sim.clkcycle_ps);

  PRINTF(" (executed) [cycle %lld, #%lld]\n", runtime.sim.cycles,

         runtime.cpu.instructions);

  if (config.cpu.superscalar)

    PRINTF ("Superscalar CYCLES: %u", runtime.cpu.supercycles);

  if (config.cpu.hazards)

    PRINTF ("  HAZARDWAIT: %u\n", runtime.cpu.hazardwait);

  else

    if (config.cpu.superscalar)

      PRINTF ("\n");

  if ((physical_pc = peek_into_itlb(pc))) {

    /*

     * PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", pc, physical_pc);

     */

    dumpmemory(physical_pc, physical_pc + 4, 1, 0);

  }

  else

    PRINTF("%"PRIxADDR": : xxxxxxxx  ITLB miss follows", pc);

  PRINTF(" (next insn) %s", (delay_insn?"(delay insn)":""));

  for(i = 0; i < MAX_GPRS; i++) {

    if (i % 4 == 0)

      PRINTF("\n");

    PRINTF("GPR%.2u: %"PRIxREG"  ", i, evalsim_reg(i));

  }

  PRINTF("flag: %u\n", flag);

}

/* Generated/built in decoding/executing function */

static inline void decode_execute (struct iqueue_entry *current);

/* Wrapper around real decode_execute function -- some statistics here only */

static inline void decode_execute_wrapper (struct iqueue_entry *current)

{

  breakpoint = 0;

  next_delay_insn = 0;

#ifndef HAS_EXECUTION

#error HAS_EXECUTION has to be defined in order to execute programs.

#endif

  if(config.debug.enabled && CheckDebugUnit(DebugInstructionFetch, pc_phy))

    breakpoint = 1;

  decode_execute (current);

#if SET_OV_FLAG

  /* Check for range exception */

  if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))

    except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));

#endif

  if(breakpoint)

    except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));

}

/* Reset the CPU */

void cpu_reset()

{

  int i;

  runtime.sim.cycles = 0;

  runtime.sim.loadcycles = 0;

  runtime.sim.storecycles = 0;