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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 1471

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1 706 markom 
/* execute.c -- Instruction specific functions.
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 
                 2000-2002 Marko Mlinar, markom@opencores.org
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
INSTRUCTION (l_add) {
22 1350 nogj 
  orreg_t temp1, temp2, temp3;
23 
  int8_t temp4;
24 706 markom 
 
25 1350 nogj 
  temp2 = (orreg_t)PARAM2;
26 
  temp3 = (orreg_t)PARAM1;
27 1170 csanchez 
  temp1 = temp2 + temp3;
28 1342 nogj 
  SET_PARAM0(temp1);
29 706 markom 
  set_ov_flag (temp1);
30 
  if (ARITH_SET_FLAG) {
31 
    flag = temp1 == 0;
32 
    setsprbits(SPR_SR, SPR_SR_F, flag);
33 
  }
34 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
35 1170 csanchez 
          setsprbits(SPR_SR, SPR_SR_CY, 1);
36 
  else
37 
          setsprbits(SPR_SR, SPR_SR_CY, 0);
38 706 markom 
 
39 
  temp4 = temp1;
40 
  if (temp4 == temp1)
41 1244 hpanther 
    or1k_mstats.byteadd++;
42 706 markom 
}
43 1170 csanchez 
INSTRUCTION (l_addc) {
44 1350 nogj 
  orreg_t temp1, temp2, temp3;
45 
  int8_t temp4;
46 1170 csanchez 
 
47 1350 nogj 
  temp2 = (orreg_t)PARAM2;
48 
  temp3 = (orreg_t)PARAM1;
49 1170 csanchez 
  temp1 = temp2 + temp3 + getsprbits(SPR_SR, SPR_SR_CY);
50 1342 nogj 
  SET_PARAM0(temp1);
51 1170 csanchez 
  set_ov_flag (temp1);
52 
  if (ARITH_SET_FLAG) {
53 
    flag = temp1 == 0;
54 
    setsprbits(SPR_SR, SPR_SR_F, flag);
55 
  }
56 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
57 1170 csanchez 
        setsprbits(SPR_SR, SPR_SR_CY, 1);
58 
  else
59 
        setsprbits(SPR_SR, SPR_SR_CY, 0);
60 
 
61 
  temp4 = temp1;
62 
  if (temp4 == temp1)
63 1244 hpanther 
    or1k_mstats.byteadd++;
64 1170 csanchez 
}
65 706 markom 
INSTRUCTION (l_sw) {
66 
  int old_cyc = 0;
67 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
68 1342 nogj 
  set_mem32(PARAM0, PARAM1, &breakpoint);
69 706 markom 
  if (config.cpu.sbuf_len) {
70 884 markom 
    int t = runtime.sim.mem_cycles;
71 
    runtime.sim.mem_cycles = old_cyc;
72 706 markom 
    sbuf_store (t - old_cyc);
73 
  }
74 
}
75 
INSTRUCTION (l_sb) {
76 
  int old_cyc = 0;
77 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
78 1342 nogj 
  set_mem8(PARAM0, PARAM1, &breakpoint);
79 706 markom 
  if (config.cpu.sbuf_len) {
80 884 markom 
    int t = runtime.sim.mem_cycles;
81 
    runtime.sim.mem_cycles = old_cyc;
82 706 markom 
    sbuf_store (t- old_cyc);
83 
  }
84 
}
85 
INSTRUCTION (l_sh) {
86 
  int old_cyc = 0;
87 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
88 1342 nogj 
  set_mem16(PARAM0, PARAM1, &breakpoint);
89 706 markom 
  if (config.cpu.sbuf_len) {
90 884 markom 
    int t = runtime.sim.mem_cycles;
91 
    runtime.sim.mem_cycles = old_cyc;
92 706 markom 
    sbuf_store (t - old_cyc);
93 
  }
94 
}
95 
INSTRUCTION (l_lwz) {
96 1350 nogj 
  uint32_t val;
97 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
98 1342 nogj 
  val = eval_mem32(PARAM1, &breakpoint);
99 706 markom 
  /* If eval operand produced exception don't set anything */
100 1386 nogj 
  if (!except_pending)
101 1342 nogj 
    SET_PARAM0(val);
102 706 markom 
}
103 
INSTRUCTION (l_lbs) {
104 1350 nogj 
  int8_t val;
105 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
106 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
107 706 markom 
  /* If eval opreand produced exception don't set anything */
108 1386 nogj 
  if (!except_pending)
109 1342 nogj 
    SET_PARAM0(val);
110 706 markom 
}
111 
INSTRUCTION (l_lbz) {
112 1350 nogj 
  uint8_t val;
113 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
114 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
115 706 markom 
  /* If eval opreand produced exception don't set anything */
116 1386 nogj 
  if (!except_pending)
117 1342 nogj 
    SET_PARAM0(val);
118 706 markom 
}
119 
INSTRUCTION (l_lhs) {
120 1350 nogj 
  int16_t val;
121 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
122 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
123 706 markom 
  /* If eval opreand produced exception don't set anything */
124 1386 nogj 
  if (!except_pending)
125 1342 nogj 
    SET_PARAM0(val);
126 706 markom 
}
127 
INSTRUCTION (l_lhz) {
128 1350 nogj 
  uint16_t val;
129 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
130 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
131 706 markom 
  /* If eval opreand produced exception don't set anything */
132 1386 nogj 
  if (!except_pending)
133 1342 nogj 
    SET_PARAM0(val);
134 706 markom 
}
135 
INSTRUCTION (l_movhi) {
136 1342 nogj 
  SET_PARAM0(PARAM1 << 16);
137 706 markom 
}
138 
INSTRUCTION (l_and) {
139 1350 nogj 
  uorreg_t temp1;
140 1342 nogj 
  temp1 = PARAM1 & PARAM2;
141 
  set_ov_flag (temp1);
142 
  SET_PARAM0(temp1);
143 706 markom 
  if (ARITH_SET_FLAG) {
144 
    flag = temp1 == 0;
145 
    setsprbits(SPR_SR, SPR_SR_F, flag);
146 
  }
147 
}
148 
INSTRUCTION (l_or) {
149 1350 nogj 
  uorreg_t temp1;
150 1342 nogj 
  temp1 = PARAM1 | PARAM2;
151 
  set_ov_flag (temp1);
152 
  SET_PARAM0(temp1);
153 706 markom 
}
154 
INSTRUCTION (l_xor) {
155 1350 nogj 
  uorreg_t temp1;
156 1342 nogj 
  temp1 = PARAM1 ^ PARAM2;
157 
  set_ov_flag (temp1);
158 
  SET_PARAM0(temp1);
159 706 markom 
}
160 
INSTRUCTION (l_sub) {
161 1350 nogj 
  orreg_t temp1;
162 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
163 1342 nogj 
  set_ov_flag (temp1);
164 
  SET_PARAM0(temp1);
165 706 markom 
}
166 
/*int mcount = 0;*/
167 
INSTRUCTION (l_mul) {
168 1350 nogj 
  orreg_t temp1;
169 706 markom 
 
170 1350 nogj 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
171 1342 nogj 
  set_ov_flag (temp1);
172 
  SET_PARAM0(temp1);
173 706 markom 
  /*if (!(mcount++ & 1023)) {
174 997 markom 
    PRINTF ("[%i]\n",mcount);
175 706 markom 
    }*/
176 
}
177 
INSTRUCTION (l_div) {
178 1350 nogj 
  orreg_t temp3, temp2, temp1;
179 706 markom 
 
180 1342 nogj 
  temp3 = PARAM2;
181 
  temp2 = PARAM1;
182 706 markom 
  if (temp3)
183 
    temp1 = temp2 / temp3;
184 
  else {
185 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
186 706 markom 
    return;
187 
  }
188 1342 nogj 
  set_ov_flag (temp1);
189 
  SET_PARAM0(temp1);
190 706 markom 
}
191 
INSTRUCTION (l_divu) {
192 1350 nogj 
  uorreg_t temp3, temp2, temp1;
193 706 markom 
 
194 1342 nogj 
  temp3 = PARAM2;
195 
  temp2 = PARAM1;
196 
  if (temp3)
197 
    temp1 = temp2 / temp3;
198 
  else {
199 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
200 1342 nogj 
    return;
201 
  }
202 
  set_ov_flag (temp1);
203 
  SET_PARAM0(temp1);
204 884 markom 
  /* runtime.sim.cycles += 16; */
205 706 markom 
}
206 
INSTRUCTION (l_sll) {
207 1350 nogj 
  uorreg_t temp1;
208 1342 nogj 
 
209 
  temp1 = PARAM1 << PARAM2;
210 
  set_ov_flag (temp1);
211 
  SET_PARAM0(temp1);
212 884 markom 
  /* runtime.sim.cycles += 2; */
213 706 markom 
}
214 
INSTRUCTION (l_sra) {
215 1350 nogj 
  orreg_t temp1;
216 706 markom 
 
217 1350 nogj 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
218 1342 nogj 
  set_ov_flag (temp1);
219 
  SET_PARAM0(temp1);
220 884 markom 
  /* runtime.sim.cycles += 2; */
221 706 markom 
}
222 
INSTRUCTION (l_srl) {
223 1350 nogj 
  uorreg_t temp1;
224 1342 nogj 
  temp1 = PARAM1 >> PARAM2;
225 
  set_ov_flag (temp1);
226 
  SET_PARAM0(temp1);
227 884 markom 
  /* runtime.sim.cycles += 2; */
228 706 markom 
}
229 
INSTRUCTION (l_bf) {
230 
  if (config.bpb.enabled) {
231 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
232 1244 hpanther 
    or1k_mstats.bf[flag][fwd]++;
233 713 markom 
    bpb_update(current->insn_addr, flag);
234 706 markom 
  }
235 
  if (flag) {
236 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
237 706 markom 
    btic_update(pcnext);
238 
    next_delay_insn = 1;
239 
  } else {
240 1432 nogj 
    btic_update(cpu_state.pc);
241 706 markom 
  }
242 
}
243 
INSTRUCTION (l_bnf) {
244 
  if (config.bpb.enabled) {
245 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
246 1244 hpanther 
    or1k_mstats.bnf[!flag][fwd]++;
247 713 markom 
    bpb_update(current->insn_addr, flag == 0);
248 706 markom 
  }
249 
  if (flag == 0) {
250 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
251 706 markom 
    btic_update(pcnext);
252 
    next_delay_insn = 1;
253 
  } else {
254 1432 nogj 
    btic_update(cpu_state.pc);
255 706 markom 
  }
256 
}
257 
INSTRUCTION (l_j) {
258 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
259 706 markom 
  next_delay_insn = 1;
260 
}
261 
INSTRUCTION (l_jal) {
262 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
263 706 markom 
 
264 1432 nogj 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
265 706 markom 
  next_delay_insn = 1;
266 
  if (config.sim.profile) {
267 
    struct label_entry *tmp;
268 1432 nogj 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
269 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
270 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
271 
               tmp->name);
272 706 markom 
    else
273 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
274 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
275 
               cpu_state.pc_delay);
276 706 markom 
  }
277 
}
278 
INSTRUCTION (l_jalr) {
279 1432 nogj 
  cpu_state.pc_delay = PARAM0;
280 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
281 706 markom 
  next_delay_insn = 1;
282 
}
283 
INSTRUCTION (l_jr) {
284 1432 nogj 
  cpu_state.pc_delay = PARAM0;
285 706 markom 
  next_delay_insn = 1;
286 
  if (config.sim.profile)
287 1350 nogj 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
288 1432 nogj 
             cpu_state.pc_delay);
289 706 markom 
}
290 
INSTRUCTION (l_rfe) {
291 
  pcnext = mfspr(SPR_EPCR_BASE);
292 
  mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
293 
}
294 
INSTRUCTION (l_nop) {
295 1350 nogj 
  oraddr_t stackaddr;
296 
  uint32_t k = PARAM0;
297 706 markom 
  switch (k) {
298 
    case NOP_NOP:
299 
      break;
300 
    case NOP_EXIT:
301 1350 nogj 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
302 1343 nogj 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
303 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
304 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
305 
              runtime.cpu.instructions);
306 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
307 
              runtime.sim.cycles - runtime.sim.reset_cycles,
308 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
309 706 markom 
      if (config.debug.gdb_enabled)
310 
        set_stall_state (1);
311 
      else
312 1471 nogj 
        sim_done();
313 706 markom 
      break;
314 1319 phoenix 
    case NOP_CNT_RESET:
315 
      PRINTF("****************** counters reset ******************\n");
316 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
317 
      PRINTF("****************** counters reset ******************\n");
318 
      runtime.sim.reset_cycles = runtime.sim.cycles;
319 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
320 
      break;
321 706 markom 
    case NOP_PRINTF:
322 1350 nogj 
      stackaddr = evalsim_reg(4);
323 
      simprintf(stackaddr, evalsim_reg(3));
324 706 markom 
      debug(5, "simprintf %x\n", stackaddr);
325 
      break;
326 
    case NOP_REPORT:
327 1438 nogj 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
328 706 markom 
    default:
329 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
330 1350 nogj 
      PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
331 
             evalsim_reg(3));
332 706 markom 
      break;
333 
  }
334 
}
335 
INSTRUCTION (l_sfeq) {
336 1342 nogj 
  flag = PARAM0 == PARAM1;
337 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
338 
}
339 
INSTRUCTION (l_sfne) {
340 1342 nogj 
  flag = PARAM0 != PARAM1;
341 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
342 
}
343 
INSTRUCTION (l_sfgts) {
344 1350 nogj 
  flag = (orreg_t)PARAM0 > (orreg_t)PARAM1;
345 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
346 
}
347 
INSTRUCTION (l_sfges) {
348 1350 nogj 
  flag = (orreg_t)PARAM0 >= (orreg_t)PARAM1;
349 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
350 
}
351 
INSTRUCTION (l_sflts) {
352 1350 nogj 
  flag = (orreg_t)PARAM0 < (orreg_t)PARAM1;
353 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
354 
}
355 
INSTRUCTION (l_sfles) {
356 1350 nogj 
  flag = (orreg_t)PARAM0 <= (orreg_t)PARAM1;
357 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
358 
}
359 
INSTRUCTION (l_sfgtu) {
360 1350 nogj 
  flag = PARAM0 > PARAM1;
361 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
362 
}
363 
INSTRUCTION (l_sfgeu) {
364 1350 nogj 
  flag = PARAM0 >= PARAM1;
365 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
366 
}
367 
INSTRUCTION (l_sfltu) {
368 1350 nogj 
  flag = PARAM0 < PARAM1;
369 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
370 
}
371 
INSTRUCTION (l_sfleu) {
372 1350 nogj 
  flag = PARAM0 <= PARAM1;
373 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
374 
}
375 
INSTRUCTION (l_extbs) {
376 1350 nogj 
  int8_t x;
377 1342 nogj 
  x = PARAM1;
378 1350 nogj 
  SET_PARAM0((orreg_t)x);
379 706 markom 
}
380 
INSTRUCTION (l_extbz) {
381 1350 nogj 
  uint8_t x;
382 1342 nogj 
  x = PARAM1;
383 1350 nogj 
  SET_PARAM0((uorreg_t)x);
384 706 markom 
}
385 
INSTRUCTION (l_exths) {
386 1350 nogj 
  int16_t x;
387 1342 nogj 
  x = PARAM1;
388 1350 nogj 
  SET_PARAM0((orreg_t)x);
389 706 markom 
}
390 
INSTRUCTION (l_exthz) {
391 1350 nogj 
  uint16_t x;
392 1342 nogj 
  x = PARAM1;
393 1350 nogj 
  SET_PARAM0((uorreg_t)x);
394 706 markom 
}
395 
INSTRUCTION (l_extws) {
396 1350 nogj 
  int32_t x;
397 1342 nogj 
  x = PARAM1;
398 1350 nogj 
  SET_PARAM0((orreg_t)x);
399 706 markom 
}
400 
INSTRUCTION (l_extwz) {
401 1350 nogj 
  uint32_t x;
402 1342 nogj 
  x = PARAM1;
403 1350 nogj 
  SET_PARAM0((uorreg_t)x);
404 706 markom 
}
405 
INSTRUCTION (l_mtspr) {
406 1350 nogj 
  uint16_t regno = PARAM0 + PARAM2;
407 
  uorreg_t value = PARAM1;
408 706 markom 
 
409 
  if (runtime.sim.fspr_log) {
410 1350 nogj 
    fprintf(runtime.sim.fspr_log, "Write to SPR  : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);
411 706 markom 
  }
412 
 
413 
  if (mfspr(SPR_SR) & SPR_SR_SM)
414 
    mtspr(regno, value);
415 
  else {
416 997 markom 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
417 1471 nogj 
    sim_done();
418 706 markom 
  }
419 
}
420 
INSTRUCTION (l_mfspr) {
421 1350 nogj 
  uint16_t regno = PARAM1 + PARAM2;
422 
  uorreg_t value = mfspr(regno);
423 706 markom 
 
424 
  if (runtime.sim.fspr_log) {
425 1350 nogj 
    fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);
426 706 markom 
  }
427 
 
428 
  if (mfspr(SPR_SR) & SPR_SR_SM)
429 1342 nogj 
    SET_PARAM0(value);
430 706 markom 
  else {
431 1342 nogj 
    SET_PARAM0(0);
432 997 markom 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
433 1471 nogj 
    sim_done();
434 706 markom 
  }
435 
}
436 
INSTRUCTION (l_sys) {
437 
  except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
438 
}
439 
INSTRUCTION (l_trap) {
440 
  /* TODO: some SR related code here! */
441 
  except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
442 
}
443 
INSTRUCTION (l_mac) {
444 
  sprword lo, hi;
445 
  LONGEST l;
446 1350 nogj 
  orreg_t x, y;
447 
 
448 706 markom 
  lo = mfspr (SPR_MACLO);
449 
  hi = mfspr (SPR_MACHI);
450 1342 nogj 
  x = PARAM0;
451 
  y = PARAM1;
452 1350 nogj 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
453 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
454 
  l += (LONGEST) x * (LONGEST) y;
455 
 
456 
  /* This implementation is very fast - it needs only one cycle for mac.  */
457 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
458 
  hi = ((LONGEST)l) >> 32;
459 
  mtspr (SPR_MACLO, lo);
460 
  mtspr (SPR_MACHI, hi);
461 1308 phoenix 
  PRINTF ("(%08lx,%08lx)\n", hi, lo);
462 706 markom 
}
463 
INSTRUCTION (l_msb) {
464 
  sprword lo, hi;
465 
  LONGEST l;
466 1350 nogj 
  orreg_t x, y;
467 
 
468 706 markom 
  lo = mfspr (SPR_MACLO);
469 
  hi = mfspr (SPR_MACHI);
470 1342 nogj 
  x = PARAM0;
471 
  y = PARAM1;
472 1350 nogj 
 
473 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
474 
 
475 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
476 1342 nogj 
  l -= x * y;
477 706 markom 
 
478 
  /* This implementation is very fast - it needs only one cycle for msb.  */
479 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
480 
  hi = ((LONGEST)l) >> 32;
481 
  mtspr (SPR_MACLO, lo);
482 
  mtspr (SPR_MACHI, hi);
483 1308 phoenix 
  PRINTF ("(%08lx,%08lx)\n", hi, lo);
484 706 markom 
}
485 
INSTRUCTION (l_macrc) {
486 
  sprword lo, hi;
487 
  LONGEST l;
488 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
489 
  lo =  mfspr (SPR_MACLO);
490 
  hi =  mfspr (SPR_MACHI);
491 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
492 
  l >>= 28;
493 997 markom 
  //PRINTF ("<%08x>\n", (unsigned long)l);
494 1350 nogj 
  SET_PARAM0((orreg_t)l);
495 706 markom 
  mtspr (SPR_MACLO, 0);
496 
  mtspr (SPR_MACHI, 0);
497 
}
498 
INSTRUCTION (l_cmov) {
499 1342 nogj 
  SET_PARAM0(flag ? PARAM1 : PARAM2);
500 706 markom 
}
501 1338 andreje 
INSTRUCTION (l_ff1) {
502 1342 nogj 
  SET_PARAM0(ffs(PARAM1));
503 1338 andreje 
}
504 720 markom 
/******* Floating point instructions *******/
505 
/* Single precision */
506 
INSTRUCTION (lf_add_s) {
507 1350 nogj 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
508 720 markom 
}
509 
INSTRUCTION (lf_div_s) {
510 1350 nogj 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
511 720 markom 
}
512 1303 phoenix 
INSTRUCTION (lf_ftoi_s) {
513 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
514 720 markom 
}
515 
INSTRUCTION (lf_itof_s) {
516 1303 phoenix 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
517 
}
518 720 markom 
INSTRUCTION (lf_madd_s) {
519 1350 nogj 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
520 720 markom 
}
521 
INSTRUCTION (lf_mul_s) {
522 1350 nogj 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
523 720 markom 
}
524 
INSTRUCTION (lf_rem_s) {
525 1342 nogj 
  float temp = (float)PARAM1 / (float)PARAM2;
526 1350 nogj 
  SET_PARAM0(temp - (uint32_t)temp);
527 720 markom 
}
528 
INSTRUCTION (lf_sfeq_s) {
529 1342 nogj 
  flag = (float)PARAM0 == (float)PARAM1;
530 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
531 
}
532 
INSTRUCTION (lf_sfge_s) {
533 1342 nogj 
  flag = (float)PARAM0 >= (float)PARAM1;
534 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
535 
}
536 
INSTRUCTION (lf_sfgt_s) {
537 1342 nogj 
  flag = (float)PARAM0 > (float)PARAM1;
538 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
539 
}
540 
INSTRUCTION (lf_sfle_s) {
541 1342 nogj 
  flag = (float)PARAM0 <= (float)PARAM1;
542 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
543 
}
544 
INSTRUCTION (lf_sflt_s) {
545 1342 nogj 
  flag = (float)PARAM0 < (float)PARAM1;
546 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
547 
}
548 
INSTRUCTION (lf_sfne_s) {
549 1342 nogj 
  flag = (float)PARAM0 != (float)PARAM1;
550 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
551 
}
552 
INSTRUCTION (lf_sub_s) {
553 1350 nogj 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
554 720 markom 
}
555 
 
556 
/******* Custom instructions *******/
557 706 markom 
INSTRUCTION (l_cust1) {
558 713 markom 
  /*int destr = current->insn >> 21;
559 
    int src1r = current->insn >> 15;
560 
    int src2r = current->insn >> 9;*/
561 706 markom 
}
562 
INSTRUCTION (l_cust2) {
563 
}
564 
INSTRUCTION (l_cust3) {
565 
}
566 
INSTRUCTION (l_cust4) {
567 
}

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