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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 1506

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Line No. Rev Author Line
1 706 markom 
/* execute.c -- Instruction specific functions.
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 
                 2000-2002 Marko Mlinar, markom@opencores.org
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
INSTRUCTION (l_add) {
22 1350 nogj 
  orreg_t temp1, temp2, temp3;
23 
  int8_t temp4;
24 706 markom 
 
25 1350 nogj 
  temp2 = (orreg_t)PARAM2;
26 
  temp3 = (orreg_t)PARAM1;
27 1170 csanchez 
  temp1 = temp2 + temp3;
28 1342 nogj 
  SET_PARAM0(temp1);
29 706 markom 
  set_ov_flag (temp1);
30 
  if (ARITH_SET_FLAG) {
31 
    flag = temp1 == 0;
32 1506 nogj 
    if(flag)
33 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
34 
    else
35 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
36 706 markom 
  }
37 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
38 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
39 1170 csanchez 
  else
40 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
41 706 markom 
 
42 
  temp4 = temp1;
43 
  if (temp4 == temp1)
44 1244 hpanther 
    or1k_mstats.byteadd++;
45 706 markom 
}
46 1170 csanchez 
INSTRUCTION (l_addc) {
47 1350 nogj 
  orreg_t temp1, temp2, temp3;
48 
  int8_t temp4;
49 1170 csanchez 
 
50 1350 nogj 
  temp2 = (orreg_t)PARAM2;
51 
  temp3 = (orreg_t)PARAM1;
52 1506 nogj 
  temp1 = temp2 + temp3;
53 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
54 
    temp1++;
55 1342 nogj 
  SET_PARAM0(temp1);
56 1170 csanchez 
  set_ov_flag (temp1);
57 
  if (ARITH_SET_FLAG) {
58 
    flag = temp1 == 0;
59 1506 nogj 
    if(flag)
60 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
61 
    else
62 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
63 1170 csanchez 
  }
64 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
65 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
66 1170 csanchez 
  else
67 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
68 1170 csanchez 
 
69 
  temp4 = temp1;
70 
  if (temp4 == temp1)
71 1244 hpanther 
    or1k_mstats.byteadd++;
72 1170 csanchez 
}
73 706 markom 
INSTRUCTION (l_sw) {
74 
  int old_cyc = 0;
75 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
76 1342 nogj 
  set_mem32(PARAM0, PARAM1, &breakpoint);
77 706 markom 
  if (config.cpu.sbuf_len) {
78 884 markom 
    int t = runtime.sim.mem_cycles;
79 
    runtime.sim.mem_cycles = old_cyc;
80 706 markom 
    sbuf_store (t - old_cyc);
81 
  }
82 
}
83 
INSTRUCTION (l_sb) {
84 
  int old_cyc = 0;
85 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
86 1342 nogj 
  set_mem8(PARAM0, PARAM1, &breakpoint);
87 706 markom 
  if (config.cpu.sbuf_len) {
88 884 markom 
    int t = runtime.sim.mem_cycles;
89 
    runtime.sim.mem_cycles = old_cyc;
90 706 markom 
    sbuf_store (t- old_cyc);
91 
  }
92 
}
93 
INSTRUCTION (l_sh) {
94 
  int old_cyc = 0;
95 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
96 1342 nogj 
  set_mem16(PARAM0, PARAM1, &breakpoint);
97 706 markom 
  if (config.cpu.sbuf_len) {
98 884 markom 
    int t = runtime.sim.mem_cycles;
99 
    runtime.sim.mem_cycles = old_cyc;
100 706 markom 
    sbuf_store (t - old_cyc);
101 
  }
102 
}
103 
INSTRUCTION (l_lwz) {
104 1350 nogj 
  uint32_t val;
105 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
106 1342 nogj 
  val = eval_mem32(PARAM1, &breakpoint);
107 706 markom 
  /* If eval operand produced exception don't set anything */
108 1386 nogj 
  if (!except_pending)
109 1342 nogj 
    SET_PARAM0(val);
110 706 markom 
}
111 
INSTRUCTION (l_lbs) {
112 1350 nogj 
  int8_t val;
113 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
114 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
115 706 markom 
  /* If eval opreand produced exception don't set anything */
116 1386 nogj 
  if (!except_pending)
117 1342 nogj 
    SET_PARAM0(val);
118 706 markom 
}
119 
INSTRUCTION (l_lbz) {
120 1350 nogj 
  uint8_t val;
121 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
122 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
123 706 markom 
  /* If eval opreand produced exception don't set anything */
124 1386 nogj 
  if (!except_pending)
125 1342 nogj 
    SET_PARAM0(val);
126 706 markom 
}
127 
INSTRUCTION (l_lhs) {
128 1350 nogj 
  int16_t val;
129 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
130 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
131 706 markom 
  /* If eval opreand produced exception don't set anything */
132 1386 nogj 
  if (!except_pending)
133 1342 nogj 
    SET_PARAM0(val);
134 706 markom 
}
135 
INSTRUCTION (l_lhz) {
136 1350 nogj 
  uint16_t val;
137 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
138 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
139 706 markom 
  /* If eval opreand produced exception don't set anything */
140 1386 nogj 
  if (!except_pending)
141 1342 nogj 
    SET_PARAM0(val);
142 706 markom 
}
143 
INSTRUCTION (l_movhi) {
144 1342 nogj 
  SET_PARAM0(PARAM1 << 16);
145 706 markom 
}
146 
INSTRUCTION (l_and) {
147 1350 nogj 
  uorreg_t temp1;
148 1342 nogj 
  temp1 = PARAM1 & PARAM2;
149 
  set_ov_flag (temp1);
150 
  SET_PARAM0(temp1);
151 706 markom 
  if (ARITH_SET_FLAG) {
152 
    flag = temp1 == 0;
153 1506 nogj 
    if(flag)
154 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
155 
    else
156 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
157 706 markom 
  }
158 
}
159 
INSTRUCTION (l_or) {
160 1350 nogj 
  uorreg_t temp1;
161 1342 nogj 
  temp1 = PARAM1 | PARAM2;
162 
  set_ov_flag (temp1);
163 
  SET_PARAM0(temp1);
164 706 markom 
}
165 
INSTRUCTION (l_xor) {
166 1350 nogj 
  uorreg_t temp1;
167 1342 nogj 
  temp1 = PARAM1 ^ PARAM2;
168 
  set_ov_flag (temp1);
169 
  SET_PARAM0(temp1);
170 706 markom 
}
171 
INSTRUCTION (l_sub) {
172 1350 nogj 
  orreg_t temp1;
173 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
174 1342 nogj 
  set_ov_flag (temp1);
175 
  SET_PARAM0(temp1);
176 706 markom 
}
177 
/*int mcount = 0;*/
178 
INSTRUCTION (l_mul) {
179 1350 nogj 
  orreg_t temp1;
180 706 markom 
 
181 1350 nogj 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
182 1342 nogj 
  set_ov_flag (temp1);
183 
  SET_PARAM0(temp1);
184 706 markom 
  /*if (!(mcount++ & 1023)) {
185 997 markom 
    PRINTF ("[%i]\n",mcount);
186 706 markom 
    }*/
187 
}
188 
INSTRUCTION (l_div) {
189 1350 nogj 
  orreg_t temp3, temp2, temp1;
190 706 markom 
 
191 1342 nogj 
  temp3 = PARAM2;
192 
  temp2 = PARAM1;
193 706 markom 
  if (temp3)
194 
    temp1 = temp2 / temp3;
195 
  else {
196 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
197 706 markom 
    return;
198 
  }
199 1342 nogj 
  set_ov_flag (temp1);
200 
  SET_PARAM0(temp1);
201 706 markom 
}
202 
INSTRUCTION (l_divu) {
203 1350 nogj 
  uorreg_t temp3, temp2, temp1;
204 706 markom 
 
205 1342 nogj 
  temp3 = PARAM2;
206 
  temp2 = PARAM1;
207 
  if (temp3)
208 
    temp1 = temp2 / temp3;
209 
  else {
210 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
211 1342 nogj 
    return;
212 
  }
213 
  set_ov_flag (temp1);
214 
  SET_PARAM0(temp1);
215 884 markom 
  /* runtime.sim.cycles += 16; */
216 706 markom 
}
217 
INSTRUCTION (l_sll) {
218 1350 nogj 
  uorreg_t temp1;
219 1342 nogj 
 
220 
  temp1 = PARAM1 << PARAM2;
221 
  set_ov_flag (temp1);
222 
  SET_PARAM0(temp1);
223 884 markom 
  /* runtime.sim.cycles += 2; */
224 706 markom 
}
225 
INSTRUCTION (l_sra) {
226 1350 nogj 
  orreg_t temp1;
227 706 markom 
 
228 1350 nogj 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
229 1342 nogj 
  set_ov_flag (temp1);
230 
  SET_PARAM0(temp1);
231 884 markom 
  /* runtime.sim.cycles += 2; */
232 706 markom 
}
233 
INSTRUCTION (l_srl) {
234 1350 nogj 
  uorreg_t temp1;
235 1342 nogj 
  temp1 = PARAM1 >> PARAM2;
236 
  set_ov_flag (temp1);
237 
  SET_PARAM0(temp1);
238 884 markom 
  /* runtime.sim.cycles += 2; */
239 706 markom 
}
240 
INSTRUCTION (l_bf) {
241 
  if (config.bpb.enabled) {
242 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
243 1244 hpanther 
    or1k_mstats.bf[flag][fwd]++;
244 713 markom 
    bpb_update(current->insn_addr, flag);
245 706 markom 
  }
246 
  if (flag) {
247 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
248 706 markom 
    btic_update(pcnext);
249 
    next_delay_insn = 1;
250 
  } else {
251 1432 nogj 
    btic_update(cpu_state.pc);
252 706 markom 
  }
253 
}
254 
INSTRUCTION (l_bnf) {
255 
  if (config.bpb.enabled) {
256 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
257 1244 hpanther 
    or1k_mstats.bnf[!flag][fwd]++;
258 713 markom 
    bpb_update(current->insn_addr, flag == 0);
259 706 markom 
  }
260 
  if (flag == 0) {
261 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
262 706 markom 
    btic_update(pcnext);
263 
    next_delay_insn = 1;
264 
  } else {
265 1432 nogj 
    btic_update(cpu_state.pc);
266 706 markom 
  }
267 
}
268 
INSTRUCTION (l_j) {
269 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
270 706 markom 
  next_delay_insn = 1;
271 
}
272 
INSTRUCTION (l_jal) {
273 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
274 706 markom 
 
275 1432 nogj 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
276 706 markom 
  next_delay_insn = 1;
277 
  if (config.sim.profile) {
278 
    struct label_entry *tmp;
279 1432 nogj 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
280 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
281 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
282 
               tmp->name);
283 706 markom 
    else
284 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
285 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
286 
               cpu_state.pc_delay);
287 706 markom 
  }
288 
}
289 
INSTRUCTION (l_jalr) {
290 1432 nogj 
  cpu_state.pc_delay = PARAM0;
291 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
292 706 markom 
  next_delay_insn = 1;
293 
}
294 
INSTRUCTION (l_jr) {
295 1432 nogj 
  cpu_state.pc_delay = PARAM0;
296 706 markom 
  next_delay_insn = 1;
297 
  if (config.sim.profile)
298 1350 nogj 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
299 1432 nogj 
             cpu_state.pc_delay);
300 706 markom 
}
301 
INSTRUCTION (l_rfe) {
302 
  pcnext = mfspr(SPR_EPCR_BASE);
303 
  mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
304 
}
305 
INSTRUCTION (l_nop) {
306 1350 nogj 
  oraddr_t stackaddr;
307 
  uint32_t k = PARAM0;
308 706 markom 
  switch (k) {
309 
    case NOP_NOP:
310 
      break;
311 
    case NOP_EXIT:
312 1350 nogj 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
313 1343 nogj 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
314 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
315 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
316 
              runtime.cpu.instructions);
317 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
318 
              runtime.sim.cycles - runtime.sim.reset_cycles,
319 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
320 706 markom 
      if (config.debug.gdb_enabled)
321 
        set_stall_state (1);
322 
      else
323 1471 nogj 
        sim_done();
324 706 markom 
      break;
325 1319 phoenix 
    case NOP_CNT_RESET:
326 
      PRINTF("****************** counters reset ******************\n");
327 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
328 
      PRINTF("****************** counters reset ******************\n");
329 
      runtime.sim.reset_cycles = runtime.sim.cycles;
330 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
331 
      break;
332 706 markom 
    case NOP_PRINTF:
333 1350 nogj 
      stackaddr = evalsim_reg(4);
334 
      simprintf(stackaddr, evalsim_reg(3));
335 706 markom 
      debug(5, "simprintf %x\n", stackaddr);
336 
      break;
337 
    case NOP_REPORT:
338 1438 nogj 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
339 706 markom 
    default:
340 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
341 1350 nogj 
      PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
342 
             evalsim_reg(3));
343 706 markom 
      break;
344 
  }
345 
}
346 
INSTRUCTION (l_sfeq) {
347 1342 nogj 
  flag = PARAM0 == PARAM1;
348 1506 nogj 
  if(flag)
349 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
350 
  else
351 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
352 706 markom 
}
353 
INSTRUCTION (l_sfne) {
354 1342 nogj 
  flag = PARAM0 != PARAM1;
355 1506 nogj 
  if(flag)
356 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
357 
  else
358 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
359 706 markom 
}
360 
INSTRUCTION (l_sfgts) {
361 1350 nogj 
  flag = (orreg_t)PARAM0 > (orreg_t)PARAM1;
362 1506 nogj 
  if(flag)
363 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
364 
  else
365 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
366 706 markom 
}
367 
INSTRUCTION (l_sfges) {
368 1350 nogj 
  flag = (orreg_t)PARAM0 >= (orreg_t)PARAM1;
369 1506 nogj 
  if(flag)
370 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
371 
  else
372 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
373 706 markom 
}
374 
INSTRUCTION (l_sflts) {
375 1350 nogj 
  flag = (orreg_t)PARAM0 < (orreg_t)PARAM1;
376 1506 nogj 
  if(flag)
377 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
378 
  else
379 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
380 706 markom 
}
381 
INSTRUCTION (l_sfles) {
382 1350 nogj 
  flag = (orreg_t)PARAM0 <= (orreg_t)PARAM1;
383 1506 nogj 
  if(flag)
384 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
385 
  else
386 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
387 706 markom 
}
388 
INSTRUCTION (l_sfgtu) {
389 1350 nogj 
  flag = PARAM0 > PARAM1;
390 1506 nogj 
  if(flag)
391 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
392 
  else
393 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
394 706 markom 
}
395 
INSTRUCTION (l_sfgeu) {
396 1350 nogj 
  flag = PARAM0 >= PARAM1;
397 1506 nogj 
  if(flag)
398 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
399 
  else
400 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
401 706 markom 
}
402 
INSTRUCTION (l_sfltu) {
403 1350 nogj 
  flag = PARAM0 < PARAM1;
404 1506 nogj 
  if(flag)
405 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
406 
  else
407 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
408 706 markom 
}
409 
INSTRUCTION (l_sfleu) {
410 1350 nogj 
  flag = PARAM0 <= PARAM1;
411 1506 nogj 
  if(flag)
412 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
413 
  else
414 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
415 706 markom 
}
416 
INSTRUCTION (l_extbs) {
417 1350 nogj 
  int8_t x;
418 1342 nogj 
  x = PARAM1;
419 1350 nogj 
  SET_PARAM0((orreg_t)x);
420 706 markom 
}
421 
INSTRUCTION (l_extbz) {
422 1350 nogj 
  uint8_t x;
423 1342 nogj 
  x = PARAM1;
424 1350 nogj 
  SET_PARAM0((uorreg_t)x);
425 706 markom 
}
426 
INSTRUCTION (l_exths) {
427 1350 nogj 
  int16_t x;
428 1342 nogj 
  x = PARAM1;
429 1350 nogj 
  SET_PARAM0((orreg_t)x);
430 706 markom 
}
431 
INSTRUCTION (l_exthz) {
432 1350 nogj 
  uint16_t x;
433 1342 nogj 
  x = PARAM1;
434 1350 nogj 
  SET_PARAM0((uorreg_t)x);
435 706 markom 
}
436 
INSTRUCTION (l_extws) {
437 1350 nogj 
  int32_t x;
438 1342 nogj 
  x = PARAM1;
439 1350 nogj 
  SET_PARAM0((orreg_t)x);
440 706 markom 
}
441 
INSTRUCTION (l_extwz) {
442 1350 nogj 
  uint32_t x;
443 1342 nogj 
  x = PARAM1;
444 1350 nogj 
  SET_PARAM0((uorreg_t)x);
445 706 markom 
}
446 
INSTRUCTION (l_mtspr) {
447 1350 nogj 
  uint16_t regno = PARAM0 + PARAM2;
448 
  uorreg_t value = PARAM1;
449 706 markom 
 
450 
  if (runtime.sim.fspr_log) {
451 1350 nogj 
    fprintf(runtime.sim.fspr_log, "Write to SPR  : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);
452 706 markom 
  }
453 
 
454 
  if (mfspr(SPR_SR) & SPR_SR_SM)
455 
    mtspr(regno, value);
456 
  else {
457 997 markom 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
458 1471 nogj 
    sim_done();
459 706 markom 
  }
460 
}
461 
INSTRUCTION (l_mfspr) {
462 1350 nogj 
  uint16_t regno = PARAM1 + PARAM2;
463 
  uorreg_t value = mfspr(regno);
464 706 markom 
 
465 
  if (runtime.sim.fspr_log) {
466 1350 nogj 
    fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);
467 706 markom 
  }
468 
 
469 
  if (mfspr(SPR_SR) & SPR_SR_SM)
470 1342 nogj 
    SET_PARAM0(value);
471 706 markom 
  else {
472 1342 nogj 
    SET_PARAM0(0);
473 997 markom 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
474 1471 nogj 
    sim_done();
475 706 markom 
  }
476 
}
477 
INSTRUCTION (l_sys) {
478 
  except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
479 
}
480 
INSTRUCTION (l_trap) {
481 
  /* TODO: some SR related code here! */
482 
  except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
483 
}
484 
INSTRUCTION (l_mac) {
485 
  sprword lo, hi;
486 
  LONGEST l;
487 1350 nogj 
  orreg_t x, y;
488 
 
489 706 markom 
  lo = mfspr (SPR_MACLO);
490 
  hi = mfspr (SPR_MACHI);
491 1342 nogj 
  x = PARAM0;
492 
  y = PARAM1;
493 1350 nogj 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
494 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
495 
  l += (LONGEST) x * (LONGEST) y;
496 
 
497 
  /* This implementation is very fast - it needs only one cycle for mac.  */
498 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
499 
  hi = ((LONGEST)l) >> 32;
500 
  mtspr (SPR_MACLO, lo);
501 
  mtspr (SPR_MACHI, hi);
502 1308 phoenix 
  PRINTF ("(%08lx,%08lx)\n", hi, lo);
503 706 markom 
}
504 
INSTRUCTION (l_msb) {
505 
  sprword lo, hi;
506 
  LONGEST l;
507 1350 nogj 
  orreg_t x, y;
508 
 
509 706 markom 
  lo = mfspr (SPR_MACLO);
510 
  hi = mfspr (SPR_MACHI);
511 1342 nogj 
  x = PARAM0;
512 
  y = PARAM1;
513 1350 nogj 
 
514 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
515 
 
516 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
517 1342 nogj 
  l -= x * y;
518 706 markom 
 
519 
  /* This implementation is very fast - it needs only one cycle for msb.  */
520 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
521 
  hi = ((LONGEST)l) >> 32;
522 
  mtspr (SPR_MACLO, lo);
523 
  mtspr (SPR_MACHI, hi);
524 1308 phoenix 
  PRINTF ("(%08lx,%08lx)\n", hi, lo);
525 706 markom 
}
526 
INSTRUCTION (l_macrc) {
527 
  sprword lo, hi;
528 
  LONGEST l;
529 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
530 
  lo =  mfspr (SPR_MACLO);
531 
  hi =  mfspr (SPR_MACHI);
532 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
533 
  l >>= 28;
534 997 markom 
  //PRINTF ("<%08x>\n", (unsigned long)l);
535 1350 nogj 
  SET_PARAM0((orreg_t)l);
536 706 markom 
  mtspr (SPR_MACLO, 0);
537 
  mtspr (SPR_MACHI, 0);
538 
}
539 
INSTRUCTION (l_cmov) {
540 1342 nogj 
  SET_PARAM0(flag ? PARAM1 : PARAM2);
541 706 markom 
}
542 1338 andreje 
INSTRUCTION (l_ff1) {
543 1342 nogj 
  SET_PARAM0(ffs(PARAM1));
544 1338 andreje 
}
545 720 markom 
/******* Floating point instructions *******/
546 
/* Single precision */
547 
INSTRUCTION (lf_add_s) {
548 1350 nogj 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
549 720 markom 
}
550 
INSTRUCTION (lf_div_s) {
551 1350 nogj 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
552 720 markom 
}
553 1303 phoenix 
INSTRUCTION (lf_ftoi_s) {
554 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
555 720 markom 
}
556 
INSTRUCTION (lf_itof_s) {
557 1303 phoenix 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
558 
}
559 720 markom 
INSTRUCTION (lf_madd_s) {
560 1350 nogj 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
561 720 markom 
}
562 
INSTRUCTION (lf_mul_s) {
563 1350 nogj 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
564 720 markom 
}
565 
INSTRUCTION (lf_rem_s) {
566 1342 nogj 
  float temp = (float)PARAM1 / (float)PARAM2;
567 1350 nogj 
  SET_PARAM0(temp - (uint32_t)temp);
568 720 markom 
}
569 
INSTRUCTION (lf_sfeq_s) {
570 1342 nogj 
  flag = (float)PARAM0 == (float)PARAM1;
571 1506 nogj 
  if(flag)
572 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
573 
  else
574 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
575 720 markom 
}
576 
INSTRUCTION (lf_sfge_s) {
577 1342 nogj 
  flag = (float)PARAM0 >= (float)PARAM1;
578 1506 nogj 
  if(flag)
579 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
580 
  else
581 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
582 720 markom 
}
583 
INSTRUCTION (lf_sfgt_s) {
584 1342 nogj 
  flag = (float)PARAM0 > (float)PARAM1;
585 1506 nogj 
  if(flag)
586 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
587 
  else
588 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
589 720 markom 
}
590 
INSTRUCTION (lf_sfle_s) {
591 1342 nogj 
  flag = (float)PARAM0 <= (float)PARAM1;
592 1506 nogj 
  if(flag)
593 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
594 
  else
595 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
596 720 markom 
}
597 
INSTRUCTION (lf_sflt_s) {
598 1342 nogj 
  flag = (float)PARAM0 < (float)PARAM1;
599 1506 nogj 
  if(flag)
600 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
601 
  else
602 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
603 720 markom 
}
604 
INSTRUCTION (lf_sfne_s) {
605 1342 nogj 
  flag = (float)PARAM0 != (float)PARAM1;
606 1506 nogj 
  if(flag)
607 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
608 
  else
609 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
610 720 markom 
}
611 
INSTRUCTION (lf_sub_s) {
612 1350 nogj 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
613 720 markom 
}
614 
 
615 
/******* Custom instructions *******/
616 706 markom 
INSTRUCTION (l_cust1) {
617 713 markom 
  /*int destr = current->insn >> 21;
618 
    int src1r = current->insn >> 15;
619 
    int src2r = current->insn >> 9;*/
620 706 markom 
}
621 
INSTRUCTION (l_cust2) {
622 
}
623 
INSTRUCTION (l_cust3) {
624 
}
625 
INSTRUCTION (l_cust4) {
626 
}

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