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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 1651

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1 706 markom 
/* execute.c -- Instruction specific functions.
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 
                 2000-2002 Marko Mlinar, markom@opencores.org
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
INSTRUCTION (l_add) {
22 1350 nogj 
  orreg_t temp1, temp2, temp3;
23 
  int8_t temp4;
24 706 markom 
 
25 1350 nogj 
  temp2 = (orreg_t)PARAM2;
26 
  temp3 = (orreg_t)PARAM1;
27 1170 csanchez 
  temp1 = temp2 + temp3;
28 1342 nogj 
  SET_PARAM0(temp1);
29 706 markom 
  set_ov_flag (temp1);
30 
  if (ARITH_SET_FLAG) {
31 1513 nogj 
    if(!temp1)
32 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
33 
    else
34 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
35 706 markom 
  }
36 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
37 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
38 1170 csanchez 
  else
39 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
40 706 markom 
 
41 
  temp4 = temp1;
42 
  if (temp4 == temp1)
43 1244 hpanther 
    or1k_mstats.byteadd++;
44 706 markom 
}
45 1170 csanchez 
INSTRUCTION (l_addc) {
46 1350 nogj 
  orreg_t temp1, temp2, temp3;
47 
  int8_t temp4;
48 1170 csanchez 
 
49 1350 nogj 
  temp2 = (orreg_t)PARAM2;
50 
  temp3 = (orreg_t)PARAM1;
51 1506 nogj 
  temp1 = temp2 + temp3;
52 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
53 
    temp1++;
54 1342 nogj 
  SET_PARAM0(temp1);
55 1170 csanchez 
  set_ov_flag (temp1);
56 
  if (ARITH_SET_FLAG) {
57 1513 nogj 
    if(!temp1)
58 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
59 
    else
60 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
61 1170 csanchez 
  }
62 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
63 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
64 1170 csanchez 
  else
65 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
66 1170 csanchez 
 
67 
  temp4 = temp1;
68 
  if (temp4 == temp1)
69 1244 hpanther 
    or1k_mstats.byteadd++;
70 1170 csanchez 
}
71 706 markom 
INSTRUCTION (l_sw) {
72 
  int old_cyc = 0;
73 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
74 1342 nogj 
  set_mem32(PARAM0, PARAM1, &breakpoint);
75 706 markom 
  if (config.cpu.sbuf_len) {
76 884 markom 
    int t = runtime.sim.mem_cycles;
77 
    runtime.sim.mem_cycles = old_cyc;
78 706 markom 
    sbuf_store (t - old_cyc);
79 
  }
80 
}
81 
INSTRUCTION (l_sb) {
82 
  int old_cyc = 0;
83 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
84 1342 nogj 
  set_mem8(PARAM0, PARAM1, &breakpoint);
85 706 markom 
  if (config.cpu.sbuf_len) {
86 884 markom 
    int t = runtime.sim.mem_cycles;
87 
    runtime.sim.mem_cycles = old_cyc;
88 706 markom 
    sbuf_store (t- old_cyc);
89 
  }
90 
}
91 
INSTRUCTION (l_sh) {
92 
  int old_cyc = 0;
93 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
94 1342 nogj 
  set_mem16(PARAM0, PARAM1, &breakpoint);
95 706 markom 
  if (config.cpu.sbuf_len) {
96 884 markom 
    int t = runtime.sim.mem_cycles;
97 
    runtime.sim.mem_cycles = old_cyc;
98 706 markom 
    sbuf_store (t - old_cyc);
99 
  }
100 
}
101 
INSTRUCTION (l_lwz) {
102 1350 nogj 
  uint32_t val;
103 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
104 1342 nogj 
  val = eval_mem32(PARAM1, &breakpoint);
105 706 markom 
  /* If eval operand produced exception don't set anything */
106 1386 nogj 
  if (!except_pending)
107 1342 nogj 
    SET_PARAM0(val);
108 706 markom 
}
109 
INSTRUCTION (l_lbs) {
110 1350 nogj 
  int8_t val;
111 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
112 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
113 706 markom 
  /* If eval opreand produced exception don't set anything */
114 1386 nogj 
  if (!except_pending)
115 1342 nogj 
    SET_PARAM0(val);
116 706 markom 
}
117 
INSTRUCTION (l_lbz) {
118 1350 nogj 
  uint8_t val;
119 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
120 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
121 706 markom 
  /* If eval opreand produced exception don't set anything */
122 1386 nogj 
  if (!except_pending)
123 1342 nogj 
    SET_PARAM0(val);
124 706 markom 
}
125 
INSTRUCTION (l_lhs) {
126 1350 nogj 
  int16_t val;
127 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
128 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
129 706 markom 
  /* If eval opreand produced exception don't set anything */
130 1386 nogj 
  if (!except_pending)
131 1342 nogj 
    SET_PARAM0(val);
132 706 markom 
}
133 
INSTRUCTION (l_lhz) {
134 1350 nogj 
  uint16_t val;
135 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
136 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
137 706 markom 
  /* If eval opreand produced exception don't set anything */
138 1386 nogj 
  if (!except_pending)
139 1342 nogj 
    SET_PARAM0(val);
140 706 markom 
}
141 
INSTRUCTION (l_movhi) {
142 1342 nogj 
  SET_PARAM0(PARAM1 << 16);
143 706 markom 
}
144 
INSTRUCTION (l_and) {
145 1350 nogj 
  uorreg_t temp1;
146 1342 nogj 
  temp1 = PARAM1 & PARAM2;
147 
  set_ov_flag (temp1);
148 
  SET_PARAM0(temp1);
149 706 markom 
  if (ARITH_SET_FLAG) {
150 1513 nogj 
    if(!temp1)
151 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
152 
    else
153 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
154 706 markom 
  }
155 
}
156 
INSTRUCTION (l_or) {
157 1350 nogj 
  uorreg_t temp1;
158 1342 nogj 
  temp1 = PARAM1 | PARAM2;
159 
  set_ov_flag (temp1);
160 
  SET_PARAM0(temp1);
161 706 markom 
}
162 
INSTRUCTION (l_xor) {
163 1350 nogj 
  uorreg_t temp1;
164 1342 nogj 
  temp1 = PARAM1 ^ PARAM2;
165 
  set_ov_flag (temp1);
166 
  SET_PARAM0(temp1);
167 706 markom 
}
168 
INSTRUCTION (l_sub) {
169 1350 nogj 
  orreg_t temp1;
170 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
171 1342 nogj 
  set_ov_flag (temp1);
172 
  SET_PARAM0(temp1);
173 706 markom 
}
174 
/*int mcount = 0;*/
175 
INSTRUCTION (l_mul) {
176 1350 nogj 
  orreg_t temp1;
177 706 markom 
 
178 1350 nogj 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
179 1342 nogj 
  set_ov_flag (temp1);
180 
  SET_PARAM0(temp1);
181 706 markom 
  /*if (!(mcount++ & 1023)) {
182 997 markom 
    PRINTF ("[%i]\n",mcount);
183 706 markom 
    }*/
184 
}
185 
INSTRUCTION (l_div) {
186 1350 nogj 
  orreg_t temp3, temp2, temp1;
187 706 markom 
 
188 1342 nogj 
  temp3 = PARAM2;
189 
  temp2 = PARAM1;
190 706 markom 
  if (temp3)
191 
    temp1 = temp2 / temp3;
192 
  else {
193 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
194 706 markom 
    return;
195 
  }
196 1342 nogj 
  set_ov_flag (temp1);
197 
  SET_PARAM0(temp1);
198 706 markom 
}
199 
INSTRUCTION (l_divu) {
200 1350 nogj 
  uorreg_t temp3, temp2, temp1;
201 706 markom 
 
202 1342 nogj 
  temp3 = PARAM2;
203 
  temp2 = PARAM1;
204 
  if (temp3)
205 
    temp1 = temp2 / temp3;
206 
  else {
207 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
208 1342 nogj 
    return;
209 
  }
210 
  set_ov_flag (temp1);
211 
  SET_PARAM0(temp1);
212 884 markom 
  /* runtime.sim.cycles += 16; */
213 706 markom 
}
214 
INSTRUCTION (l_sll) {
215 1350 nogj 
  uorreg_t temp1;
216 1342 nogj 
 
217 
  temp1 = PARAM1 << PARAM2;
218 
  set_ov_flag (temp1);
219 
  SET_PARAM0(temp1);
220 884 markom 
  /* runtime.sim.cycles += 2; */
221 706 markom 
}
222 
INSTRUCTION (l_sra) {
223 1350 nogj 
  orreg_t temp1;
224 706 markom 
 
225 1350 nogj 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
226 1342 nogj 
  set_ov_flag (temp1);
227 
  SET_PARAM0(temp1);
228 884 markom 
  /* runtime.sim.cycles += 2; */
229 706 markom 
}
230 
INSTRUCTION (l_srl) {
231 1350 nogj 
  uorreg_t temp1;
232 1342 nogj 
  temp1 = PARAM1 >> PARAM2;
233 
  set_ov_flag (temp1);
234 
  SET_PARAM0(temp1);
235 884 markom 
  /* runtime.sim.cycles += 2; */
236 706 markom 
}
237 
INSTRUCTION (l_bf) {
238 
  if (config.bpb.enabled) {
239 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
240 1513 nogj 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
241 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
242 706 markom 
  }
243 1513 nogj 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
244 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
245 706 markom 
    btic_update(pcnext);
246 
    next_delay_insn = 1;
247 
  } else {
248 1432 nogj 
    btic_update(cpu_state.pc);
249 706 markom 
  }
250 
}
251 
INSTRUCTION (l_bnf) {
252 
  if (config.bpb.enabled) {
253 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
254 1513 nogj 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
255 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
256 706 markom 
  }
257 1513 nogj 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
258 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
259 706 markom 
    btic_update(pcnext);
260 
    next_delay_insn = 1;
261 
  } else {
262 1432 nogj 
    btic_update(cpu_state.pc);
263 706 markom 
  }
264 
}
265 
INSTRUCTION (l_j) {
266 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
267 706 markom 
  next_delay_insn = 1;
268 
}
269 
INSTRUCTION (l_jal) {
270 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
271 706 markom 
 
272 1432 nogj 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
273 706 markom 
  next_delay_insn = 1;
274 
  if (config.sim.profile) {
275 
    struct label_entry *tmp;
276 1432 nogj 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
277 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
278 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
279 
               tmp->name);
280 706 markom 
    else
281 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
282 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
283 
               cpu_state.pc_delay);
284 706 markom 
  }
285 
}
286 
INSTRUCTION (l_jalr) {
287 1432 nogj 
  cpu_state.pc_delay = PARAM0;
288 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
289 706 markom 
  next_delay_insn = 1;
290 
}
291 
INSTRUCTION (l_jr) {
292 1432 nogj 
  cpu_state.pc_delay = PARAM0;
293 706 markom 
  next_delay_insn = 1;
294 
  if (config.sim.profile)
295 1350 nogj 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
296 1432 nogj 
             cpu_state.pc_delay);
297 706 markom 
}
298 
INSTRUCTION (l_rfe) {
299 1508 nogj 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
300 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
301 706 markom 
}
302 
INSTRUCTION (l_nop) {
303 1350 nogj 
  oraddr_t stackaddr;
304 
  uint32_t k = PARAM0;
305 706 markom 
  switch (k) {
306 
    case NOP_NOP:
307 
      break;
308 
    case NOP_EXIT:
309 1350 nogj 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
310 1343 nogj 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
311 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
312 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
313 
              runtime.cpu.instructions);
314 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
315 
              runtime.sim.cycles - runtime.sim.reset_cycles,
316 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
317 706 markom 
      if (config.debug.gdb_enabled)
318 
        set_stall_state (1);
319 
      else
320 1471 nogj 
        sim_done();
321 706 markom 
      break;
322 1319 phoenix 
    case NOP_CNT_RESET:
323 
      PRINTF("****************** counters reset ******************\n");
324 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
325 
      PRINTF("****************** counters reset ******************\n");
326 
      runtime.sim.reset_cycles = runtime.sim.cycles;
327 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
328 
      break;
329 706 markom 
    case NOP_PRINTF:
330 1350 nogj 
      stackaddr = evalsim_reg(4);
331 
      simprintf(stackaddr, evalsim_reg(3));
332 706 markom 
      break;
333 
    case NOP_REPORT:
334 1438 nogj 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
335 706 markom 
    default:
336 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
337 1350 nogj 
      PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
338 
             evalsim_reg(3));
339 706 markom 
      break;
340 
  }
341 
}
342 
INSTRUCTION (l_sfeq) {
343 1513 nogj 
  if(PARAM0 == PARAM1)
344 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
345 
  else
346 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
347 706 markom 
}
348 
INSTRUCTION (l_sfne) {
349 1513 nogj 
  if(PARAM0 != PARAM1)
350 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
351 
  else
352 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
353 706 markom 
}
354 
INSTRUCTION (l_sfgts) {
355 1513 nogj 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
356 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
357 
  else
358 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
359 706 markom 
}
360 
INSTRUCTION (l_sfges) {
361 1513 nogj 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
362 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
363 
  else
364 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
365 706 markom 
}
366 
INSTRUCTION (l_sflts) {
367 1513 nogj 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
368 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
369 
  else
370 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
371 706 markom 
}
372 
INSTRUCTION (l_sfles) {
373 1513 nogj 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
374 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
375 
  else
376 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
377 706 markom 
}
378 
INSTRUCTION (l_sfgtu) {
379 1513 nogj 
  if(PARAM0 > PARAM1)
380 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
381 
  else
382 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
383 706 markom 
}
384 
INSTRUCTION (l_sfgeu) {
385 1513 nogj 
  if(PARAM0 >= PARAM1)
386 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
387 
  else
388 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
389 706 markom 
}
390 
INSTRUCTION (l_sfltu) {
391 1513 nogj 
  if(PARAM0 < PARAM1)
392 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
393 
  else
394 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
395 706 markom 
}
396 
INSTRUCTION (l_sfleu) {
397 1513 nogj 
  if(PARAM0 <= PARAM1)
398 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
399 
  else
400 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
401 706 markom 
}
402 
INSTRUCTION (l_extbs) {
403 1350 nogj 
  int8_t x;
404 1342 nogj 
  x = PARAM1;
405 1350 nogj 
  SET_PARAM0((orreg_t)x);
406 706 markom 
}
407 
INSTRUCTION (l_extbz) {
408 1350 nogj 
  uint8_t x;
409 1342 nogj 
  x = PARAM1;
410 1350 nogj 
  SET_PARAM0((uorreg_t)x);
411 706 markom 
}
412 
INSTRUCTION (l_exths) {
413 1350 nogj 
  int16_t x;
414 1342 nogj 
  x = PARAM1;
415 1350 nogj 
  SET_PARAM0((orreg_t)x);
416 706 markom 
}
417 
INSTRUCTION (l_exthz) {
418 1350 nogj 
  uint16_t x;
419 1342 nogj 
  x = PARAM1;
420 1350 nogj 
  SET_PARAM0((uorreg_t)x);
421 706 markom 
}
422 
INSTRUCTION (l_extws) {
423 1350 nogj 
  int32_t x;
424 1342 nogj 
  x = PARAM1;
425 1350 nogj 
  SET_PARAM0((orreg_t)x);
426 706 markom 
}
427 
INSTRUCTION (l_extwz) {
428 1350 nogj 
  uint32_t x;
429 1342 nogj 
  x = PARAM1;
430 1350 nogj 
  SET_PARAM0((uorreg_t)x);
431 706 markom 
}
432 
INSTRUCTION (l_mtspr) {
433 1350 nogj 
  uint16_t regno = PARAM0 + PARAM2;
434 
  uorreg_t value = PARAM1;
435 706 markom 
 
436 1508 nogj 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
437 706 markom 
    mtspr(regno, value);
438 
  else {
439 997 markom 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
440 1471 nogj 
    sim_done();
441 706 markom 
  }
442 
}
443 
INSTRUCTION (l_mfspr) {
444 1350 nogj 
  uint16_t regno = PARAM1 + PARAM2;
445 
  uorreg_t value = mfspr(regno);
446 706 markom 
 
447 1508 nogj 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
448 1342 nogj 
    SET_PARAM0(value);
449 706 markom 
  else {
450 1342 nogj 
    SET_PARAM0(0);
451 997 markom 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
452 1471 nogj 
    sim_done();
453 706 markom 
  }
454 
}
455 
INSTRUCTION (l_sys) {
456 1508 nogj 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
457 706 markom 
}
458 
INSTRUCTION (l_trap) {
459 
  /* TODO: some SR related code here! */
460 1508 nogj 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
461 706 markom 
}
462 
INSTRUCTION (l_mac) {
463 1508 nogj 
  uorreg_t lo, hi;
464 706 markom 
  LONGEST l;
465 1350 nogj 
  orreg_t x, y;
466 
 
467 1508 nogj 
  lo = cpu_state.sprs[SPR_MACLO];
468 
  hi = cpu_state.sprs[SPR_MACHI];
469 1342 nogj 
  x = PARAM0;
470 
  y = PARAM1;
471 1350 nogj 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
472 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
473 
  l += (LONGEST) x * (LONGEST) y;
474 
 
475 
  /* This implementation is very fast - it needs only one cycle for mac.  */
476 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
477 
  hi = ((LONGEST)l) >> 32;
478 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = lo;
479 
  cpu_state.sprs[SPR_MACHI] = hi;
480 1557 nogj 
  PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo);
481 706 markom 
}
482 
INSTRUCTION (l_msb) {
483 1508 nogj 
  uorreg_t lo, hi;
484 706 markom 
  LONGEST l;
485 1350 nogj 
  orreg_t x, y;
486 
 
487 1508 nogj 
  lo = cpu_state.sprs[SPR_MACLO];
488 
  hi = cpu_state.sprs[SPR_MACHI];
489 1342 nogj 
  x = PARAM0;
490 
  y = PARAM1;
491 1350 nogj 
 
492 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
493 
 
494 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
495 1342 nogj 
  l -= x * y;
496 706 markom 
 
497 
  /* This implementation is very fast - it needs only one cycle for msb.  */
498 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
499 
  hi = ((LONGEST)l) >> 32;
500 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = lo;
501 
  cpu_state.sprs[SPR_MACHI] = hi;
502 1557 nogj 
  PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo);
503 706 markom 
}
504 
INSTRUCTION (l_macrc) {
505 1508 nogj 
  uorreg_t lo, hi;
506 706 markom 
  LONGEST l;
507 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
508 1508 nogj 
  lo =  cpu_state.sprs[SPR_MACLO];
509 
  hi =  cpu_state.sprs[SPR_MACHI];
510 706 markom 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
511 
  l >>= 28;
512 997 markom 
  //PRINTF ("<%08x>\n", (unsigned long)l);
513 1350 nogj 
  SET_PARAM0((orreg_t)l);
514 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = 0;
515 
  cpu_state.sprs[SPR_MACHI] = 0;
516 706 markom 
}
517 
INSTRUCTION (l_cmov) {
518 1513 nogj 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
519 706 markom 
}
520 1338 andreje 
INSTRUCTION (l_ff1) {
521 1342 nogj 
  SET_PARAM0(ffs(PARAM1));
522 1338 andreje 
}
523 720 markom 
/******* Floating point instructions *******/
524 
/* Single precision */
525 
INSTRUCTION (lf_add_s) {
526 1350 nogj 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
527 720 markom 
}
528 
INSTRUCTION (lf_div_s) {
529 1350 nogj 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
530 720 markom 
}
531 1303 phoenix 
INSTRUCTION (lf_ftoi_s) {
532 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
533 720 markom 
}
534 
INSTRUCTION (lf_itof_s) {
535 1303 phoenix 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
536 
}
537 720 markom 
INSTRUCTION (lf_madd_s) {
538 1350 nogj 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
539 720 markom 
}
540 
INSTRUCTION (lf_mul_s) {
541 1350 nogj 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
542 720 markom 
}
543 
INSTRUCTION (lf_rem_s) {
544 1342 nogj 
  float temp = (float)PARAM1 / (float)PARAM2;
545 1350 nogj 
  SET_PARAM0(temp - (uint32_t)temp);
546 720 markom 
}
547 
INSTRUCTION (lf_sfeq_s) {
548 1513 nogj 
  if((float)PARAM0 == (float)PARAM1)
549 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
550 
  else
551 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
552 720 markom 
}
553 
INSTRUCTION (lf_sfge_s) {
554 1513 nogj 
  if((float)PARAM0 >= (float)PARAM1)
555 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
556 
  else
557 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
558 720 markom 
}
559 
INSTRUCTION (lf_sfgt_s) {
560 1513 nogj 
  if((float)PARAM0 > (float)PARAM1)
561 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
562 
  else
563 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
564 720 markom 
}
565 
INSTRUCTION (lf_sfle_s) {
566 1513 nogj 
  if((float)PARAM0 <= (float)PARAM1)
567 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
568 
  else
569 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
570 720 markom 
}
571 
INSTRUCTION (lf_sflt_s) {
572 1513 nogj 
  if((float)PARAM0 < (float)PARAM1)
573 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
574 
  else
575 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
576 720 markom 
}
577 
INSTRUCTION (lf_sfne_s) {
578 1513 nogj 
  if((float)PARAM0 != (float)PARAM1)
579 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
580 
  else
581 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
582 720 markom 
}
583 
INSTRUCTION (lf_sub_s) {
584 1350 nogj 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
585 720 markom 
}
586 
 
587 
/******* Custom instructions *******/
588 706 markom 
INSTRUCTION (l_cust1) {
589 713 markom 
  /*int destr = current->insn >> 21;
590 
    int src1r = current->insn >> 15;
591 
    int src2r = current->insn >> 9;*/
592 706 markom 
}
593 
INSTRUCTION (l_cust2) {
594 
}
595 
INSTRUCTION (l_cust3) {
596 
}
597 
INSTRUCTION (l_cust4) {
598 
}

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