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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 1744

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Line No. Rev Author Line
1 706 markom 
/* execute.c -- Instruction specific functions.
2 1744 jeremybenn 
 
3 706 markom 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 1744 jeremybenn 
   Copyright (C) 2008 Embecosm Limited
6 
 
7 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
23 706 markom 
 
24 
 
25 
INSTRUCTION (l_add) {
26 1350 nogj 
  orreg_t temp1, temp2, temp3;
27 
  int8_t temp4;
28 706 markom 
 
29 1350 nogj 
  temp2 = (orreg_t)PARAM2;
30 
  temp3 = (orreg_t)PARAM1;
31 1170 csanchez 
  temp1 = temp2 + temp3;
32 1342 nogj 
  SET_PARAM0(temp1);
33 706 markom 
  set_ov_flag (temp1);
34 
  if (ARITH_SET_FLAG) {
35 1513 nogj 
    if(!temp1)
36 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
37 
    else
38 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
39 706 markom 
  }
40 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
41 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
42 1170 csanchez 
  else
43 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
44 706 markom 
 
45 
  temp4 = temp1;
46 
  if (temp4 == temp1)
47 1244 hpanther 
    or1k_mstats.byteadd++;
48 706 markom 
}
49 1170 csanchez 
INSTRUCTION (l_addc) {
50 1350 nogj 
  orreg_t temp1, temp2, temp3;
51 
  int8_t temp4;
52 1170 csanchez 
 
53 1350 nogj 
  temp2 = (orreg_t)PARAM2;
54 
  temp3 = (orreg_t)PARAM1;
55 1506 nogj 
  temp1 = temp2 + temp3;
56 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
57 
    temp1++;
58 1342 nogj 
  SET_PARAM0(temp1);
59 1170 csanchez 
  set_ov_flag (temp1);
60 
  if (ARITH_SET_FLAG) {
61 1513 nogj 
    if(!temp1)
62 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
63 
    else
64 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
65 1170 csanchez 
  }
66 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
67 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
68 1170 csanchez 
  else
69 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
70 1170 csanchez 
 
71 
  temp4 = temp1;
72 
  if (temp4 == temp1)
73 1244 hpanther 
    or1k_mstats.byteadd++;
74 1170 csanchez 
}
75 706 markom 
INSTRUCTION (l_sw) {
76 
  int old_cyc = 0;
77 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
78 1342 nogj 
  set_mem32(PARAM0, PARAM1, &breakpoint);
79 706 markom 
  if (config.cpu.sbuf_len) {
80 884 markom 
    int t = runtime.sim.mem_cycles;
81 
    runtime.sim.mem_cycles = old_cyc;
82 706 markom 
    sbuf_store (t - old_cyc);
83 
  }
84 
}
85 
INSTRUCTION (l_sb) {
86 
  int old_cyc = 0;
87 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
88 1342 nogj 
  set_mem8(PARAM0, PARAM1, &breakpoint);
89 706 markom 
  if (config.cpu.sbuf_len) {
90 884 markom 
    int t = runtime.sim.mem_cycles;
91 
    runtime.sim.mem_cycles = old_cyc;
92 706 markom 
    sbuf_store (t- old_cyc);
93 
  }
94 
}
95 
INSTRUCTION (l_sh) {
96 
  int old_cyc = 0;
97 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
98 1342 nogj 
  set_mem16(PARAM0, PARAM1, &breakpoint);
99 706 markom 
  if (config.cpu.sbuf_len) {
100 884 markom 
    int t = runtime.sim.mem_cycles;
101 
    runtime.sim.mem_cycles = old_cyc;
102 706 markom 
    sbuf_store (t - old_cyc);
103 
  }
104 
}
105 
INSTRUCTION (l_lwz) {
106 1350 nogj 
  uint32_t val;
107 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
108 1342 nogj 
  val = eval_mem32(PARAM1, &breakpoint);
109 1744 jeremybenn 
  /* If eval operand produced exception don't set anything. JPB changed to
110 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
111 
  if (!(except_pending || breakpoint))
112 1342 nogj 
    SET_PARAM0(val);
113 706 markom 
}
114 
INSTRUCTION (l_lbs) {
115 1350 nogj 
  int8_t val;
116 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
117 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
118 1744 jeremybenn 
  /* If eval operand produced exception don't set anything. JPB changed to
119 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
120 
  if (!(except_pending || breakpoint))
121 1342 nogj 
    SET_PARAM0(val);
122 706 markom 
}
123 
INSTRUCTION (l_lbz) {
124 1350 nogj 
  uint8_t val;
125 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
126 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
127 1744 jeremybenn 
  /* If eval operand produced exception don't set anything. JPB changed to
128 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
129 
  if (!(except_pending || breakpoint))
130 1342 nogj 
    SET_PARAM0(val);
131 706 markom 
}
132 
INSTRUCTION (l_lhs) {
133 1350 nogj 
  int16_t val;
134 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
135 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
136 1744 jeremybenn 
  /* If eval operand produced exception don't set anything. JPB changed to
137 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
138 
  if (!(except_pending || breakpoint))
139 1342 nogj 
    SET_PARAM0(val);
140 706 markom 
}
141 
INSTRUCTION (l_lhz) {
142 1350 nogj 
  uint16_t val;
143 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
144 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
145 1744 jeremybenn 
  /* If eval operand produced exception don't set anything. JPB changed to
146 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
147 
  if (!(except_pending || breakpoint))
148 1342 nogj 
    SET_PARAM0(val);
149 706 markom 
}
150 
INSTRUCTION (l_movhi) {
151 1342 nogj 
  SET_PARAM0(PARAM1 << 16);
152 706 markom 
}
153 
INSTRUCTION (l_and) {
154 1350 nogj 
  uorreg_t temp1;
155 1342 nogj 
  temp1 = PARAM1 & PARAM2;
156 
  set_ov_flag (temp1);
157 
  SET_PARAM0(temp1);
158 706 markom 
  if (ARITH_SET_FLAG) {
159 1513 nogj 
    if(!temp1)
160 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
161 
    else
162 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
163 706 markom 
  }
164 
}
165 
INSTRUCTION (l_or) {
166 1350 nogj 
  uorreg_t temp1;
167 1342 nogj 
  temp1 = PARAM1 | PARAM2;
168 
  set_ov_flag (temp1);
169 
  SET_PARAM0(temp1);
170 706 markom 
}
171 
INSTRUCTION (l_xor) {
172 1350 nogj 
  uorreg_t temp1;
173 1342 nogj 
  temp1 = PARAM1 ^ PARAM2;
174 
  set_ov_flag (temp1);
175 
  SET_PARAM0(temp1);
176 706 markom 
}
177 
INSTRUCTION (l_sub) {
178 1350 nogj 
  orreg_t temp1;
179 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
180 1342 nogj 
  set_ov_flag (temp1);
181 
  SET_PARAM0(temp1);
182 706 markom 
}
183 
/*int mcount = 0;*/
184 
INSTRUCTION (l_mul) {
185 1350 nogj 
  orreg_t temp1;
186 706 markom 
 
187 1350 nogj 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
188 1342 nogj 
  set_ov_flag (temp1);
189 
  SET_PARAM0(temp1);
190 706 markom 
  /*if (!(mcount++ & 1023)) {
191 997 markom 
    PRINTF ("[%i]\n",mcount);
192 706 markom 
    }*/
193 
}
194 
INSTRUCTION (l_div) {
195 1350 nogj 
  orreg_t temp3, temp2, temp1;
196 706 markom 
 
197 1342 nogj 
  temp3 = PARAM2;
198 
  temp2 = PARAM1;
199 706 markom 
  if (temp3)
200 
    temp1 = temp2 / temp3;
201 
  else {
202 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
203 706 markom 
    return;
204 
  }
205 1342 nogj 
  set_ov_flag (temp1);
206 
  SET_PARAM0(temp1);
207 706 markom 
}
208 
INSTRUCTION (l_divu) {
209 1350 nogj 
  uorreg_t temp3, temp2, temp1;
210 706 markom 
 
211 1342 nogj 
  temp3 = PARAM2;
212 
  temp2 = PARAM1;
213 
  if (temp3)
214 
    temp1 = temp2 / temp3;
215 
  else {
216 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
217 1342 nogj 
    return;
218 
  }
219 
  set_ov_flag (temp1);
220 
  SET_PARAM0(temp1);
221 884 markom 
  /* runtime.sim.cycles += 16; */
222 706 markom 
}
223 
INSTRUCTION (l_sll) {
224 1350 nogj 
  uorreg_t temp1;
225 1342 nogj 
 
226 
  temp1 = PARAM1 << PARAM2;
227 
  set_ov_flag (temp1);
228 
  SET_PARAM0(temp1);
229 884 markom 
  /* runtime.sim.cycles += 2; */
230 706 markom 
}
231 
INSTRUCTION (l_sra) {
232 1350 nogj 
  orreg_t temp1;
233 706 markom 
 
234 1350 nogj 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
235 1342 nogj 
  set_ov_flag (temp1);
236 
  SET_PARAM0(temp1);
237 884 markom 
  /* runtime.sim.cycles += 2; */
238 706 markom 
}
239 
INSTRUCTION (l_srl) {
240 1350 nogj 
  uorreg_t temp1;
241 1342 nogj 
  temp1 = PARAM1 >> PARAM2;
242 
  set_ov_flag (temp1);
243 
  SET_PARAM0(temp1);
244 884 markom 
  /* runtime.sim.cycles += 2; */
245 706 markom 
}
246 
INSTRUCTION (l_bf) {
247 
  if (config.bpb.enabled) {
248 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
249 1513 nogj 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
250 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
251 706 markom 
  }
252 1513 nogj 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
253 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
254 706 markom 
    btic_update(pcnext);
255 
    next_delay_insn = 1;
256 
  } else {
257 1432 nogj 
    btic_update(cpu_state.pc);
258 706 markom 
  }
259 
}
260 
INSTRUCTION (l_bnf) {
261 
  if (config.bpb.enabled) {
262 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
263 1513 nogj 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
264 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
265 706 markom 
  }
266 1513 nogj 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
267 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
268 706 markom 
    btic_update(pcnext);
269 
    next_delay_insn = 1;
270 
  } else {
271 1432 nogj 
    btic_update(cpu_state.pc);
272 706 markom 
  }
273 
}
274 
INSTRUCTION (l_j) {
275 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
276 706 markom 
  next_delay_insn = 1;
277 
}
278 
INSTRUCTION (l_jal) {
279 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
280 706 markom 
 
281 1432 nogj 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
282 706 markom 
  next_delay_insn = 1;
283 
  if (config.sim.profile) {
284 
    struct label_entry *tmp;
285 1432 nogj 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
286 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
287 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
288 
               tmp->name);
289 706 markom 
    else
290 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
291 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
292 
               cpu_state.pc_delay);
293 706 markom 
  }
294 
}
295 
INSTRUCTION (l_jalr) {
296 1432 nogj 
  cpu_state.pc_delay = PARAM0;
297 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
298 706 markom 
  next_delay_insn = 1;
299 
}
300 
INSTRUCTION (l_jr) {
301 1432 nogj 
  cpu_state.pc_delay = PARAM0;
302 706 markom 
  next_delay_insn = 1;
303 
  if (config.sim.profile)
304 1350 nogj 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
305 1432 nogj 
             cpu_state.pc_delay);
306 706 markom 
}
307 
INSTRUCTION (l_rfe) {
308 1508 nogj 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
309 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
310 706 markom 
}
311 
INSTRUCTION (l_nop) {
312 1350 nogj 
  oraddr_t stackaddr;
313 
  uint32_t k = PARAM0;
314 706 markom 
  switch (k) {
315 
    case NOP_NOP:
316 
      break;
317 
    case NOP_EXIT:
318 1350 nogj 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
319 1343 nogj 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
320 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
321 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
322 
              runtime.cpu.instructions);
323 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
324 
              runtime.sim.cycles - runtime.sim.reset_cycles,
325 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
326 706 markom 
      if (config.debug.gdb_enabled)
327 
        set_stall_state (1);
328 
      else
329 1471 nogj 
        sim_done();
330 706 markom 
      break;
331 1319 phoenix 
    case NOP_CNT_RESET:
332 
      PRINTF("****************** counters reset ******************\n");
333 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
334 
      PRINTF("****************** counters reset ******************\n");
335 
      runtime.sim.reset_cycles = runtime.sim.cycles;
336 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
337 
      break;
338 706 markom 
    case NOP_PRINTF:
339 1350 nogj 
      stackaddr = evalsim_reg(4);
340 
      simprintf(stackaddr, evalsim_reg(3));
341 706 markom 
      break;
342 1744 jeremybenn 
    case NOP_PUTC:              /*JPB */
343 
      printf( "%c", evalsim_reg( 3 ));
344 
      fflush( stdout );
345 
      break;
346 706 markom 
    case NOP_REPORT:
347 1438 nogj 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
348 706 markom 
    default:
349 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
350 1350 nogj 
      PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
351 
             evalsim_reg(3));
352 706 markom 
      break;
353 
  }
354 
}
355 
INSTRUCTION (l_sfeq) {
356 1513 nogj 
  if(PARAM0 == PARAM1)
357 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
358 
  else
359 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
360 706 markom 
}
361 
INSTRUCTION (l_sfne) {
362 1513 nogj 
  if(PARAM0 != PARAM1)
363 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
364 
  else
365 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
366 706 markom 
}
367 
INSTRUCTION (l_sfgts) {
368 1513 nogj 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
369 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
370 
  else
371 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
372 706 markom 
}
373 
INSTRUCTION (l_sfges) {
374 1513 nogj 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
375 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
376 
  else
377 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
378 706 markom 
}
379 
INSTRUCTION (l_sflts) {
380 1513 nogj 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
381 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
382 
  else
383 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
384 706 markom 
}
385 
INSTRUCTION (l_sfles) {
386 1513 nogj 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
387 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
388 
  else
389 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
390 706 markom 
}
391 
INSTRUCTION (l_sfgtu) {
392 1513 nogj 
  if(PARAM0 > PARAM1)
393 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
394 
  else
395 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
396 706 markom 
}
397 
INSTRUCTION (l_sfgeu) {
398 1513 nogj 
  if(PARAM0 >= PARAM1)
399 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
400 
  else
401 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
402 706 markom 
}
403 
INSTRUCTION (l_sfltu) {
404 1513 nogj 
  if(PARAM0 < PARAM1)
405 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
406 
  else
407 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
408 706 markom 
}
409 
INSTRUCTION (l_sfleu) {
410 1513 nogj 
  if(PARAM0 <= PARAM1)
411 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
412 
  else
413 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
414 706 markom 
}
415 
INSTRUCTION (l_extbs) {
416 1350 nogj 
  int8_t x;
417 1342 nogj 
  x = PARAM1;
418 1350 nogj 
  SET_PARAM0((orreg_t)x);
419 706 markom 
}
420 
INSTRUCTION (l_extbz) {
421 1350 nogj 
  uint8_t x;
422 1342 nogj 
  x = PARAM1;
423 1350 nogj 
  SET_PARAM0((uorreg_t)x);
424 706 markom 
}
425 
INSTRUCTION (l_exths) {
426 1350 nogj 
  int16_t x;
427 1342 nogj 
  x = PARAM1;
428 1350 nogj 
  SET_PARAM0((orreg_t)x);
429 706 markom 
}
430 
INSTRUCTION (l_exthz) {
431 1350 nogj 
  uint16_t x;
432 1342 nogj 
  x = PARAM1;
433 1350 nogj 
  SET_PARAM0((uorreg_t)x);
434 706 markom 
}
435 
INSTRUCTION (l_extws) {
436 1350 nogj 
  int32_t x;
437 1342 nogj 
  x = PARAM1;
438 1350 nogj 
  SET_PARAM0((orreg_t)x);
439 706 markom 
}
440 
INSTRUCTION (l_extwz) {
441 1350 nogj 
  uint32_t x;
442 1342 nogj 
  x = PARAM1;
443 1350 nogj 
  SET_PARAM0((uorreg_t)x);
444 706 markom 
}
445 
INSTRUCTION (l_mtspr) {
446 1350 nogj 
  uint16_t regno = PARAM0 + PARAM2;
447 
  uorreg_t value = PARAM1;
448 706 markom 
 
449 1508 nogj 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
450 706 markom 
    mtspr(regno, value);
451 
  else {
452 997 markom 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
453 1471 nogj 
    sim_done();
454 706 markom 
  }
455 
}
456 
INSTRUCTION (l_mfspr) {
457 1350 nogj 
  uint16_t regno = PARAM1 + PARAM2;
458 
  uorreg_t value = mfspr(regno);
459 706 markom 
 
460 1508 nogj 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
461 1342 nogj 
    SET_PARAM0(value);
462 706 markom 
  else {
463 1342 nogj 
    SET_PARAM0(0);
464 997 markom 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
465 1471 nogj 
    sim_done();
466 706 markom 
  }
467 
}
468 
INSTRUCTION (l_sys) {
469 1508 nogj 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
470 706 markom 
}
471 
INSTRUCTION (l_trap) {
472 
  /* TODO: some SR related code here! */
473 1508 nogj 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
474 706 markom 
}
475 
INSTRUCTION (l_mac) {
476 1508 nogj 
  uorreg_t lo, hi;
477 706 markom 
  LONGEST l;
478 1350 nogj 
  orreg_t x, y;
479 
 
480 1508 nogj 
  lo = cpu_state.sprs[SPR_MACLO];
481 
  hi = cpu_state.sprs[SPR_MACHI];
482 1342 nogj 
  x = PARAM0;
483 
  y = PARAM1;
484 1350 nogj 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
485 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
486 
  l += (LONGEST) x * (LONGEST) y;
487 
 
488 
  /* This implementation is very fast - it needs only one cycle for mac.  */
489 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
490 
  hi = ((LONGEST)l) >> 32;
491 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = lo;
492 
  cpu_state.sprs[SPR_MACHI] = hi;
493 1557 nogj 
  PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo);
494 706 markom 
}
495 
INSTRUCTION (l_msb) {
496 1508 nogj 
  uorreg_t lo, hi;
497 706 markom 
  LONGEST l;
498 1350 nogj 
  orreg_t x, y;
499 
 
500 1508 nogj 
  lo = cpu_state.sprs[SPR_MACLO];
501 
  hi = cpu_state.sprs[SPR_MACHI];
502 1342 nogj 
  x = PARAM0;
503 
  y = PARAM1;
504 1350 nogj 
 
505 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
506 
 
507 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
508 1342 nogj 
  l -= x * y;
509 706 markom 
 
510 
  /* This implementation is very fast - it needs only one cycle for msb.  */
511 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
512 
  hi = ((LONGEST)l) >> 32;
513 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = lo;
514 
  cpu_state.sprs[SPR_MACHI] = hi;
515 1557 nogj 
  PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo);
516 706 markom 
}
517 
INSTRUCTION (l_macrc) {
518 1508 nogj 
  uorreg_t lo, hi;
519 706 markom 
  LONGEST l;
520 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
521 1508 nogj 
  lo =  cpu_state.sprs[SPR_MACLO];
522 
  hi =  cpu_state.sprs[SPR_MACHI];
523 706 markom 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
524 
  l >>= 28;
525 997 markom 
  //PRINTF ("<%08x>\n", (unsigned long)l);
526 1350 nogj 
  SET_PARAM0((orreg_t)l);
527 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = 0;
528 
  cpu_state.sprs[SPR_MACHI] = 0;
529 706 markom 
}
530 
INSTRUCTION (l_cmov) {
531 1513 nogj 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
532 706 markom 
}
533 1338 andreje 
INSTRUCTION (l_ff1) {
534 1342 nogj 
  SET_PARAM0(ffs(PARAM1));
535 1338 andreje 
}
536 720 markom 
/******* Floating point instructions *******/
537 
/* Single precision */
538 
INSTRUCTION (lf_add_s) {
539 1350 nogj 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
540 720 markom 
}
541 
INSTRUCTION (lf_div_s) {
542 1350 nogj 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
543 720 markom 
}
544 1303 phoenix 
INSTRUCTION (lf_ftoi_s) {
545 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
546 720 markom 
}
547 
INSTRUCTION (lf_itof_s) {
548 1303 phoenix 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
549 
}
550 720 markom 
INSTRUCTION (lf_madd_s) {
551 1350 nogj 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
552 720 markom 
}
553 
INSTRUCTION (lf_mul_s) {
554 1350 nogj 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
555 720 markom 
}
556 
INSTRUCTION (lf_rem_s) {
557 1342 nogj 
  float temp = (float)PARAM1 / (float)PARAM2;
558 1350 nogj 
  SET_PARAM0(temp - (uint32_t)temp);
559 720 markom 
}
560 
INSTRUCTION (lf_sfeq_s) {
561 1513 nogj 
  if((float)PARAM0 == (float)PARAM1)
562 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
563 
  else
564 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
565 720 markom 
}
566 
INSTRUCTION (lf_sfge_s) {
567 1513 nogj 
  if((float)PARAM0 >= (float)PARAM1)
568 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
569 
  else
570 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
571 720 markom 
}
572 
INSTRUCTION (lf_sfgt_s) {
573 1513 nogj 
  if((float)PARAM0 > (float)PARAM1)
574 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
575 
  else
576 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
577 720 markom 
}
578 
INSTRUCTION (lf_sfle_s) {
579 1513 nogj 
  if((float)PARAM0 <= (float)PARAM1)
580 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
581 
  else
582 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
583 720 markom 
}
584 
INSTRUCTION (lf_sflt_s) {
585 1513 nogj 
  if((float)PARAM0 < (float)PARAM1)
586 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
587 
  else
588 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
589 720 markom 
}
590 
INSTRUCTION (lf_sfne_s) {
591 1513 nogj 
  if((float)PARAM0 != (float)PARAM1)
592 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
593 
  else
594 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
595 720 markom 
}
596 
INSTRUCTION (lf_sub_s) {
597 1350 nogj 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
598 720 markom 
}
599 
 
600 
/******* Custom instructions *******/
601 706 markom 
INSTRUCTION (l_cust1) {
602 713 markom 
  /*int destr = current->insn >> 21;
603 
    int src1r = current->insn >> 15;
604 
    int src2r = current->insn >> 9;*/
605 706 markom 
}
606 
INSTRUCTION (l_cust2) {
607 
}
608 
INSTRUCTION (l_cust3) {
609 
}
610 
INSTRUCTION (l_cust4) {
611 
}

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