OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or32/] [op.c] - Blame information for rev 1661

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1452 nogj
/* op.c -- Micro operations for the recompiler
2
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
 
21
#include <stdio.h>
22
#include <stdint.h>
23
#include <stdlib.h>
24
 
25
#include "config.h"
26
 
27
#ifdef HAVE_INTTYPES_H
28
#include <inttypes.h>
29
#endif
30
 
31
#include "port.h"
32
#include "arch.h"
33
#include "spr_defs.h"
34
#include "opcode/or32.h"
35
#include "sim-config.h"
36
#include "except.h"
37
#include "abstract.h"
38
#include "execute.h"
39
#include "sprs.h"
40
#include "sched.h"
41
 
42
#include "op_support.h"
43
 
44
#include "i386_regs.h"
45
 
46
#include "dyn_rec.h"
47
 
48
/* This must be here since the function in op_i386.h use this variable */
49
register struct cpu_state *env asm(CPU_STATE_REG);
50
 
51
#include "op_i386.h"
52
 
53
/*
54 1549 nogj
 * WARNING: Before going of and wildly editing everything in this file remember
55 1452 nogj
 * the following about its contents:
56
 * 1) The `functions' don't EVER return.  In otherwords haveing return state-
57
 *    ments _anywere_ in this file is likely not to work.  This is because
58
 *    dyngen just strips away the ret from the end of the function and just uses
59
 *    the function `body'.  If a ret statement is executed _anyware_ inside the
60
 *    dynamicly generated code, then it is undefined were we shall jump to.
61
 * 2) Because of 1), try not to have overly complicated functions.  In too
62
 *    complicated functions, gcc may decide to generate premature `exits'.  This
63
 *    is what passing the -fno-reorder-blocks command line switch to gcc helps
64
 *    with.  This is ofcourse not desired and is rather flaky as we don't (and
65
 *    can't) control the kind of code that gcc generates: It may work for one
66
 *    and break for another.  The less branches there are the less likely it is
67
 *    that a premature return shall occur.
68
 * 3) If gcc decides that it is going to be a basterd then it will optimise a
69
 *    very simple condition (if/switch) with a premature exit.  But gcc can't
70
 *    fuck ME over!  Just stick a FORCE_RET; at the END of the offending
71
 *    function.
72
 * 4) All operations must start with `op_'.  dyngen ignores all other functions.
73
 * 5) Local variables are depriciated: They hinder performance.
74
 * 6) Function calls are expensive as the stack has to be shifted (twice).
75
 */
76
 
77
/*#define __or_dynop __attribute__((noreturn))*/
78
#define __or_dynop
79
 
80
/* Temporaries to hold the (simulated) registers in */
81
register uint32_t t0 asm(T0_REG);
82
register uint32_t t1 asm(T1_REG);
83
register uint32_t t2 asm(T2_REG);
84
 
85
#define OP_PARAM1 ((uorreg_t)(&__op_param1))
86
#define OP_PARAM2 ((uorreg_t)(&__op_param2))
87
#define OP_PARAM3 ((uorreg_t)(&__op_param3))
88
 
89
extern uorreg_t __op_param1;
90
extern uorreg_t __op_param2;
91
extern uorreg_t __op_param3;
92
 
93
 
94
/* Helper function.  Whenever we escape the recompiled code and there is a
95
 * potential that an exception may happen this function must be called */
96
static inline void save_t_temporary(void)
97
{
98
  env->t0 = t0;
99
  env->t1 = t1;
100
  env->t2 = t2;
101
}
102
 
103
/* Wrapper around do_scheduler.  This is needed because op_do_sched must be as
104
 * small as possible. */
105
void do_sched_wrap(void)
106
{
107
  save_t_temporary();
108
  upd_sim_cycles();
109
  do_scheduler();
110
}
111
 
112 1481 nogj
/* do_scheduler wrapper for instructions that are in the delay slot */
113
void do_sched_wrap_delay(void)
114
{
115
  save_t_temporary();
116
  upd_sim_cycles();
117
  env->ts_current = 1;
118
  /* The PC gets set to the location of the jump, but do_sched increments that
119
   * so pull it back here to point to the right location again.  This could be
120
   * done in op_add_pc/op_set_pc_pc_delay but that would enlarge the recompiled
121
   * code. */
122
  //env->pc -= 4;
123
  do_scheduler();
124
  env->ts_current = 0;
125
}
126
 
127
void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
128
{
129
  uint16_t reg;
130
 
131 1483 nogj
  addr &= config.immu.pagesize - 1;
132 1481 nogj
  addr >>= 2;
133
 
134
  reg = dp->ts_bound[addr];
135
 
136
  if(reg & 0x1f)
137
    t0 = cpu_state.reg[reg & 0x1f];
138
 
139
  if((reg >> 5) & 0x1f)
140
    t1 = cpu_state.reg[(reg >> 5) & 0x1f];
141
 
142
  if((reg >> 10) & 0x1f)
143
    t2 = cpu_state.reg[(reg >> 10) & 0x1f];
144
 
145
  or_longjmp(dp->locs[addr]);
146
}
147
 
148 1452 nogj
 
149 1481 nogj
__or_dynop void op_set_pc_pc_delay(void)
150 1452 nogj
{
151 1481 nogj
  env->sprs[SPR_PPC] = get_pc();
152
  /* pc_delay is pulled back 4 since imediatly after this is run, the scheduler
153
   * runs which also increments it by 4 */
154
  set_pc(env->pc_delay - 4);
155 1452 nogj
}
156
 
157
__or_dynop void op_set_pc_delay_imm(void)
158
{
159
  env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
160
  env->delay_insn = 1;
161
}
162
 
163
__or_dynop void op_set_pc_delay_pc(void)
164
{
165
  env->pc_delay = get_pc();
166
  env->delay_insn = 1;
167
}
168
 
169
__or_dynop void op_clear_pc_delay(void)
170
{
171
  env->pc_delay = 0;
172
  env->delay_insn = 1;
173
}
174
 
175
__or_dynop void op_do_jump(void)
176
{
177 1481 nogj
  do_jump(get_pc());
178
}
179
 
180
__or_dynop void op_do_jump_delay(void)
181
{
182 1452 nogj
  do_jump(env->pc_delay);
183
}
184
 
185 1481 nogj
__or_dynop void op_clear_delay_insn(void)
186 1452 nogj
{
187 1481 nogj
  env->delay_insn = 0;
188 1452 nogj
}
189
 
190 1481 nogj
__or_dynop void op_set_delay_insn(void)
191 1452 nogj
{
192 1481 nogj
  env->delay_insn = 1;
193 1452 nogj
}
194
 
195 1481 nogj
__or_dynop void op_check_delay_slot(void)
196 1452 nogj
{
197 1481 nogj
  if(!env->delay_insn)
198
    OP_JUMP(OP_PARAM1);
199 1452 nogj
}
200
 
201
__or_dynop void op_jmp_imm(void)
202
{
203
  OP_JUMP(OP_PARAM1);
204
}
205
 
206
__or_dynop void op_set_flag(void)
207
{
208
  env->sprs[SPR_SR] |= SPR_SR_F;
209
}
210
 
211
__or_dynop void op_clear_flag(void)
212
{
213
  env->sprs[SPR_SR] &= ~SPR_SR_F;
214
}
215
 
216 1481 nogj
/* Used for the l.bf instruction.  Therefore if the flag is not set, jump over
217
 * all the jumping stuff */
218 1452 nogj
__or_dynop void op_check_flag(void)
219
{
220 1481 nogj
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
221
    HANDLE_SCHED(do_sched_wrap, "no_sched_chk_flg");
222
    OP_JUMP(OP_PARAM1);
223
  }
224
}
225
 
226
/* Used for l.bf if the delay slot instruction is on another page */
227
__or_dynop void op_check_flag_delay(void)
228
{
229 1452 nogj
  if(env->sprs[SPR_SR] & SPR_SR_F) {
230 1481 nogj
    env->delay_insn = 1;
231 1452 nogj
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
232
  }
233
}
234
 
235 1481 nogj
/* Used for the l.bnf instruction.  Therefore if the flag is set, jump over all
236
 * the jumping stuff */
237 1452 nogj
__or_dynop void op_check_not_flag(void)
238
{
239 1481 nogj
  if(env->sprs[SPR_SR] & SPR_SR_F) {
240
    HANDLE_SCHED(do_sched_wrap, "no_sched_chk_not_flg");
241
    OP_JUMP(OP_PARAM1);
242
  }
243
}
244
 
245
/* Used for l.bnf if the delay slot instruction is on another page */
246
__or_dynop void op_check_not_flag_delay(void)
247
{
248 1452 nogj
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
249 1481 nogj
    env->delay_insn = 1;
250 1452 nogj
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
251
  }
252
}
253
 
254
__or_dynop void op_set_ts_current(void)
255
{
256
  env->ts_current = 1;
257
}
258
 
259 1481 nogj
__or_dynop void op_add_pc(void)
260 1452 nogj
{
261 1481 nogj
  /* FIXME: Optimise */
262
  set_pc(get_pc() + OP_PARAM1);
263 1452 nogj
}
264
 
265
__or_dynop void op_nop_exit(void)
266
{
267
  upd_sim_cycles();
268
  save_t_temporary();
269
  op_support_nop_exit();
270
  FORCE_RET;
271
}
272
 
273
__or_dynop void op_nop_reset(void)
274
{
275
  upd_sim_cycles();
276
  op_support_nop_reset();
277 1481 nogj
  do_jump(EXCEPT_RESET);
278 1452 nogj
}
279
 
280
__or_dynop void op_nop_printf(void)
281
{
282
  save_t_temporary();
283
  upd_sim_cycles();
284
  op_support_nop_printf();
285
  FORCE_RET;
286
}
287
 
288
__or_dynop void op_nop_report(void)
289
{
290
  save_t_temporary();
291
  upd_sim_cycles();
292
  op_support_nop_report();
293
  FORCE_RET;
294
}
295
 
296
__or_dynop void op_nop_report_imm(void)
297
{
298
  save_t_temporary();
299
  upd_sim_cycles();
300
  op_support_nop_report_imm(OP_PARAM1);
301
}
302
 
303 1657 nogj
__or_dynop void op_analysis(void)
304 1452 nogj
{
305 1657 nogj
  env->iqueue.insn_index = OP_PARAM1;
306
  env->iqueue.insn = OP_PARAM2;
307
  env->iqueue.insn_addr = get_pc();
308
  save_t_temporary();
309
  op_support_analysis();
310
  FORCE_RET;
311 1452 nogj
}
312
 
313 1657 nogj
__or_dynop void op_move_gpr1_pc_delay(void)
314
{
315
  env->pc_delay = env->reg[1];
316
  env->delay_insn = 1;
317
}
318 1452 nogj
 
319 1657 nogj
__or_dynop void op_move_gpr2_pc_delay(void)
320 1452 nogj
{
321 1657 nogj
  env->pc_delay = env->reg[2];
322
  env->delay_insn = 1;
323 1452 nogj
}
324
 
325 1657 nogj
__or_dynop void op_move_gpr3_pc_delay(void)
326 1452 nogj
{
327 1657 nogj
  env->pc_delay = env->reg[3];
328
  env->delay_insn = 1;
329 1452 nogj
}
330
 
331 1657 nogj
__or_dynop void op_move_gpr4_pc_delay(void)
332
{
333
  env->pc_delay = env->reg[4];
334
  env->delay_insn = 1;
335
}
336 1452 nogj
 
337 1657 nogj
__or_dynop void op_move_gpr5_pc_delay(void)
338 1452 nogj
{
339 1657 nogj
  env->pc_delay = env->reg[5];
340
  env->delay_insn = 1;
341 1452 nogj
}
342
 
343 1657 nogj
__or_dynop void op_move_gpr6_pc_delay(void)
344 1452 nogj
{
345 1657 nogj
  env->pc_delay = env->reg[6];
346
  env->delay_insn = 1;
347 1452 nogj
}
348
 
349 1657 nogj
__or_dynop void op_move_gpr7_pc_delay(void)
350 1452 nogj
{
351 1657 nogj
  env->pc_delay = env->reg[7];
352
  env->delay_insn = 1;
353 1452 nogj
}
354
 
355 1657 nogj
__or_dynop void op_move_gpr8_pc_delay(void)
356 1452 nogj
{
357 1657 nogj
  env->pc_delay = env->reg[8];
358
  env->delay_insn = 1;
359 1452 nogj
}
360
 
361 1657 nogj
__or_dynop void op_move_gpr9_pc_delay(void)
362
{
363
  env->pc_delay = env->reg[9];
364
  env->delay_insn = 1;
365
}
366
 
367
__or_dynop void op_move_gpr10_pc_delay(void)
368
{
369
  env->pc_delay = env->reg[10];
370
  env->delay_insn = 1;
371
}
372
 
373
__or_dynop void op_move_gpr11_pc_delay(void)
374
{
375
  env->pc_delay = env->reg[11];
376
  env->delay_insn = 1;
377
}
378
 
379
__or_dynop void op_move_gpr12_pc_delay(void)
380
{
381
  env->pc_delay = env->reg[12];
382
  env->delay_insn = 1;
383
}
384
 
385
__or_dynop void op_move_gpr13_pc_delay(void)
386
{
387
  env->pc_delay = env->reg[13];
388
  env->delay_insn = 1;
389
}
390
 
391
__or_dynop void op_move_gpr14_pc_delay(void)
392
{
393
  env->pc_delay = env->reg[14];
394
  env->delay_insn = 1;
395
}
396
 
397
__or_dynop void op_move_gpr15_pc_delay(void)
398
{
399
  env->pc_delay = env->reg[15];
400
  env->delay_insn = 1;
401
}
402
 
403
__or_dynop void op_move_gpr16_pc_delay(void)
404
{
405
  env->pc_delay = env->reg[16];
406
  env->delay_insn = 1;
407
}
408
 
409
__or_dynop void op_move_gpr17_pc_delay(void)
410
{
411
  env->pc_delay = env->reg[17];
412
  env->delay_insn = 1;
413
}
414
 
415
__or_dynop void op_move_gpr18_pc_delay(void)
416
{
417
  env->pc_delay = env->reg[18];
418
  env->delay_insn = 1;
419
}
420
 
421
__or_dynop void op_move_gpr19_pc_delay(void)
422
{
423
  env->pc_delay = env->reg[19];
424
  env->delay_insn = 1;
425
}
426
 
427
__or_dynop void op_move_gpr20_pc_delay(void)
428
{
429
  env->pc_delay = env->reg[20];
430
  env->delay_insn = 1;
431
}
432
 
433
__or_dynop void op_move_gpr21_pc_delay(void)
434
{
435
  env->pc_delay = env->reg[21];
436
  env->delay_insn = 1;
437
}
438
 
439
__or_dynop void op_move_gpr22_pc_delay(void)
440
{
441
  env->pc_delay = env->reg[22];
442
  env->delay_insn = 1;
443
}
444
 
445
__or_dynop void op_move_gpr23_pc_delay(void)
446
{
447
  env->pc_delay = env->reg[23];
448
  env->delay_insn = 1;
449
}
450
 
451
__or_dynop void op_move_gpr24_pc_delay(void)
452
{
453
  env->pc_delay = env->reg[24];
454
  env->delay_insn = 1;
455
}
456
 
457
__or_dynop void op_move_gpr25_pc_delay(void)
458
{
459
  env->pc_delay = env->reg[25];
460
  env->delay_insn = 1;
461
}
462
 
463
__or_dynop void op_move_gpr26_pc_delay(void)
464
{
465
  env->pc_delay = env->reg[26];
466
  env->delay_insn = 1;
467
}
468
 
469
__or_dynop void op_move_gpr27_pc_delay(void)
470
{
471
  env->pc_delay = env->reg[27];
472
  env->delay_insn = 1;
473
}
474
 
475
__or_dynop void op_move_gpr28_pc_delay(void)
476
{
477
  env->pc_delay = env->reg[28];
478
  env->delay_insn = 1;
479
}
480
 
481
__or_dynop void op_move_gpr29_pc_delay(void)
482
{
483
  env->pc_delay = env->reg[29];
484
  env->delay_insn = 1;
485
}
486
 
487
__or_dynop void op_move_gpr30_pc_delay(void)
488
{
489
  env->pc_delay = env->reg[30];
490
  env->delay_insn = 1;
491
}
492
 
493
__or_dynop void op_move_gpr31_pc_delay(void)
494
{
495
  env->pc_delay = env->reg[31];
496
  env->delay_insn = 1;
497
}
498
 
499
#define OP_FILE "op_1t_op.h"
500
#include "op_1t.h"
501
#undef OP_FILE
502 1658 nogj
 
503
#define OP_FILE "op_2t_op.h"
504
#include "op_2t.h"
505
#undef OP_FILE
506 1660 nogj
 
507
#define OP_FILE "op_3t_op.h"
508
#include "op_3t.h"
509
#undef OP_FILE
510
 
511 1661 nogj
#define OP_FILE "op_arith_op.h"
512 1452 nogj
#define OP_EXTRA
513
 
514
#define OP /
515 1661 nogj
#define OP_CAST(x) (orreg_t)(x)
516 1452 nogj
#define OP_NAME div
517 1661 nogj
#include "op_3t.h"
518 1452 nogj
#undef OP_NAME
519
#undef OP_CAST
520
#undef OP
521
 
522
#define OP /
523 1661 nogj
#define OP_CAST(x) (x)
524 1452 nogj
#define OP_NAME divu
525 1661 nogj
#include "op_3t.h"
526 1452 nogj
#undef OP_NAME
527
#undef OP_CAST
528
#undef OP
529
 
530
#define OP *
531 1661 nogj
#define OP_CAST(x) (x)
532 1452 nogj
#define OP_NAME mulu
533 1661 nogj
#include "op_3t.h"
534 1452 nogj
#undef OP_NAME
535
#undef OP_CAST
536
#undef OP
537
 
538
#define OP -
539 1661 nogj
#define OP_CAST(x) (orreg_t)(x)
540 1452 nogj
#define OP_NAME sub
541 1661 nogj
#include "op_3t.h"
542 1452 nogj
#undef OP_NAME
543
#undef OP_CAST
544
#undef OP
545
 
546
#undef OP_EXTRA
547
 
548
#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10)
549
#define OP +
550 1661 nogj
#define OP_CAST(x) (orreg_t)(x)
551 1452 nogj
#define OP_NAME addc
552 1661 nogj
#include "op_3t.h"
553
#include "op_2t.h"
554 1452 nogj
#undef OP_NAME
555
#undef OP_CAST
556
#undef OP
557
 
558
#undef OP_EXTRA
559
#define OP_EXTRA
560
 
561
#define OP +
562 1661 nogj
#define OP_CAST(x) (orreg_t)(x)
563 1452 nogj
#define OP_NAME add
564 1661 nogj
#include "op_3t.h"
565
#include "op_2t.h"
566 1452 nogj
#undef OP_NAME
567
#undef OP_CAST
568
#undef OP
569
 
570
#define OP &
571 1661 nogj
#define OP_CAST(x) (x)
572 1452 nogj
#define OP_NAME and
573 1661 nogj
#include "op_3t.h"
574
#include "op_2t.h"
575 1452 nogj
#undef OP_NAME
576
#undef OP_CAST
577
#undef OP
578
 
579
#define OP *
580 1661 nogj
#define OP_CAST(x) (orreg_t)(x)
581 1452 nogj
#define OP_NAME mul
582 1661 nogj
#include "op_3t.h"
583
#include "op_2t.h"
584 1452 nogj
#undef OP_NAME
585
#undef OP_CAST
586
#undef OP
587
 
588
#define OP |
589 1661 nogj
#define OP_CAST(x) (x)
590 1452 nogj
#define OP_NAME or
591 1661 nogj
#include "op_3t.h"
592
#include "op_2t.h"
593 1452 nogj
#undef OP_NAME
594
#undef OP_CAST
595
#undef OP
596
 
597
#define OP <<
598 1661 nogj
#define OP_CAST(x) (x)
599 1452 nogj
#define OP_NAME sll
600 1661 nogj
#include "op_3t.h"
601
#include "op_2t.h"
602 1452 nogj
#undef OP_NAME
603
#undef OP_CAST
604
#undef OP
605
 
606
#define OP >>
607 1661 nogj
#define OP_CAST(x) (orreg_t)(x)
608 1452 nogj
#define OP_NAME sra
609 1661 nogj
#include "op_3t.h"
610
#include "op_2t.h"
611 1452 nogj
#undef OP_NAME
612
#undef OP_CAST
613
#undef OP
614
 
615
#define OP >>
616 1661 nogj
#define OP_CAST(x) (x)
617 1452 nogj
#define OP_NAME srl
618 1661 nogj
#include "op_3t.h"
619
#include "op_2t.h"
620 1452 nogj
#undef OP_NAME
621
#undef OP_CAST
622
#undef OP
623
 
624
#define OP ^
625 1661 nogj
#define OP_CAST(x) (x)
626 1452 nogj
#define OP_NAME xor
627 1661 nogj
#include "op_3t.h"
628
#include "op_2t.h"
629 1452 nogj
#undef OP_NAME
630
#undef OP_CAST
631
#undef OP
632
 
633
#undef OP_EXTRA
634 1661 nogj
#undef OP_FILE
635 1452 nogj
 
636
#define EXT_NAME extbs
637
#define EXT_TYPE int8_t
638
#define EXT_CAST (orreg_t)
639
#include "op_extend_op.h"
640
#undef EXT_CAST
641
#undef EXT_TYPE
642
#undef EXT_NAME
643
 
644
#define EXT_NAME extbz
645
#define EXT_TYPE uint8_t
646
#define EXT_CAST (uorreg_t)
647
#include "op_extend_op.h"
648
#undef EXT_CAST
649
#undef EXT_TYPE
650
#undef EXT_NAME
651
 
652
#define EXT_NAME exths
653
#define EXT_TYPE int16_t
654
#define EXT_CAST (orreg_t)
655
#include "op_extend_op.h"
656
#undef EXT_CAST
657
#undef EXT_TYPE
658
#undef EXT_NAME
659
 
660
#define EXT_NAME exthz
661
#define EXT_TYPE uint16_t
662
#define EXT_CAST (uorreg_t)
663
#include "op_extend_op.h"
664
#undef EXT_CAST
665
#undef EXT_TYPE
666
#undef EXT_NAME
667
 
668
#define COMP ==
669
#define COMP_NAME sfeq
670
#define COMP_CAST(t) t
671
#include "op_comp_op.h"
672
#undef COMP_CAST
673
#undef COMP_NAME
674
#undef COMP
675
 
676
#define COMP !=
677
#define COMP_NAME sfne
678
#define COMP_CAST(t) t
679
#include "op_comp_op.h"
680
#undef COMP_CAST
681
#undef COMP_NAME
682
#undef COMP
683
 
684
#define COMP >
685
#define COMP_NAME sfgtu
686
#define COMP_CAST(t) t
687
#include "op_comp_op.h"
688
#undef COMP_CAST
689
#undef COMP_NAME
690
#undef COMP
691
 
692
#define COMP >=
693
#define COMP_NAME sfgeu
694
#define COMP_CAST(t) t
695
#include "op_comp_op.h"
696
#undef COMP_CAST
697
#undef COMP_NAME
698
#undef COMP
699
 
700
#define COMP <
701
#define COMP_NAME sfltu
702
#define COMP_CAST(t) t
703
#include "op_comp_op.h"
704
#undef COMP_CAST
705
#undef COMP_NAME
706
#undef COMP
707
 
708
#define COMP <=
709
#define COMP_NAME sfleu
710
#define COMP_CAST(t) t
711
#include "op_comp_op.h"
712
#undef COMP_CAST
713
#undef COMP_NAME
714
#undef COMP
715
 
716
#define COMP >
717
#define COMP_NAME sfgts
718
#define COMP_CAST(t) (orreg_t)t
719
#include "op_comp_op.h"
720
#undef COMP_CAST
721
#undef COMP_NAME
722
#undef COMP
723
 
724
#define COMP >=
725
#define COMP_NAME sfges
726
#define COMP_CAST(t) (orreg_t)t
727
#include "op_comp_op.h"
728
#undef COMP_CAST
729
#undef COMP_NAME
730
#undef COMP
731
 
732
#define COMP <
733
#define COMP_NAME sflts
734
#define COMP_CAST(t) (orreg_t)t
735
#include "op_comp_op.h"
736
#undef COMP_CAST
737
#undef COMP_NAME
738
#undef COMP
739
 
740
#define COMP <=
741
#define COMP_NAME sfles
742
#define COMP_CAST(t) (orreg_t)t
743
#include "op_comp_op.h"
744
#undef COMP_CAST
745
#undef COMP_NAME
746
#undef COMP
747
 
748 1657 nogj
#define OP_FILE "op_t_reg_mov_op.h"
749
#include "op_1t.h"
750
#undef OP_FILE
751 1452 nogj
 
752
#define SPR_T_NAME SPR_T
753
#define GPR_T_NAME GPR_T
754
 
755
#define SPR_T t0
756
#define GPR_T t0
757
#include "op_mftspr_op.h"
758
#undef GPR_T
759
 
760
#define GPR_T t1
761
#include "op_mftspr_op.h"
762
#undef GPR_T
763
 
764
#define GPR_T t2
765
#include "op_mftspr_op.h"
766
#undef GPR_T
767
#undef SPR_T
768
 
769
#define SPR_T t1
770
#define GPR_T t0
771
#include "op_mftspr_op.h"
772
#undef GPR_T
773
 
774
#define GPR_T t1
775
#include "op_mftspr_op.h"
776
#undef GPR_T
777
 
778
#define GPR_T t2
779
#include "op_mftspr_op.h"
780
#undef GPR_T
781
#undef SPR_T
782
 
783
#define SPR_T t2
784
#define GPR_T t0
785
#include "op_mftspr_op.h"
786
#undef GPR_T
787
 
788
#define GPR_T t1
789
#include "op_mftspr_op.h"
790
#undef GPR_T
791
 
792
#define GPR_T t2
793
#include "op_mftspr_op.h"
794
#undef GPR_T
795
#undef SPR_T
796
 
797
#undef GPR_T_NAME
798
#undef SPR_T_NAME
799
 
800
#define SPR_T_NAME imm
801
#define GPR_T_NAME GPR_T
802
 
803
#define SPR_T 0
804
 
805
#define GPR_T t0
806
#include "op_mftspr_op.h"
807
#undef GPR_T
808
 
809
#define GPR_T t1
810
#include "op_mftspr_op.h"
811
#undef GPR_T
812
 
813
#define GPR_T t2
814
#include "op_mftspr_op.h"
815
#undef GPR_T
816
#undef SPR_T
817
 
818
#undef SPR_T_NAME
819
#undef GPR_T_NAME
820
 
821
#define ONLY_MTSPR
822
#define SPR_T_NAME SPR_T
823
#define GPR_T_NAME clear
824
 
825
#define GPR_T 0
826
 
827
#define SPR_T t0
828
#include "op_mftspr_op.h"
829
#undef SPR_T
830
 
831
#define SPR_T t1
832
#include "op_mftspr_op.h"
833
#undef SPR_T
834
 
835
#define SPR_T t2
836
#include "op_mftspr_op.h"
837
#undef SPR_T
838
 
839
#undef GPR_T
840
 
841
#undef SPR_T_NAME
842
#undef GPR_T_NAME
843
 
844
#define SPR_T_NAME imm
845
#define GPR_T_NAME clear
846
#define GPR_T 0
847
#define SPR_T 0
848
#include "op_mftspr_op.h"
849
#undef SPR_T
850
#undef GPR_T
851
#undef GPR_T_NAME
852
#undef SPR_T_NAME
853
 
854
#undef ONLY_MTSPR
855
 
856
#define OP +=
857
#define OP_NAME mac
858
#include "op_mac_op.h"
859
#undef OP_NAME
860
#undef OP
861
 
862
#define OP -=
863
#define OP_NAME msb
864
#include "op_mac_op.h"
865
#undef OP_NAME
866
#undef OP
867
 
868
#define LS_OP_NAME lbz
869
#define LS_OP_CAST
870
#define LS_OP_FUNC eval_mem8
871
#include "op_lwhb_op.h"
872
#undef LS_OP_FUNC
873
#undef LS_OP_CAST
874
#undef LS_OP_NAME
875
 
876
#define LS_OP_NAME lbs
877
#define LS_OP_CAST (int8_t)
878
#define LS_OP_FUNC eval_mem8
879
#include "op_lwhb_op.h"
880
#undef LS_OP_FUNC
881
#undef LS_OP_CAST
882
#undef LS_OP_NAME
883
 
884
#define LS_OP_NAME lhz
885
#define LS_OP_CAST
886
#define LS_OP_FUNC eval_mem16
887
#include "op_lwhb_op.h"
888
#undef LS_OP_FUNC
889
#undef LS_OP_CAST
890
#undef LS_OP_NAME
891
 
892
#define LS_OP_NAME lhs
893
#define LS_OP_CAST (int16_t)
894
#define LS_OP_FUNC eval_mem16
895
#include "op_lwhb_op.h"
896
#undef LS_OP_FUNC
897
#undef LS_OP_CAST
898
#undef LS_OP_NAME
899
 
900
#define LS_OP_NAME lwz
901
#define LS_OP_CAST
902
#define LS_OP_FUNC eval_mem32
903
#include "op_lwhb_op.h"
904
#undef LS_OP_FUNC
905
#undef LS_OP_CAST
906
#undef LS_OP_NAME
907
 
908
#define LS_OP_NAME lws
909
#define LS_OP_CAST (int32_t)
910
#define LS_OP_FUNC eval_mem32
911
#include "op_lwhb_op.h"
912
#undef LS_OP_FUNC
913
#undef LS_OP_CAST
914
#undef LS_OP_NAME
915
 
916
#define S_OP_NAME sb
917
#define S_FUNC set_mem8
918
#include "op_swhb_op.h"
919
#undef S_FUNC
920
#undef S_OP_NAME
921
 
922
#define S_OP_NAME sh
923
#define S_FUNC set_mem16
924
#include "op_swhb_op.h"
925
#undef S_FUNC
926
#undef S_OP_NAME
927
 
928
#define S_OP_NAME sw
929
#define S_FUNC set_mem32
930
#include "op_swhb_op.h"
931
#undef S_FUNC
932
#undef S_OP_NAME
933
 
934
__or_dynop void op_join_mem_cycles(void)
935
{
936
  join_mem_cycles();
937
}
938
 
939
__or_dynop void op_store_link_addr_gpr(void)
940
{
941
  env->reg[LINK_REGNO] = get_pc() + 8;
942
}
943
 
944
__or_dynop void op_prep_rfe(void)
945
{
946
  env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
947
  env->sprs[SPR_PPC] = get_pc();
948 1481 nogj
  env->ts_current = 1;
949
  set_pc(env->sprs[SPR_EPCR_BASE] - 4);
950 1452 nogj
}
951
 
952
static inline void prep_except(oraddr_t epcr_base)
953
{
954
  env->sprs[SPR_EPCR_BASE] = epcr_base;
955
 
956
  env->sprs[SPR_ESR_BASE] = env->sprs[SPR_SR];
957
 
958
  /* Address translation is always disabled when starting exception. */
959
  env->sprs[SPR_SR] &= ~SPR_SR_DME;
960
  env->sprs[SPR_SR] &= ~SPR_SR_IME;
961
 
962
  env->sprs[SPR_SR] &= ~SPR_SR_OVE;   /* Disable overflow flag exception. */
963
 
964
  env->sprs[SPR_SR] |= SPR_SR_SM;     /* SUPV mode */
965
  env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE);    /* Disable interrupts. */
966
}
967
 
968
__or_dynop void op_set_except_pc(void)
969
{
970
  set_pc(OP_PARAM1);
971
}
972
 
973
/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
974
 * Therefore the pc will point to the instruction after the l.sys or l.trap
975
 * instruction */
976
__or_dynop void op_prep_sys_delay(void)
977
{
978
  env->delay_insn = 0;
979 1481 nogj
  env->ts_current = 1;
980 1452 nogj
  prep_except(get_pc() - 4);
981 1481 nogj
  set_pc(EXCEPT_SYSCALL - 4);
982 1452 nogj
}
983
 
984
__or_dynop void op_prep_sys(void)
985
{
986 1481 nogj
  env->ts_current = 1;
987 1452 nogj
  prep_except(get_pc() + 4);
988 1481 nogj
  set_pc(EXCEPT_SYSCALL - 4);
989 1452 nogj
}
990
 
991
__or_dynop void op_prep_trap_delay(void)
992
{
993 1481 nogj
  env->ts_current = 1;
994 1452 nogj
  env->delay_insn = 0;
995
  prep_except(get_pc() - 4);
996 1481 nogj
  set_pc(EXCEPT_TRAP - 4);
997 1452 nogj
}
998
 
999
__or_dynop void op_prep_trap(void)
1000
{
1001 1481 nogj
  env->ts_current = 1;
1002 1452 nogj
  prep_except(get_pc());
1003 1481 nogj
  set_pc(EXCEPT_TRAP - 4);
1004 1452 nogj
}
1005
 
1006
/* FIXME: This `instruction' should be split up like the l.trap and l.sys
1007
 * instructions are done */
1008
__or_dynop void op_illegal_delay(void)
1009
{
1010
  env->delay_insn = 0;
1011 1481 nogj
  env->ts_current = 1;
1012 1452 nogj
  env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
1013 1481 nogj
  do_jump(EXCEPT_ILLEGAL - 4);
1014 1452 nogj
}
1015
 
1016
__or_dynop void op_illegal(void)
1017
{
1018
  env->sprs[SPR_EEAR_BASE] = get_pc();
1019 1481 nogj
  do_jump(EXCEPT_ILLEGAL);
1020 1452 nogj
}
1021
 
1022
__or_dynop void op_do_sched(void)
1023
{
1024 1481 nogj
  HANDLE_SCHED(do_sched_wrap, "no_sched");
1025 1452 nogj
}
1026
 
1027 1481 nogj
__or_dynop void op_do_sched_delay(void)
1028
{
1029
  HANDLE_SCHED(do_sched_wrap_delay, "no_sched_delay");
1030
}
1031
 
1032 1452 nogj
__or_dynop void op_macc(void)
1033
{
1034
  env->sprs[SPR_MACLO] = 0;
1035
  env->sprs[SPR_MACHI] = 0;
1036
}
1037
 
1038
__or_dynop void op_store_insn_ea(void)
1039
{
1040
  env->insn_ea = OP_PARAM1;
1041
}
1042
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.