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/* op.c -- Micro operations for the recompiler
   Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "spr_defs.h"
#include "opcode/or32.h"
#include "sim-config.h"
#include "except.h"
#include "abstract.h"
#include "execute.h"
#include "sprs.h"
#include "sched.h"
 
#include "op_support.h"
 
#include "i386_regs.h"
 
#include "dyn_rec.h"
 
/* This must be here since the function in op_i386.h use this variable */
register struct cpu_state *env asm(CPU_STATE_REG);
 
#include "op_i386.h"
 
/*
 * WARNING: Before going of and wildly editing everything in this file remember
 * the following about its contents:
 * 1) The `functions' don't EVER return.  In otherwords haveing return state-
 *    ments _anywere_ in this file is likely not to work.  This is because
 *    dyngen just strips away the ret from the end of the function and just uses
 *    the function `body'.  If a ret statement is executed _anyware_ inside the
 *    dynamicly generated code, then it is undefined were we shall jump to.
 * 2) Because of 1), try not to have overly complicated functions.  In too
 *    complicated functions, gcc may decide to generate premature `exits'.  This
 *    is what passing the -fno-reorder-blocks command line switch to gcc helps
 *    with.  This is ofcourse not desired and is rather flaky as we don't (and
 *    can't) control the kind of code that gcc generates: It may work for one
 *    and break for another.  The less branches there are the less likely it is
 *    that a premature return shall occur.
 * 3) If gcc decides that it is going to be a basterd then it will optimise a
 *    very simple condition (if/switch) with a premature exit.  But gcc can't
 *    fuck ME over!  Just stick a FORCE_RET; at the END of the offending
 *    function.
 * 4) All operations must start with `op_'.  dyngen ignores all other functions.
 * 5) Local variables are depriciated: They hinder performance.
 * 6) Function calls are expensive as the stack has to be shifted (twice).
 */
 
/*#define __or_dynop __attribute__((noreturn))*/
#define __or_dynop
 
/* Temporaries to hold the (simulated) registers in */
register uint32_t t0 asm(T0_REG);
register uint32_t t1 asm(T1_REG);
register uint32_t t2 asm(T2_REG);
 
#define OP_PARAM1 ((uorreg_t)(&__op_param1))
#define OP_PARAM2 ((uorreg_t)(&__op_param2))
#define OP_PARAM3 ((uorreg_t)(&__op_param3))
 
extern uorreg_t __op_param1;
extern uorreg_t __op_param2;
extern uorreg_t __op_param3;
 
 
/* Helper function.  Whenever we escape the recompiled code and there is a
 * potential that an exception may happen this function must be called */
static inline void save_t_temporary(void)
{
  env->t0 = t0;
  env->t1 = t1;
  env->t2 = t2;
}
 
/* Wrapper around do_scheduler.  This is needed because op_do_sched must be as
 * small as possible. */
void do_sched_wrap(void)
{
  save_t_temporary();
  upd_sim_cycles();
  do_scheduler();
}
 
/* do_scheduler wrapper for instructions that are in the delay slot */
void do_sched_wrap_delay(void)
{
  save_t_temporary();
  upd_sim_cycles();
  env->ts_current = 1;
  /* The PC gets set to the location of the jump, but do_sched increments that
   * so pull it back here to point to the right location again.  This could be
   * done in op_add_pc/op_set_pc_pc_delay but that would enlarge the recompiled
   * code. */
  //env->pc -= 4;
  do_scheduler();
  env->ts_current = 0;
}
 
void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
{
  uint16_t reg;
 
  addr &= config.immu.pagesize - 1;
  addr >>= 2;
 
  reg = dp->ts_bound[addr];
 
  if(reg & 0x1f)
    t0 = cpu_state.reg[reg & 0x1f];
 
  if((reg >> 5) & 0x1f)
    t1 = cpu_state.reg[(reg >> 5) & 0x1f];
 
  if((reg >> 10) & 0x1f)
    t2 = cpu_state.reg[(reg >> 10) & 0x1f];
 
  or_longjmp(dp->locs[addr]);
}
 
 
__or_dynop void op_set_pc_pc_delay(void)
{
  env->sprs[SPR_PPC] = get_pc();
  /* pc_delay is pulled back 4 since imediatly after this is run, the scheduler
   * runs which also increments it by 4 */
  set_pc(env->pc_delay - 4);
}
 
__or_dynop void op_set_pc_delay_imm(void)
{
  env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
  env->delay_insn = 1;
}
 
__or_dynop void op_set_pc_delay_pc(void)
{
  env->pc_delay = get_pc();
  env->delay_insn = 1;
}
 
__or_dynop void op_clear_pc_delay(void)
{
  env->pc_delay = 0;
  env->delay_insn = 1;
}
 
__or_dynop void op_do_jump(void)
{
  do_jump(get_pc());
}
 
__or_dynop void op_do_jump_delay(void)
{
  do_jump(env->pc_delay);
}
 
__or_dynop void op_clear_delay_insn(void)
{
  env->delay_insn = 0;
}
 
__or_dynop void op_set_delay_insn(void)
{
  env->delay_insn = 1;
}
 
__or_dynop void op_check_delay_slot(void)
{
  if(!env->delay_insn)
    OP_JUMP(OP_PARAM1);
}
 
__or_dynop void op_jmp_imm(void)
{
  OP_JUMP(OP_PARAM1);
}
 
__or_dynop void op_set_flag(void)
{
  env->sprs[SPR_SR] |= SPR_SR_F;
}
 
__or_dynop void op_clear_flag(void)
{
  env->sprs[SPR_SR] &= ~SPR_SR_F;
}
 
/* Used for the l.bf instruction.  Therefore if the flag is not set, jump over
 * all the jumping stuff */
__or_dynop void op_check_flag(void)
{
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
    HANDLE_SCHED(do_sched_wrap, "no_sched_chk_flg");
    OP_JUMP(OP_PARAM1);
  }
}
 
/* Used for l.bf if the delay slot instruction is on another page */
__or_dynop void op_check_flag_delay(void)
{
  if(env->sprs[SPR_SR] & SPR_SR_F) {
    env->delay_insn = 1;
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
  }
}
 
/* Used for the l.bnf instruction.  Therefore if the flag is set, jump over all
 * the jumping stuff */
__or_dynop void op_check_not_flag(void)
{
  if(env->sprs[SPR_SR] & SPR_SR_F) {
    HANDLE_SCHED(do_sched_wrap, "no_sched_chk_not_flg");
    OP_JUMP(OP_PARAM1);
  }
}
 
/* Used for l.bnf if the delay slot instruction is on another page */
__or_dynop void op_check_not_flag_delay(void)
{
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
    env->delay_insn = 1;
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
  }
}
 
__or_dynop void op_set_ts_current(void)
{
  env->ts_current = 1;
}
 
__or_dynop void op_add_pc(void)
{
  /* FIXME: Optimise */
  set_pc(get_pc() + OP_PARAM1);
}
 
__or_dynop void op_nop_exit(void)
{
  upd_sim_cycles();
  save_t_temporary();
  op_support_nop_exit();
  FORCE_RET;
}
 
__or_dynop void op_nop_reset(void)
{
  upd_sim_cycles();
  op_support_nop_reset();
  do_jump(EXCEPT_RESET);
}
 
__or_dynop void op_nop_printf(void)
{
  save_t_temporary();
  upd_sim_cycles();
  op_support_nop_printf();
  FORCE_RET;
}
 
__or_dynop void op_nop_report(void)
{
  save_t_temporary();
  upd_sim_cycles();
  op_support_nop_report();
  FORCE_RET;
}
 
__or_dynop void op_nop_report_imm(void)
{
  save_t_temporary();
  upd_sim_cycles();
  op_support_nop_report_imm(OP_PARAM1);
}
 
__or_dynop void op_analysis(void)
{
  env->iqueue.insn_index = OP_PARAM1;
  env->iqueue.insn = OP_PARAM2;
  env->iqueue.insn_addr = get_pc();
  save_t_temporary();
  op_support_analysis();
  FORCE_RET;
}
 
__or_dynop void op_move_gpr1_pc_delay(void)
{
  env->pc_delay = env->reg[1];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr2_pc_delay(void)
{
  env->pc_delay = env->reg[2];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr3_pc_delay(void)
{
  env->pc_delay = env->reg[3];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr4_pc_delay(void)
{
  env->pc_delay = env->reg[4];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr5_pc_delay(void)
{
  env->pc_delay = env->reg[5];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr6_pc_delay(void)
{
  env->pc_delay = env->reg[6];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr7_pc_delay(void)
{
  env->pc_delay = env->reg[7];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr8_pc_delay(void)
{
  env->pc_delay = env->reg[8];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr9_pc_delay(void)
{
  env->pc_delay = env->reg[9];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr10_pc_delay(void)
{
  env->pc_delay = env->reg[10];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr11_pc_delay(void)
{
  env->pc_delay = env->reg[11];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr12_pc_delay(void)
{
  env->pc_delay = env->reg[12];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr13_pc_delay(void)
{
  env->pc_delay = env->reg[13];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr14_pc_delay(void)
{
  env->pc_delay = env->reg[14];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr15_pc_delay(void)
{
  env->pc_delay = env->reg[15];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr16_pc_delay(void)
{
  env->pc_delay = env->reg[16];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr17_pc_delay(void)
{
  env->pc_delay = env->reg[17];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr18_pc_delay(void)
{
  env->pc_delay = env->reg[18];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr19_pc_delay(void)
{
  env->pc_delay = env->reg[19];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr20_pc_delay(void)
{
  env->pc_delay = env->reg[20];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr21_pc_delay(void)
{
  env->pc_delay = env->reg[21];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr22_pc_delay(void)
{
  env->pc_delay = env->reg[22];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr23_pc_delay(void)
{
  env->pc_delay = env->reg[23];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr24_pc_delay(void)
{
  env->pc_delay = env->reg[24];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr25_pc_delay(void)
{
  env->pc_delay = env->reg[25];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr26_pc_delay(void)
{
  env->pc_delay = env->reg[26];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr27_pc_delay(void)
{
  env->pc_delay = env->reg[27];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr28_pc_delay(void)
{
  env->pc_delay = env->reg[28];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr29_pc_delay(void)
{
  env->pc_delay = env->reg[29];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr30_pc_delay(void)
{
  env->pc_delay = env->reg[30];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr31_pc_delay(void)
{
  env->pc_delay = env->reg[31];
  env->delay_insn = 1;
}
 
#define OP_FILE "op_1t_op.h"
#include "op_1t.h"
#undef OP_FILE
 
#define OP_FILE "op_2t_op.h"
#include "op_2t.h"
#undef OP_FILE
 
#define OP_FILE "op_3t_op.h"
#include "op_3t.h"
#undef OP_FILE
 
#define OP_FILE "op_arith_op.h"
#define OP_EXTRA
 
#define OP /
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME div
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP /
#define OP_CAST(x) (x)
#define OP_NAME divu
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP *
#define OP_CAST(x) (x)
#define OP_NAME mulu
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP -
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME sub
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
 
#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10)
#define OP +
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME addc
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
#define OP_EXTRA
 
#define OP +
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME add
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP &
#define OP_CAST(x) (x)
#define OP_NAME and
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP *
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME mul
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP |
#define OP_CAST(x) (x)
#define OP_NAME or
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP <<
#define OP_CAST(x) (x)
#define OP_NAME sll
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP >>
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME sra
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP >>
#define OP_CAST(x) (x)
#define OP_NAME srl
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP ^
#define OP_CAST(x) (x)
#define OP_NAME xor
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
#undef OP_FILE
 
#define OP_FILE "op_extend_op.h"
 
#define EXT_NAME extbs
#define EXT_TYPE int8_t
#define EXT_CAST (orreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME extbz
#define EXT_TYPE uint8_t
#define EXT_CAST (uorreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME exths
#define EXT_TYPE int16_t
#define EXT_CAST (orreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME exthz
#define EXT_TYPE uint16_t
#define EXT_CAST (uorreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#undef OP_FILE
 
#define OP_FILE "op_comp_op.h"
 
#define COMP ==
#define COMP_NAME sfeq
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP !=
#define COMP_NAME sfne
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >
#define COMP_NAME sfgtu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >=
#define COMP_NAME sfgeu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <
#define COMP_NAME sfltu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <=
#define COMP_NAME sfleu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >
#define COMP_NAME sfgts
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >=
#define COMP_NAME sfges
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <
#define COMP_NAME sflts
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <=
#define COMP_NAME sfles
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#undef OP_FILE
 
#define OP_FILE "op_t_reg_mov_op.h"
#include "op_1t.h"
#undef OP_FILE
 
#define SPR_T_NAME SPR_T
#define GPR_T_NAME GPR_T
 
#define SPR_T t0
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#define SPR_T t1
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#define SPR_T t2
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#undef GPR_T_NAME
#undef SPR_T_NAME
 
#define SPR_T_NAME imm
#define GPR_T_NAME GPR_T
 
#define SPR_T 0
 
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#undef SPR_T_NAME
#undef GPR_T_NAME
 
#define ONLY_MTSPR
#define SPR_T_NAME SPR_T
#define GPR_T_NAME clear
 
#define GPR_T 0
 
#define SPR_T t0
#include "op_mftspr_op.h"
#undef SPR_T
 
#define SPR_T t1
#include "op_mftspr_op.h"
#undef SPR_T
 
#define SPR_T t2
#include "op_mftspr_op.h"
#undef SPR_T
 
#undef GPR_T
 
#undef SPR_T_NAME
#undef GPR_T_NAME
 
#define SPR_T_NAME imm
#define GPR_T_NAME clear
#define GPR_T 0
#define SPR_T 0
#include "op_mftspr_op.h"
#undef SPR_T
#undef GPR_T
#undef GPR_T_NAME
#undef SPR_T_NAME
 
#undef ONLY_MTSPR
 
#define OP +=
#define OP_NAME mac
#include "op_mac_op.h"
#undef OP_NAME
#undef OP
 
#define OP -=
#define OP_NAME msb
#include "op_mac_op.h"
#undef OP_NAME
#undef OP
 
#define LS_OP_NAME lbz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem8
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lbs
#define LS_OP_CAST (int8_t)
#define LS_OP_FUNC eval_mem8
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lhz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem16
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lhs
#define LS_OP_CAST (int16_t)
#define LS_OP_FUNC eval_mem16
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lwz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem32
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lws
#define LS_OP_CAST (int32_t)
#define LS_OP_FUNC eval_mem32
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define S_OP_NAME sb
#define S_FUNC set_mem8
#include "op_swhb_op.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sh
#define S_FUNC set_mem16
#include "op_swhb_op.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sw
#define S_FUNC set_mem32
#include "op_swhb_op.h"
#undef S_FUNC
#undef S_OP_NAME
 
__or_dynop void op_join_mem_cycles(void)
{
  join_mem_cycles();
}
 
__or_dynop void op_store_link_addr_gpr(void)
{
  env->reg[LINK_REGNO] = get_pc() + 8;
}
 
__or_dynop void op_prep_rfe(void)
{
  env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
  env->sprs[SPR_PPC] = get_pc();
  env->ts_current = 1;
  set_pc(env->sprs[SPR_EPCR_BASE] - 4);
}
 
static inline void prep_except(oraddr_t epcr_base)
{
  env->sprs[SPR_EPCR_BASE] = epcr_base;
 
  env->sprs[SPR_ESR_BASE] = env->sprs[SPR_SR];
 
  /* Address translation is always disabled when starting exception. */
  env->sprs[SPR_SR] &= ~SPR_SR_DME;
  env->sprs[SPR_SR] &= ~SPR_SR_IME;
 
  env->sprs[SPR_SR] &= ~SPR_SR_OVE;   /* Disable overflow flag exception. */
 
  env->sprs[SPR_SR] |= SPR_SR_SM;     /* SUPV mode */
  env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE);    /* Disable interrupts. */
}
 
__or_dynop void op_set_except_pc(void)
{
  set_pc(OP_PARAM1);
}
 
/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
 * Therefore the pc will point to the instruction after the l.sys or l.trap
 * instruction */
__or_dynop void op_prep_sys_delay(void)
{
  env->delay_insn = 0;
  env->ts_current = 1;
  prep_except(get_pc() - 4);
  set_pc(EXCEPT_SYSCALL - 4);
}
 
__or_dynop void op_prep_sys(void)
{
  env->ts_current = 1;
  prep_except(get_pc() + 4);
  set_pc(EXCEPT_SYSCALL - 4);
}
 
__or_dynop void op_prep_trap_delay(void)
{
  env->ts_current = 1;
  env->delay_insn = 0;
  prep_except(get_pc() - 4);
  set_pc(EXCEPT_TRAP - 4);
}
 
__or_dynop void op_prep_trap(void)
{
  env->ts_current = 1;
  prep_except(get_pc());
  set_pc(EXCEPT_TRAP - 4);
}
 
/* FIXME: This `instruction' should be split up like the l.trap and l.sys
 * instructions are done */
__or_dynop void op_illegal_delay(void)
{
  env->delay_insn = 0;
  env->ts_current = 1;
  env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
  do_jump(EXCEPT_ILLEGAL - 4);
}
 
__or_dynop void op_illegal(void)
{
  env->sprs[SPR_EEAR_BASE] = get_pc();
  do_jump(EXCEPT_ILLEGAL);
}
 
__or_dynop void op_do_sched(void)
{
  HANDLE_SCHED(do_sched_wrap, "no_sched");
}
 
__or_dynop void op_do_sched_delay(void)
{
  HANDLE_SCHED(do_sched_wrap_delay, "no_sched_delay");
}
 
__or_dynop void op_macc(void)
{
  env->sprs[SPR_MACLO] = 0;
  env->sprs[SPR_MACHI] = 0;
}
 
__or_dynop void op_store_insn_ea(void)
{
  env->insn_ea = OP_PARAM1;
}
 

Line No.	Rev	Author	Line
1	1452	nogj	`/* op.c -- Micro operations for the recompiler`
2			Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20
21			`#include <stdio.h>`
22			`#include <stdint.h>`
23			`#include <stdlib.h>`
24
25			`#include "config.h"`
26
27			`#ifdef HAVE_INTTYPES_H`
28			`#include <inttypes.h>`
29			`#endif`
30
31			`#include "port.h"`
32			`#include "arch.h"`
33			`#include "spr_defs.h"`
34			`#include "opcode/or32.h"`
35			`#include "sim-config.h"`
36			`#include "except.h"`
37			`#include "abstract.h"`
38			`#include "execute.h"`
39			`#include "sprs.h"`
40			`#include "sched.h"`
41
42			`#include "op_support.h"`
43
44			`#include "i386_regs.h"`
45
46			`#include "dyn_rec.h"`
47
48			`/* This must be here since the function in op_i386.h use this variable */`
49			`register struct cpu_state *env asm(CPU_STATE_REG);`
50
51			`#include "op_i386.h"`
52
53			`/*`
54	1549	nogj	`* WARNING: Before going of and wildly editing everything in this file remember`
55	1452	nogj	`* the following about its contents:`
56			* 1) The `functions' don't EVER return. In otherwords haveing return state-
57			`* ments _anywere_ in this file is likely not to work. This is because`
58			`* dyngen just strips away the ret from the end of the function and just uses`
59			* the function `body'. If a ret statement is executed _anyware_ inside the
60			`* dynamicly generated code, then it is undefined were we shall jump to.`
61			`* 2) Because of 1), try not to have overly complicated functions. In too`
62			* complicated functions, gcc may decide to generate premature `exits'. This
63			`* is what passing the -fno-reorder-blocks command line switch to gcc helps`
64			`* with. This is ofcourse not desired and is rather flaky as we don't (and`
65			`* can't) control the kind of code that gcc generates: It may work for one`
66			`* and break for another. The less branches there are the less likely it is`
67			`* that a premature return shall occur.`
68			`* 3) If gcc decides that it is going to be a basterd then it will optimise a`
69			`* very simple condition (if/switch) with a premature exit. But gcc can't`
70			`* fuck ME over! Just stick a FORCE_RET; at the END of the offending`
71			`* function.`
72			* 4) All operations must start with `op_'. dyngen ignores all other functions.
73			`* 5) Local variables are depriciated: They hinder performance.`
74			`* 6) Function calls are expensive as the stack has to be shifted (twice).`
75			`*/`
76
77			`/#define __or_dynop __attribute__((noreturn))/`
78			`#define __or_dynop`
79
80			`/* Temporaries to hold the (simulated) registers in */`
81			`register uint32_t t0 asm(T0_REG);`
82			`register uint32_t t1 asm(T1_REG);`
83			`register uint32_t t2 asm(T2_REG);`
84
85			`#define OP_PARAM1 ((uorreg_t)(&__op_param1))`
86			`#define OP_PARAM2 ((uorreg_t)(&__op_param2))`
87			`#define OP_PARAM3 ((uorreg_t)(&__op_param3))`
88
89			`extern uorreg_t __op_param1;`
90			`extern uorreg_t __op_param2;`
91			`extern uorreg_t __op_param3;`
92
93
94			`/* Helper function. Whenever we escape the recompiled code and there is a`
95			`* potential that an exception may happen this function must be called */`
96			`static inline void save_t_temporary(void)`
97			`{`
98			`env->t0 = t0;`
99			`env->t1 = t1;`
100			`env->t2 = t2;`
101			`}`
102
103			`/* Wrapper around do_scheduler. This is needed because op_do_sched must be as`
104			`* small as possible. */`
105			`void do_sched_wrap(void)`
106			`{`
107			`save_t_temporary();`
108			`upd_sim_cycles();`
109			`do_scheduler();`
110			`}`
111
112	1481	nogj	`/* do_scheduler wrapper for instructions that are in the delay slot */`
113			`void do_sched_wrap_delay(void)`
114			`{`
115			`save_t_temporary();`
116			`upd_sim_cycles();`
117			`env->ts_current = 1;`
118			`/* The PC gets set to the location of the jump, but do_sched increments that`
119			`* so pull it back here to point to the right location again. This could be`
120			`* done in op_add_pc/op_set_pc_pc_delay but that would enlarge the recompiled`
121			`* code. */`
122			`//env->pc -= 4;`
123			`do_scheduler();`
124			`env->ts_current = 0;`
125			`}`
126
127			`void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)`
128			`{`
129			`uint16_t reg;`
130
131	1483	nogj	`addr &= config.immu.pagesize - 1;`
132	1481	nogj	`addr >>= 2;`
133
134			`reg = dp->ts_bound[addr];`
135
136			`if(reg & 0x1f)`
137			`t0 = cpu_state.reg[reg & 0x1f];`
138
139			`if((reg >> 5) & 0x1f)`
140			`t1 = cpu_state.reg[(reg >> 5) & 0x1f];`
141
142			`if((reg >> 10) & 0x1f)`
143			`t2 = cpu_state.reg[(reg >> 10) & 0x1f];`
144
145			`or_longjmp(dp->locs[addr]);`
146			`}`
147
148	1452	nogj
149	1481	nogj	`__or_dynop void op_set_pc_pc_delay(void)`
150	1452	nogj	`{`
151	1481	nogj	`env->sprs[SPR_PPC] = get_pc();`
152			`/* pc_delay is pulled back 4 since imediatly after this is run, the scheduler`
153			`* runs which also increments it by 4 */`
154			`set_pc(env->pc_delay - 4);`
155	1452	nogj	`}`
156
157			`__or_dynop void op_set_pc_delay_imm(void)`
158			`{`
159			`env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;`
160			`env->delay_insn = 1;`
161			`}`
162
163			`__or_dynop void op_set_pc_delay_pc(void)`
164			`{`
165			`env->pc_delay = get_pc();`
166			`env->delay_insn = 1;`
167			`}`
168
169			`__or_dynop void op_clear_pc_delay(void)`
170			`{`
171			`env->pc_delay = 0;`
172			`env->delay_insn = 1;`
173			`}`
174
175			`__or_dynop void op_do_jump(void)`
176			`{`
177	1481	nogj	`do_jump(get_pc());`
178			`}`
179
180			`__or_dynop void op_do_jump_delay(void)`
181			`{`
182	1452	nogj	`do_jump(env->pc_delay);`
183			`}`
184
185	1481	nogj	`__or_dynop void op_clear_delay_insn(void)`
186	1452	nogj	`{`
187	1481	nogj	`env->delay_insn = 0;`
188	1452	nogj	`}`
189
190	1481	nogj	`__or_dynop void op_set_delay_insn(void)`
191	1452	nogj	`{`
192	1481	nogj	`env->delay_insn = 1;`
193	1452	nogj	`}`
194
195	1481	nogj	`__or_dynop void op_check_delay_slot(void)`
196	1452	nogj	`{`
197	1481	nogj	`if(!env->delay_insn)`
198			`OP_JUMP(OP_PARAM1);`
199	1452	nogj	`}`
200
201			`__or_dynop void op_jmp_imm(void)`
202			`{`
203			`OP_JUMP(OP_PARAM1);`
204			`}`
205
206			`__or_dynop void op_set_flag(void)`
207			`{`
208			`env->sprs[SPR_SR] \|= SPR_SR_F;`
209			`}`
210
211			`__or_dynop void op_clear_flag(void)`
212			`{`
213			`env->sprs[SPR_SR] &= ~SPR_SR_F;`
214			`}`
215
216	1481	nogj	`/* Used for the l.bf instruction. Therefore if the flag is not set, jump over`
217			`* all the jumping stuff */`
218	1452	nogj	`__or_dynop void op_check_flag(void)`
219			`{`
220	1481	nogj	`if(!(env->sprs[SPR_SR] & SPR_SR_F)) {`
221			`HANDLE_SCHED(do_sched_wrap, "no_sched_chk_flg");`
222			`OP_JUMP(OP_PARAM1);`
223			`}`
224			`}`
225
226			`/* Used for l.bf if the delay slot instruction is on another page */`
227			`__or_dynop void op_check_flag_delay(void)`
228			`{`
229	1452	nogj	`if(env->sprs[SPR_SR] & SPR_SR_F) {`
230	1481	nogj	`env->delay_insn = 1;`
231	1452	nogj	`env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;`
232			`}`
233			`}`
234
235	1481	nogj	`/* Used for the l.bnf instruction. Therefore if the flag is set, jump over all`
236			`* the jumping stuff */`
237	1452	nogj	`__or_dynop void op_check_not_flag(void)`
238			`{`
239	1481	nogj	`if(env->sprs[SPR_SR] & SPR_SR_F) {`
240			`HANDLE_SCHED(do_sched_wrap, "no_sched_chk_not_flg");`
241			`OP_JUMP(OP_PARAM1);`
242			`}`
243			`}`
244
245			`/* Used for l.bnf if the delay slot instruction is on another page */`
246			`__or_dynop void op_check_not_flag_delay(void)`
247			`{`
248	1452	nogj	`if(!(env->sprs[SPR_SR] & SPR_SR_F)) {`
249	1481	nogj	`env->delay_insn = 1;`
250	1452	nogj	`env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;`
251			`}`
252			`}`
253
254			`__or_dynop void op_set_ts_current(void)`
255			`{`
256			`env->ts_current = 1;`
257			`}`
258
259	1481	nogj	`__or_dynop void op_add_pc(void)`
260	1452	nogj	`{`
261	1481	nogj	`/* FIXME: Optimise */`
262			`set_pc(get_pc() + OP_PARAM1);`
263	1452	nogj	`}`
264
265			`__or_dynop void op_nop_exit(void)`
266			`{`
267			`upd_sim_cycles();`
268			`save_t_temporary();`
269			`op_support_nop_exit();`
270			`FORCE_RET;`
271			`}`
272
273			`__or_dynop void op_nop_reset(void)`
274			`{`
275			`upd_sim_cycles();`
276			`op_support_nop_reset();`
277	1481	nogj	`do_jump(EXCEPT_RESET);`
278	1452	nogj	`}`
279
280			`__or_dynop void op_nop_printf(void)`
281			`{`
282			`save_t_temporary();`
283			`upd_sim_cycles();`
284			`op_support_nop_printf();`
285			`FORCE_RET;`
286			`}`
287
288			`__or_dynop void op_nop_report(void)`
289			`{`
290			`save_t_temporary();`
291			`upd_sim_cycles();`
292			`op_support_nop_report();`
293			`FORCE_RET;`
294			`}`
295
296			`__or_dynop void op_nop_report_imm(void)`
297			`{`
298			`save_t_temporary();`
299			`upd_sim_cycles();`
300			`op_support_nop_report_imm(OP_PARAM1);`
301			`}`
302
303	1657	nogj	`__or_dynop void op_analysis(void)`
304	1452	nogj	`{`
305	1657	nogj	`env->iqueue.insn_index = OP_PARAM1;`
306			`env->iqueue.insn = OP_PARAM2;`
307			`env->iqueue.insn_addr = get_pc();`
308			`save_t_temporary();`
309			`op_support_analysis();`
310			`FORCE_RET;`
311	1452	nogj	`}`
312
313	1657	nogj	`__or_dynop void op_move_gpr1_pc_delay(void)`
314			`{`
315			`env->pc_delay = env->reg[1];`
316			`env->delay_insn = 1;`
317			`}`
318	1452	nogj
319	1657	nogj	`__or_dynop void op_move_gpr2_pc_delay(void)`
320	1452	nogj	`{`
321	1657	nogj	`env->pc_delay = env->reg[2];`
322			`env->delay_insn = 1;`
323	1452	nogj	`}`
324
325	1657	nogj	`__or_dynop void op_move_gpr3_pc_delay(void)`
326	1452	nogj	`{`
327	1657	nogj	`env->pc_delay = env->reg[3];`
328			`env->delay_insn = 1;`
329	1452	nogj	`}`
330
331	1657	nogj	`__or_dynop void op_move_gpr4_pc_delay(void)`
332			`{`
333			`env->pc_delay = env->reg[4];`
334			`env->delay_insn = 1;`
335			`}`
336	1452	nogj
337	1657	nogj	`__or_dynop void op_move_gpr5_pc_delay(void)`
338	1452	nogj	`{`
339	1657	nogj	`env->pc_delay = env->reg[5];`
340			`env->delay_insn = 1;`
341	1452	nogj	`}`
342
343	1657	nogj	`__or_dynop void op_move_gpr6_pc_delay(void)`
344	1452	nogj	`{`
345	1657	nogj	`env->pc_delay = env->reg[6];`
346			`env->delay_insn = 1;`
347	1452	nogj	`}`
348
349	1657	nogj	`__or_dynop void op_move_gpr7_pc_delay(void)`
350	1452	nogj	`{`
351	1657	nogj	`env->pc_delay = env->reg[7];`
352			`env->delay_insn = 1;`
353	1452	nogj	`}`
354
355	1657	nogj	`__or_dynop void op_move_gpr8_pc_delay(void)`
356	1452	nogj	`{`
357	1657	nogj	`env->pc_delay = env->reg[8];`
358			`env->delay_insn = 1;`
359	1452	nogj	`}`
360
361	1657	nogj	`__or_dynop void op_move_gpr9_pc_delay(void)`
362			`{`
363			`env->pc_delay = env->reg[9];`
364			`env->delay_insn = 1;`
365			`}`
366
367			`__or_dynop void op_move_gpr10_pc_delay(void)`
368			`{`
369			`env->pc_delay = env->reg[10];`
370			`env->delay_insn = 1;`
371			`}`
372
373			`__or_dynop void op_move_gpr11_pc_delay(void)`
374			`{`
375			`env->pc_delay = env->reg[11];`
376			`env->delay_insn = 1;`
377			`}`
378
379			`__or_dynop void op_move_gpr12_pc_delay(void)`
380			`{`
381			`env->pc_delay = env->reg[12];`
382			`env->delay_insn = 1;`
383			`}`
384
385			`__or_dynop void op_move_gpr13_pc_delay(void)`
386			`{`
387			`env->pc_delay = env->reg[13];`
388			`env->delay_insn = 1;`
389			`}`
390
391			`__or_dynop void op_move_gpr14_pc_delay(void)`
392			`{`
393			`env->pc_delay = env->reg[14];`
394			`env->delay_insn = 1;`
395			`}`
396
397			`__or_dynop void op_move_gpr15_pc_delay(void)`
398			`{`
399			`env->pc_delay = env->reg[15];`
400			`env->delay_insn = 1;`
401			`}`
402
403			`__or_dynop void op_move_gpr16_pc_delay(void)`
404			`{`
405			`env->pc_delay = env->reg[16];`
406			`env->delay_insn = 1;`
407			`}`
408
409			`__or_dynop void op_move_gpr17_pc_delay(void)`
410			`{`
411			`env->pc_delay = env->reg[17];`
412			`env->delay_insn = 1;`
413			`}`
414
415			`__or_dynop void op_move_gpr18_pc_delay(void)`
416			`{`
417			`env->pc_delay = env->reg[18];`
418			`env->delay_insn = 1;`
419			`}`
420
421			`__or_dynop void op_move_gpr19_pc_delay(void)`
422			`{`
423			`env->pc_delay = env->reg[19];`
424			`env->delay_insn = 1;`
425			`}`
426
427			`__or_dynop void op_move_gpr20_pc_delay(void)`
428			`{`
429			`env->pc_delay = env->reg[20];`
430			`env->delay_insn = 1;`
431			`}`
432
433			`__or_dynop void op_move_gpr21_pc_delay(void)`
434			`{`
435			`env->pc_delay = env->reg[21];`
436			`env->delay_insn = 1;`
437			`}`
438
439			`__or_dynop void op_move_gpr22_pc_delay(void)`
440			`{`
441			`env->pc_delay = env->reg[22];`
442			`env->delay_insn = 1;`
443			`}`
444
445			`__or_dynop void op_move_gpr23_pc_delay(void)`
446			`{`
447			`env->pc_delay = env->reg[23];`
448			`env->delay_insn = 1;`
449			`}`
450
451			`__or_dynop void op_move_gpr24_pc_delay(void)`
452			`{`
453			`env->pc_delay = env->reg[24];`
454			`env->delay_insn = 1;`
455			`}`
456
457			`__or_dynop void op_move_gpr25_pc_delay(void)`
458			`{`
459			`env->pc_delay = env->reg[25];`
460			`env->delay_insn = 1;`
461			`}`
462
463			`__or_dynop void op_move_gpr26_pc_delay(void)`
464			`{`
465			`env->pc_delay = env->reg[26];`
466			`env->delay_insn = 1;`
467			`}`
468
469			`__or_dynop void op_move_gpr27_pc_delay(void)`
470			`{`
471			`env->pc_delay = env->reg[27];`
472			`env->delay_insn = 1;`
473			`}`
474
475			`__or_dynop void op_move_gpr28_pc_delay(void)`
476			`{`
477			`env->pc_delay = env->reg[28];`
478			`env->delay_insn = 1;`
479			`}`
480
481			`__or_dynop void op_move_gpr29_pc_delay(void)`
482			`{`
483			`env->pc_delay = env->reg[29];`
484			`env->delay_insn = 1;`
485			`}`
486
487			`__or_dynop void op_move_gpr30_pc_delay(void)`
488			`{`
489			`env->pc_delay = env->reg[30];`
490			`env->delay_insn = 1;`
491			`}`
492
493			`__or_dynop void op_move_gpr31_pc_delay(void)`
494			`{`
495			`env->pc_delay = env->reg[31];`
496			`env->delay_insn = 1;`
497			`}`
498
499			`#define OP_FILE "op_1t_op.h"`
500			`#include "op_1t.h"`

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