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/* dmmu.c -- Data MMU simulation
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* DMMU model (not functional yet, currently just copy of data cache). */
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "dmmu.h"
#include "abstract.h"
#include "opcode/or32.h"
#include "spr_defs.h"
#include "execute.h"
#include "stats.h"
#include "sprs.h"
#include "except.h"
#include "sim-config.h"
#include "debug.h"
 
DEFAULT_DEBUG_CHANNEL(dmmu);
 
extern int cont_run;
 
/* Data MMU */
 
inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)
{
  int set, way = -1;
  int i;
  oraddr_t tagaddr;
  oraddr_t vpn, ppn;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
    data_ci = (virtaddr >= 0x80000000);
    return virtaddr;
  }
 
  /* Which set to check out? */
  set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
  tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
  vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
 
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.dmmu.nways; i++)
    if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
        (cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))
      way = i;
 
   /* Did we find our tlb entry? */
  if (way >= 0) { /* Yes, we did. */
    dmmu_stats.loads_tlbhit++;
    TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
          runtime.sim.cycles);
 
    /* Set LRUs */
    for (i = 0; i < config.dmmu.nways; i++) {
      uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];
      if (lru & SPR_DTLBMR_LRU) {
        lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
        cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;
      }
    }
    cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
    cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
 
    /* Check if page is cache inhibited */
    data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
 
    runtime.sim.mem_cycles += config.dmmu.hitdelay;
    ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize;
 
    /* Test for page fault */
    if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
      if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE)
       || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE))
        except_handle(EXCEPT_DPF, virtaddr);
    } else {
      if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE)
       || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE))
        except_handle(EXCEPT_DPF, virtaddr);
    }
 
    return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
  }
  else {  /* No, we didn't. */
    dmmu_stats.loads_tlbmiss++;
#if 0
    for (i = 0; i < config.dmmu.nways; i++)
      if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_LRU) >> 6) < minlru)
        minway = i;
 
    cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] &= ~SPR_DTLBMR_VPN;
    cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= vpn << 12;
    for (i = 0; i < config.dmmu.nways; i++) {
      uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];
      if (lru & SPR_DTLBMR_LRU) {
        lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
        cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;
      }
    }
    cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
    cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
 
    /* 1 to 1 mapping */
    cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] &= ~SPR_DTLBTR_PPN;
    cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] |= vpn << 12;
 
    cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= SPR_DTLBMR_V;
#endif
    TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
          runtime.sim.cycles);
    runtime.sim.mem_cycles += config.dmmu.missdelay;
    /* if tlb refill implemented in HW */
    /* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
    except_handle(EXCEPT_DTLBMISS, virtaddr);
    return 0;
  }
}
 
/* DESC: try to find EA -> PA transaltion without changing
 *       any of precessor states. if this is not passible gives up
 *       (without triggering exceptions)
 *
 * PRMS: virtaddr     - EA for which to find translation
 *
 *       write_access - 0 ignore testing for write access
 *                      1 test for write access, if fails
 *                        do not return translation
 *
 *       through_dc   - 1 go through data cache
 *                      0 ignore data cache
 *
 * RTRN: 0            - no DMMU, DMMU disabled or ITLB miss
 *       else         - appropriate PA (note it DMMU is not present
 *                      PA === EA)
 */
oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
{
  int set, way = -1;
  int i;
  oraddr_t tagaddr;
  oraddr_t vpn, ppn;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
    if (through_dc)
      data_ci = (virtaddr >= 0x80000000);
    return virtaddr;
  }
 
  /* Which set to check out? */
  set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
  tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
  vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
 
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.dmmu.nways; i++)
    if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
        (cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))
      way = i;
 
   /* Did we find our tlb entry? */
  if (way >= 0) { /* Yes, we did. */
    dmmu_stats.loads_tlbhit++;
    TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
          runtime.sim.cycles);
 
    /* Test for page fault */
    if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
      if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE)
       || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE))
 
        /* otherwise exception DPF would be raised */
        return(0);
    } else {
      if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE)
       || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE))
 
        /* otherwise exception DPF would be raised */
        return(0);
    }
 
    if (through_dc) {
      /* Check if page is cache inhibited */
      data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
    }
 
    ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize;
    return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
  }
  else {  /* No, we didn't. */
    return(0);
  }
 
  ERR("ERR, should never have happened\n");
  return(0);
}
 
 
oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
{
  oraddr_t phyaddr = dmmu_simulate_tlb(virtaddr, write_access);
 
/*  PRINTF("DMMU translate(%"PRIxADDR") = %"PRIxADDR"\n", virtaddr, phyaddr);*/
  return phyaddr;
}
 
 
void dtlb_info(void)
{
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
    PRINTF("DMMU not implemented. Set UPR[DMP].\n");
    return;
  }
 
  PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);
  PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);
}
 
/* First check if virtual address is covered by DTLB and if it is:
    - increment DTLB read hit stats,
    - set 'lru' at this way to config.dmmu.ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
    - check page access attributes and invoke DMMU page fault exception
      handler if necessary
   and if not:
    - increment DTLB read miss stats
    - find lru way and entry and invoke DTLB miss exception handler
    - set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/
 
void dtlb_status(int start_set)
{
  int set;
  int way;
  int end_set = config.dmmu.nsets;
 
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
    PRINTF("DMMU not implemented. Set UPR[DMP].\n");
    return;
  }
 
  if ((start_set >= 0) && (start_set < end_set))
    end_set = start_set + 1;
  else
    start_set = 0;
 
  if (start_set < end_set) PRINTF("\nDMMU: ");
  /* Scan set(s) and way(s). */
  for (set = start_set; set < end_set; set++) {
    PRINTF("\nSet %x: ", set);
    for (way = 0; way < config.dmmu.nways; way++) {
      PRINTF("  way %d: ", way);
      PRINTF("%s\n", dump_spr(SPR_DTLBMR_BASE(way) + set,
                              cpu_state.sprs[SPR_DTLBMR_BASE(way) + set]));
      PRINTF("%s\n", dump_spr(SPR_DTLBTR_BASE(way) + set,
                              cpu_state.sprs[SPR_DTLBTR_BASE(way) + set]));
    }
  }
  if (start_set < end_set) PRINTF("\n");
}
 
/*---------------------------------------------------[ DMMU configuration ]---*/
void dmmu_enabled(union param_val val, void *dat)
{
  if(val.int_val)
    cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
  else
    cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
  config.dmmu.enabled = val.int_val;
}
 
void dmmu_nsets(union param_val val, void *dat)
{
  if (is_power2(val.int_val) && val.int_val <= 256) {
    config.dmmu.nsets = val.int_val;
    cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
    cpu_state.sprs[SPR_DMMUCFGR] |= log2(val.int_val) << 3;
  } else
    CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
}
 
void dmmu_nways(union param_val val, void *dat)
{
  if (val.int_val >= 1 && val.int_val <= 4) {
    config.dmmu.nways = val.int_val;
    cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
    cpu_state.sprs[SPR_DMMUCFGR] |= val.int_val - 1;
  }
  else
    CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
}
 
void dmmu_pagesize(union param_val val, void *dat)
{
  if (is_power2(val.int_val))
    config.dmmu.pagesize = val.int_val;
  else
    CONFIG_ERROR("value of power of two expected.");
}
 
void dmmu_entrysize(union param_val val, void *dat)
{
  if (is_power2(val.int_val))
    config.dmmu.entrysize = val.int_val;
  else
    CONFIG_ERROR("value of power of two expected.");
}
 
void dmmu_ustates(union param_val val, void *dat)
{
  if (val.int_val >= 2 && val.int_val <= 4)
    config.dmmu.ustates = val.int_val;
  else
    CONFIG_ERROR("invalid USTATE.");
}
 
void dmmu_missdelay(union param_val val, void *dat)
{
  config.dmmu.missdelay = val.int_val;
}
 
void dmmu_hitdelay(union param_val val, void *dat)
{
  config.immu.hitdelay = val.int_val;
}
 
void reg_dmmu_sec(void)
{
  struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);
 
  reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);
  reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);
  reg_config_param(sec, "nways", paramt_int, dmmu_nways);
  reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);
  reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);
  reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);
  reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);
  reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);
}

Line No.	Rev	Author	Line
1	62	lampret	`/* dmmu.c -- Data MMU simulation`
2	6	lampret	`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* DMMU model (not functional yet, currently just copy of data cache). */`
21
22	1350	nogj	`#include "config.h"`
23
24			`#ifdef HAVE_INTTYPES_H`
25			`#include <inttypes.h>`
26			`#endif`
27
28			`#include "port.h"`
29			`#include "arch.h"`
30	6	lampret	`#include "dmmu.h"`
31			`#include "abstract.h"`
32	1344	nogj	`#include "opcode/or32.h"`
33	1432	nogj	`#include "spr_defs.h"`
34			`#include "execute.h"`
35	6	lampret	`#include "stats.h"`
36	62	lampret	`#include "sprs.h"`
37			`#include "except.h"`
38	425	markom	`#include "sim-config.h"`
39	1308	phoenix	`#include "debug.h"`
40	6	lampret
41	1412	nogj	`DEFAULT_DEBUG_CHANNEL(dmmu);`
42
43	62	lampret	`extern int cont_run;`
44
45	6	lampret	`/* Data MMU */`
46
47	1350	nogj	`inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)`
48	6	lampret	`{`
49	430	markom	`int set, way = -1;`
50			`int i;`
51	1350	nogj	`oraddr_t tagaddr;`
52			`oraddr_t vpn, ppn;`
53	572	simons
54	1506	nogj	`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) \|\|`
55			`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {`
56	638	simons	`data_ci = (virtaddr >= 0x80000000);`
57	430	markom	`return virtaddr;`
58	638	simons	`}`
59	430	markom
60			`/* Which set to check out? */`
61			`set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;`
62			`tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;`
63	456	simons	`vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);`
64
65	430	markom	`/* Scan all ways and try to find a matching way. */`
66			`for (i = 0; i < config.dmmu.nways; i++)`
67	1508	nogj	`if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&`
68	1506	nogj	`(cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))`
69	430	markom	`way = i;`
70	456	simons
71			`/* Did we find our tlb entry? */`
72	430	markom	`if (way >= 0) { /* Yes, we did. */`
73			`dmmu_stats.loads_tlbhit++;`
74	1412	nogj	`TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,`
75			`runtime.sim.cycles);`
76	430	markom
77	1414	nogj	`/* Set LRUs */`
78	1506	nogj	`for (i = 0; i < config.dmmu.nways; i++) {`
79			`uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];`
80			`if (lru & SPR_DTLBMR_LRU) {`
81			`lru = (lru & ~SPR_DTLBMR_LRU) \| ((lru & SPR_DTLBMR_LRU) - 0x40);`
82			`cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;`
83			`}`
84			`}`
85			`cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;`
86			`cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] \|= (config.dmmu.nsets - 1) << 6;`
87	1414	nogj
88			`/* Check if page is cache inhibited */`
89	1508	nogj	`data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;`
90	1414	nogj
91			`runtime.sim.mem_cycles += config.dmmu.hitdelay;`
92	1508	nogj	`ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize;`
93	1414	nogj
94	430	markom	`/* Test for page fault */`
95	1508	nogj	`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {`
96			`if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE)`
97			`\|\| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE))`
98	430	markom	`except_handle(EXCEPT_DPF, virtaddr);`
99			`} else {`
100	1508	nogj	`if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE)`
101			`\|\| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE))`
102	430	markom	`except_handle(EXCEPT_DPF, virtaddr);`
103			`}`
104
105	456	simons	`return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);`
106	430	markom	`}`
107			`else { /* No, we didn't. */`
108			`dmmu_stats.loads_tlbmiss++;`
109			`#if 0`
110			`for (i = 0; i < config.dmmu.nways; i++)`
111	1506	nogj	`if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_LRU) >> 6) < minlru)`
112	430	markom	`minway = i;`
113
114	1506	nogj	`cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] &= ~SPR_DTLBMR_VPN;`
115			`cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] \|= vpn << 12;`
116			`for (i = 0; i < config.dmmu.nways; i++) {`
117			`uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];`
118			`if (lru & SPR_DTLBMR_LRU) {`
119			`lru = (lru & ~SPR_DTLBMR_LRU) \| ((lru & SPR_DTLBMR_LRU) - 0x40);`
120			`cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;`
121			`}`
122			`}`
123			`cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;`
124			`cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] \|= (config.dmmu.nsets - 1) << 6;`
125
126			`/* 1 to 1 mapping */`
127			`cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] &= ~SPR_DTLBTR_PPN;`
128			`cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] \|= vpn << 12;`
129
130			`cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] \|= SPR_DTLBMR_V;`
131	430	markom	`#endif`
132	1412	nogj	`TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,`
133			`runtime.sim.cycles);`
134	1414	nogj	`runtime.sim.mem_cycles += config.dmmu.missdelay;`
135	430	markom	`/* if tlb refill implemented in HW */`
136	1506	nogj	`/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */`
137	1414	nogj	`except_handle(EXCEPT_DTLBMISS, virtaddr);`
138	430	markom	`return 0;`
139			`}`
140			`}`
141
142	1240	phoenix	`/* DESC: try to find EA -> PA transaltion without changing`
143			`* any of precessor states. if this is not passible gives up`
144			`* (without triggering exceptions)`
145			`*`
146			`* PRMS: virtaddr - EA for which to find translation`
147			`*`
148			`* write_access - 0 ignore testing for write access`
149			`* 1 test for write access, if fails`
150			`* do not return translation`
151			`*`
152			`* through_dc - 1 go through data cache`
153			`* 0 ignore data cache`
154			`*`
155			`* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss`
156			`* else - appropriate PA (note it DMMU is not present`
157			`* PA === EA)`
158			`*/`
159	1350	nogj	`oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)`
160	1240	phoenix	`{`
161			`int set, way = -1;`
162			`int i;`
163	1350	nogj	`oraddr_t tagaddr;`
164			`oraddr_t vpn, ppn;`
165	1240	phoenix
166	1506	nogj	`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) \|\|`
167			`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {`
168	1240	phoenix	`if (through_dc)`
169			`data_ci = (virtaddr >= 0x80000000);`
170			`return virtaddr;`
171			`}`
172
173			`/* Which set to check out? */`
174			`set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;`
175			`tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;`
176			`vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);`
177
178			`/* Scan all ways and try to find a matching way. */`
179			`for (i = 0; i < config.dmmu.nways; i++)`
180	1508	nogj	`if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&`
181	1506	nogj	`(cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))`
182	1240	phoenix	`way = i;`
183
184			`/* Did we find our tlb entry? */`
185			`if (way >= 0) { /* Yes, we did. */`
186			`dmmu_stats.loads_tlbhit++;`
187	1412	nogj	`TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,`
188			`runtime.sim.cycles);`
189	1240	phoenix
190			`/* Test for page fault */`
191	1508	nogj	`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {`
192			`if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE)`
193			`\|\| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE))`
194	1240	phoenix
195			`/* otherwise exception DPF would be raised */`
196			`return(0);`
197			`} else {`
198	1508	nogj	`if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE)`
199			`\|\| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE))`
200	1240	phoenix
201			`/* otherwise exception DPF would be raised */`
202			`return(0);`
203			`}`
204
205			`if (through_dc) {`
206			`/* Check if page is cache inhibited */`
207	1508	nogj	`data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;`
208	1240	phoenix	`}`
209
210	1508	nogj	`ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize;`
211	1240	phoenix	`return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);`
212			`}`
213			`else { /* No, we didn't. */`
214			`return(0);`
215			`}`
216
217	1412	nogj	`ERR("ERR, should never have happened\n");`
218	1240	phoenix	`return(0);`
219			`}`
220
221
222	1350	nogj	`oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)`
223	430	markom	`{`
224	1350	nogj	`oraddr_t phyaddr = dmmu_simulate_tlb(virtaddr, write_access);`
225	429	markom
226	1350	nogj	`/* PRINTF("DMMU translate(%"PRIxADDR") = %"PRIxADDR"\n", virtaddr, phyaddr);*/`
227	429	markom	`return phyaddr;`
228	6	lampret	`}`
229
230
231	1506	nogj	`void dtlb_info(void)`
232	6	lampret	`{`
233	1506	nogj	`if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {`
234	997	markom	`PRINTF("DMMU not implemented. Set UPR[DMP].\n");`
235	429	markom	`return;`
236			`}`
237
238	997	markom	`PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);`
239			`PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);`
240	6	lampret	`}`
241
242	62	lampret	`/* First check if virtual address is covered by DTLB and if it is:`
243			`- increment DTLB read hit stats,`
244	425	markom	`- set 'lru' at this way to config.dmmu.ustates - 1 and`
245	6	lampret	`decrement 'lru' of other ways unless they have reached 0,`
246	62	lampret	`- check page access attributes and invoke DMMU page fault exception`
247			`handler if necessary`
248	6	lampret	`and if not:`
249	62	lampret	`- increment DTLB read miss stats`
250			`- find lru way and entry and invoke DTLB miss exception handler`
251	425	markom	`- set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other`
252	6	lampret	`ways unless they have reached 0`
253			`*/`
254
255	102	lampret	`void dtlb_status(int start_set)`
256	6	lampret	`{`
257	429	markom	`int set;`
258			`int way;`
259			`int end_set = config.dmmu.nsets;`
260	62	lampret
261	1506	nogj	`if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {`
262	997	markom	`PRINTF("DMMU not implemented. Set UPR[DMP].\n");`
263	429	markom	`return;`
264			`}`
265	102	lampret
266	429	markom	`if ((start_set >= 0) && (start_set < end_set))`
267			`end_set = start_set + 1;`
268			`else`
269			`start_set = 0;`
270	62	lampret
271	997	markom	`if (start_set < end_set) PRINTF("\nDMMU: ");`
272	429	markom	`/* Scan set(s) and way(s). */`
273			`for (set = start_set; set < end_set; set++) {`
274	997	markom	`PRINTF("\nSet %x: ", set);`
275	429	markom	`for (way = 0; way < config.dmmu.nways; way++) {`
276	997	markom	`PRINTF(" way %d: ", way);`
277	1532	nogj	`PRINTF("%s\n", dump_spr(SPR_DTLBMR_BASE(way) + set,`
278			`cpu_state.sprs[SPR_DTLBMR_BASE(way) + set]));`
279			`PRINTF("%s\n", dump_spr(SPR_DTLBTR_BASE(way) + set,`
280			`cpu_state.sprs[SPR_DTLBTR_BASE(way) + set]));`
281	429	markom	`}`
282			`}`
283	997	markom	`if (start_set < end_set) PRINTF("\n");`
284	6	lampret	`}`
285	1358	nogj
286			`/---------------------------------------------------[ DMMU configuration ]---/`
287			`void dmmu_enabled(union param_val val, void *dat)`
288			`{`
289	1506	nogj	`if(val.int_val)`
290			`cpu_state.sprs[SPR_UPR] \|= SPR_UPR_DMP;`
291			`else`
292			`cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;`
293	1358	nogj	`config.dmmu.enabled = val.int_val;`
294			`}`
295
296			`void dmmu_nsets(union param_val val, void *dat)`
297			`{`
298	1382	nogj	`if (is_power2(val.int_val) && val.int_val <= 256) {`
299	1358	nogj	`config.dmmu.nsets = val.int_val;`
300	1506	nogj	`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;`
301			`cpu_state.sprs[SPR_DMMUCFGR] \|= log2(val.int_val) << 3;`
302			`} else`
303	1358	nogj	`CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");`
304			`}`
305
306			`void dmmu_nways(union param_val val, void *dat)`
307			`{`
308	1382	nogj	`if (val.int_val >= 1 && val.int_val <= 4) {`
309	1358	nogj	`config.dmmu.nways = val.int_val;`
310	1506	nogj	`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;`
311			`cpu_state.sprs[SPR_DMMUCFGR] \|= val.int_val - 1;`
312	1382	nogj	`}`
313	1358	nogj	`else`
314			`CONFIG_ERROR("value 1, 2, 3 or 4 expected.");`
315			`}`
316
317			`void dmmu_pagesize(union param_val val, void *dat)`
318			`{`
319			`if (is_power2(val.int_val))`
320			`config.dmmu.pagesize = val.int_val;`
321			`else`
322			`CONFIG_ERROR("value of power of two expected.");`
323			`}`
324
325			`void dmmu_entrysize(union param_val val, void *dat)`
326			`{`
327			`if (is_power2(val.int_val))`
328			`config.dmmu.entrysize = val.int_val;`
329			`else`
330			`CONFIG_ERROR("value of power of two expected.");`
331			`}`
332
333			`void dmmu_ustates(union param_val val, void *dat)`
334			`{`
335			`if (val.int_val >= 2 && val.int_val <= 4)`
336			`config.dmmu.ustates = val.int_val;`
337			`else`
338			`CONFIG_ERROR("invalid USTATE.");`
339			`}`
340
341			`void dmmu_missdelay(union param_val val, void *dat)`
342			`{`
343			`config.dmmu.missdelay = val.int_val;`
344			`}`
345
346			`void dmmu_hitdelay(union param_val val, void *dat)`
347			`{`
348			`config.immu.hitdelay = val.int_val;`
349			`}`
350
351			`void reg_dmmu_sec(void)`
352			`{`
353			`struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);`
354
355			`reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);`
356			`reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);`
357			`reg_config_param(sec, "nways", paramt_int, dmmu_nways);`
358			`reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);`
359			`reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);`
360			`reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);`
361			`reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);`
362			`reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);`
363			`}`

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