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[/] [or1k/] [trunk/] [or1ksim/] [peripheral/] [16450.h] - Blame information for rev 235

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1 31 lampret
/* 16450.h -- Definition of types and structures for 8250/16450 serial UART
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   Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Prototypes */
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void uart_reset();
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void uart_clock();
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/* Registers */
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struct dev_16450 {
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        struct {
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                unsigned char txbuf;
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                unsigned char rxbuf;
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                unsigned char dll;
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                unsigned char dlh;
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                unsigned char ier;
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                unsigned char iir;
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                unsigned char lcr;
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                unsigned char mcr;
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                unsigned char lsr;
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                unsigned char msr;
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                unsigned char scr;
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        } regs;         /* Visible registers */
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        struct {
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                unsigned char txser;
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                unsigned char rxser;
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                unsigned char loopback;
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        } iregs;        /* Internal registers */
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        struct {
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                unsigned char txser;
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                unsigned char rxser;
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                unsigned char txbuf;
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                unsigned char rxbuf;
50 221 markom
                unsigned char thre_int;
51 31 lampret
                unsigned long txser_clks;
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                unsigned long rxser_clks;
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        } istat;        /* Internal status */
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        unsigned long char_clks;
55 221 markom
        FILE * rxfs;
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        FILE * txfs;
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        unsigned long baseaddr;
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};
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/* Definitions */
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#define FULL            1
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#define EMPTY           0
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#define UART_ADDR_SPACE 8       /* UART memory address space size in bytes */
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/*
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 * Addresses of visible registers
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 *
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 */
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#define UART_RXBUF      0        /* R: Rx buffer, DLAB=0 */
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#define UART_TXBUF      0        /* W: Tx buffer, DLAB=0 */
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#define UART_DLL        0        /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLH        1       /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_IER        1       /* R/W: Interrupt Enable Register */
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#define UART_IIR        2       /* R: Interrupt ID Register */
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#define UART_LCR        3       /* R/W: Line Control Register */
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#define UART_MCR        4       /* R/W: Modem Control Register */
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#define UART_LSR        5       /* R: Line Status Register */
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#define UART_MSR        6       /* R: Modem Status Register */
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#define UART_SCR        7       /* R/W: Scratch Register */
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/*
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 * R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)
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 *
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 */
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#define UART_VALID_LCR  0xff
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#define UART_VALID_LSR  0x7f
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#define UART_VALID_IIR  0x07
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#define UART_VALID_IER  0x0f
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#define UART_VALID_MCR  0x1f
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#define UART_VALID_MSR  0xff
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/*
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 * Bit definitions for the Line Control Register
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 *
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 */
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#define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
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#define UART_LCR_SBC    0x40    /* Set break control */
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#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
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#define UART_LCR_EPAR   0x10    /* Even parity select */
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#define UART_LCR_PARITY 0x08    /* Parity Enable */
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#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
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/*
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 * Bit definitions for the Line Status Register
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 */
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#define UART_LSR_TXSERE 0x40    /* Transmitter serial register empty */
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#define UART_LSR_TXBUFE 0x20    /* Transmitter buffer register empty */
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#define UART_LSR_BREAK  0x10    /* Break interrupt indicator */
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#define UART_LSR_FRAME  0x08    /* Frame error indicator */
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#define UART_LSR_PARITY 0x04    /* Parity error indicator */
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#define UART_LSR_OVRRUN 0x02    /* Overrun error indicator */
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#define UART_LSR_RDRDY  0x01    /* Receiver data ready */
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/*
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 * Bit definitions for the Interrupt Identification Register
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 */
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#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
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#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
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#define UART_IIR_MSI    0x00    /* Modem status interrupt (Low priority) */
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#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
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#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
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#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt (High p.) */
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/*
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 * Bit definitions for the Interrupt Enable Register
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 */
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#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
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#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
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#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
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#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
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/*
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 * Bit definitions for the Modem Control Register
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 */
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#define UART_MCR_LOOP   0x10    /* Enable loopback mode */
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#define UART_MCR_AUX2   0x08    /* Auxilary 2  */
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#define UART_MCR_AUX1   0x04    /* Auxilary 1 */
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#define UART_MCR_RTS    0x02    /* Force RTS */
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#define UART_MCR_DTR    0x01    /* Force DTR */
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/*
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 * Bit definitions for the Modem Status Register
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 */
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#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
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#define UART_MSR_RI     0x40    /* Ring Indicator */
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#define UART_MSR_DSR    0x20    /* Data Set Ready */
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#define UART_MSR_CTS    0x10    /* Clear to Send */
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#define UART_MSR_DDCD   0x08    /* Delta DCD */
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#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
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#define UART_MSR_DDSR   0x02    /* Delta DSR */
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#define UART_MSR_DCTS   0x01    /* Delta CTS */
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