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[/] [or1k/] [trunk/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 1390

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 1308 phoenix 
#include <netinet/in.h>
33 696 ivang 
 
34 867 markom 
#include "config.h"
35 1350 nogj 
 
36 
#ifdef HAVE_INTTYPES_H
37 
#include <inttypes.h>
38 
#endif
39 
 
40 
#include "port.h"
41 
#include "arch.h"
42 
#include "config.h"
43 696 ivang 
#include "abstract.h"
44 
#include "ethernet_i.h"
45 
#include "dma.h"
46 
#include "sim-config.h"
47 
#include "fields.h"
48 
#include "crc32.h"
49 889 ivang 
#include "vapi.h"
50 1308 phoenix 
#include "pic.h"
51 1372 nogj 
#include "sched.h"
52 1308 phoenix 
#include "debug.h"
53 696 ivang 
 
54 702 ivang 
/* simulator interface */
55 1366 nogj 
static void eth_vapi_read( unsigned long id, unsigned long data, void *dat);
56 696 ivang 
/* register interface */
57 1359 nogj 
static void eth_write32( oraddr_t addr, uint32_t value, void *dat );
58 
static uint32_t eth_read32( oraddr_t addr, void *dat );
59 696 ivang 
/* clock */
60 1372 nogj 
static void eth_controller_tx_clock( void * );
61 
static void eth_controller_rx_clock( void * );
62 696 ivang 
/* utility functions */
63 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
64 
static void eth_skip_rx_file( struct eth_device *, off_t );
65 
static void eth_rewind_rx_file( struct eth_device *, off_t );
66 
static void eth_rx_next_packet( struct eth_device * );
67 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
68 696 ivang 
/* ========================================================================= */
69 702 ivang 
/*  TX LOGIC                                                                 */
70 696 ivang 
/*---------------------------------------------------------------------------*/
71 
 
72 
/*
73 
 * TX clock
74 
 * Responsible for starting and finishing TX
75 
 */
76 1372 nogj 
void eth_controller_tx_clock( void *dat )
77 696 ivang 
{
78 1372 nogj 
    struct eth_device *eth = dat;
79 702 ivang 
    int breakpoint = 0;
80 
    int bAdvance   = 1;
81 867 markom 
#if HAVE_ETH_PHY
82 702 ivang 
    struct sockaddr_ll sll;
83 849 markom 
#endif /* HAVE_ETH_PHY */
84 702 ivang 
    long nwritten;
85 
    unsigned long read_word;
86 696 ivang 
 
87 
    switch (eth->tx.state) {
88 1372 nogj 
    case ETH_TXSTATE_IDLE:
89 
        debug (3, "TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
90 
        eth->tx.state = ETH_TXSTATE_WAIT4BD;
91 702 ivang 
        break;
92 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
93 702 ivang 
        /* Read buffer descriptor */
94 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
95 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
96 
 
97 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
98 
            /*****************/
99 
            /* initialize TX */
100 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
101 
            eth->tx.bytes_sent = 0;
102 
 
103 
            /*   Initialize error status bits */
104 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
105 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
106 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
107 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
108 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
109 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
110 
 
111 
            /* Find out minimum length */
112 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
113 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
114 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
115 
            else
116 
                eth->tx.minimum_length = eth->tx.packet_length;
117 
 
118 
            /* Find out maximum length */
119 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
120 
                eth->tx.maximum_length = eth->tx.packet_length;
121 
            else
122 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
123 
 
124 
            /* Do we need CRC on this packet? */
125 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
126 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
127 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
128 
                eth->tx.add_crc = 1;
129 
            else
130 
                eth->tx.add_crc = 0;
131 
 
132 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
133 
                eth->tx.crc_dly = 1;
134 
            else
135 
                eth->tx.crc_dly = 0;
136 
            /* XXX - For now we skip CRC calculation */
137 
 
138 1350 nogj 
            debug( 3, "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
139 
                   eth->tx.packet_length, eth->tx.minimum_length,
140 
                   eth->tx.maximum_length );
141 702 ivang 
 
142 
            if (eth->rtx_type == ETH_RTX_FILE) {
143 
                /* write packet length to file */
144 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
145 
            }
146 
 
147 
            /************************************************/
148 
            /* start transmit with reading packet into FIFO */
149 
                debug (3, "TX - entering state READFIFO\n");
150 
            eth->tx.state = ETH_TXSTATE_READFIFO;
151 
        }
152 
 
153 
        /* stay in this state if (TXEN && !READY) */
154 
        break;
155 696 ivang 
    case ETH_TXSTATE_READFIFO:
156 744 simons 
#if 1
157 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
158 1241 phoenix 
            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
159 702 ivang 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
160 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
161 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
162 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
163 
            eth->tx.bytes_sent += 4;
164 
        }
165 744 simons 
#else
166 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
167 1241 phoenix 
            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
168 744 simons 
            eth->tx.bytes_sent += 1;
169 
        }
170 
#endif
171 702 ivang 
        else {
172 
            debug (3, "TX - entering state TRANSMIT\n");
173 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
174 
        }
175 
        break;
176 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
177 702 ivang 
        /* send packet */
178 
        switch (eth->rtx_type) {
179 
        case ETH_RTX_FILE:
180 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
181 
            break;
182 867 markom 
#if HAVE_ETH_PHY
183 702 ivang 
        case ETH_RTX_SOCK:
184 
            memset(&sll, 0, sizeof(sll));
185 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
186 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
187 849 markom 
#endif /* HAVE_ETH_PHY */
188 702 ivang 
        }
189 
 
190 
        /* set BD status */
191 
        if (nwritten == eth->tx.packet_length) {
192 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
193 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
194 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
195 702 ivang 
 
196 1372 nogj 
            debug (3, "TX - entering state WAIT4BD\n");
197 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
198 1350 nogj 
            debug (3, "send (%ld)bytes OK\n", nwritten);
199 702 ivang 
        }
200 
        else {
201 
            /* XXX - implement retry mechanism here! */
202 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
203 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
204 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
205 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
206 702 ivang 
 
207 1372 nogj 
            debug (3, "TX - entering state WAIT4BD\n");
208 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
209 702 ivang 
            debug (3, "send FAILED!\n");
210 
        }
211 
 
212 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
213 
 
214 889 ivang 
        /* generate OK interrupt */
215 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
216 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
217 
        {
218 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )
219 
                report_interrupt( eth->mac_int );
220 
        }
221 
 
222 702 ivang 
        /* advance to next BD */
223 
        if (bAdvance) {
224 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
225 
                            eth->tx.bd_index >= ETH_BD_COUNT )
226 
                eth->tx.bd_index = 0;
227 
            else
228 
                eth->tx.bd_index += 2;
229 
        }
230 
 
231 
        break;
232 696 ivang 
    }
233 1372 nogj 
 
234 
    /* Reschedule */
235 1390 nogj 
    SCHED_ADD( eth_controller_tx_clock, dat, 1 );
236 696 ivang 
}
237 
/* ========================================================================= */
238 
 
239 
 
240 
/* ========================================================================= */
241 702 ivang 
/*  RX LOGIC                                                                 */
242 696 ivang 
/*---------------------------------------------------------------------------*/
243 
 
244 
/*
245 
 * RX clock
246 
 * Responsible for starting and finishing RX
247 
 */
248 1372 nogj 
void eth_controller_rx_clock( void *dat )
249 696 ivang 
{
250 1372 nogj 
    struct eth_device *eth = dat;
251 702 ivang 
    int breakpoint = 0;
252 
    long nread;
253 
    unsigned long send_word;
254 
 
255 
 
256 696 ivang 
    switch (eth->rx.state) {
257 
    case ETH_RXSTATE_IDLE:
258 1372 nogj 
        debug (3, "RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
259 
        eth->rx.state = ETH_RXSTATE_WAIT4BD;
260 702 ivang 
        break;
261 
 
262 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
263 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
264 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
265 
 
266 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
267 
            /*****************/
268 
            /* Initialize RX */
269 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
270 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
271 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
272 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
273 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
274 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
275 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
276 
 
277 
            debug( 3,  "Ethernet: Starting RX\n" );
278 
 
279 
            /* Setup file to read from */
280 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
281 
                eth->rx.fd = eth->txfd;
282 
                eth->rx.offset = &(eth->loopback_offset);
283 
            } else {
284 
                eth->rx.fd = eth->rxfd;
285 
                eth->rx.offset = 0;
286 
            }
287 889 ivang 
            debug (3, "RX - entering state RECV\n");
288 702 ivang 
            eth->rx.state = ETH_RXSTATE_RECV;
289 
        }
290 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
291 
          debug (3, "RX - entering state IDLE\n");
292 
          eth->rx.state = ETH_RXSTATE_IDLE;
293 
        }
294 
        else {
295 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
296 705 ivang 
            if (nread > 0) {
297 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
298 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
299 
                  report_interrupt(eth->mac_int);
300 702 ivang 
            }
301 
        }
302 
        break;
303 
 
304 696 ivang 
    case ETH_RXSTATE_RECV:
305 702 ivang 
        switch (eth->rtx_type) {
306 
        case ETH_RTX_FILE:
307 
            /* Read packet length */
308 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
309 
                     < sizeof(eth->rx.packet_length) ) {
310 
                /* TODO: just do what real ethernet would do (some kind of error state) */
311 1350 nogj 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );
312 884 markom 
                runtime.sim.cont_run = 0;
313 702 ivang 
                break;
314 
            }
315 
 
316 
            /* Packet must be big enough to hold a header */
317 1244 hpanther 
            if ( eth->rx.packet_length < ETHER_HDR_LEN ){
318 702 ivang 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
319 
                eth_rx_next_packet( eth );
320 
 
321 1372 nogj 
                debug (3, "RX - entering state WAIT4BD\n");
322 
                eth->rx.state = ETH_RXSTATE_WAIT4BD;
323 702 ivang 
                break;
324 
            }
325 
 
326 
            eth->rx.bytes_read = 0;
327 
            eth->rx.bytes_left = eth->rx.packet_length;
328 
 
329 
            /* for now Read entire packet into memory */
330 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
331 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
332 1350 nogj 
                debug (3, "Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);
333 844 ivang 
                eth->rx.error = 1;
334 
                break;
335 
            }
336 
 
337 
            eth->rx.packet_length = nread;
338 
            eth->rx.bytes_left = nread;
339 
            eth->rx.bytes_read = 0;
340 
 
341 
            debug (3, "RX - entering state WRITEFIFO\n");
342 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
343 
 
344 702 ivang 
            break;
345 
 
346 
        case ETH_RTX_SOCK:
347 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
348 744 simons 
 
349 
            if (nread == 0)
350 
                break;
351 
            else if (nread < 0) {
352 
                if ( errno != EAGAIN ) {
353 889 ivang 
                    debug (3, "recv() FAILED!\n");
354 
                    break;
355 
                }
356 
                else break;
357 
            }
358 744 simons 
            /* If not promiscouos mode, check the destination address */
359 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
360 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
361 
                /* Nothing for now */
362 
                }
363 
 
364 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
365 
                    eth->mac_address[4] != eth->rx_buff[1] ||
366 
                    eth->mac_address[3] != eth->rx_buff[2] ||
367 
                    eth->mac_address[2] != eth->rx_buff[3] ||
368 
                    eth->mac_address[1] != eth->rx_buff[4] ||
369 
                    eth->mac_address[0] != eth->rx_buff[5])
370 889 ivang 
                    break;
371 744 simons 
            }
372 
 
373 841 simons 
            eth->rx.packet_length = nread;
374 
            eth->rx.bytes_left = nread;
375 
            eth->rx.bytes_read = 0;
376 
 
377 
            debug (3, "RX - entering state WRITEFIFO\n");
378 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
379 
 
380 702 ivang 
            break;
381 889 ivang 
        case ETH_RTX_VAPI:
382 1366 nogj 
            break;
383 702 ivang 
        }
384 841 simons 
        break;
385 
 
386 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
387 744 simons 
#if 1
388 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
389 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
390 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
391 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
392 1241 phoenix 
        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint, 0, 0);
393 702 ivang 
        /* update counters */
394 1350 nogj 
        debug (3, "Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
395 
               eth->rx.bytes_left, send_word);
396 702 ivang 
        eth->rx.bytes_left -= 4;
397 
        eth->rx.bytes_read += 4;
398 744 simons 
#else
399 1241 phoenix 
        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint, 0, 0);
400 744 simons 
        eth->rx.bytes_left -= 1;
401 
        eth->rx.bytes_read += 1;
402 
#endif
403 
 
404 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
405 
            /* Write result to bd */
406 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
407 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
408 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
409 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
410 702 ivang 
 
411 1068 simons 
            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )
412 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
413 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
414 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
415 
 
416 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
417 
 
418 
            /* advance to next BD */
419 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
420 1018 simons 
                eth->rx.bd_index = eth->regs.tx_bd_num << 1;
421 702 ivang 
            else
422 705 ivang 
                eth->rx.bd_index += 2;
423 702 ivang 
 
424 889 ivang 
            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&
425 
                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {
426 702 ivang 
                report_interrupt( eth->mac_int );
427 
            }
428 
 
429 
            /* ready to receive next packet */
430 
                debug (3, "RX - entering state IDLE\n");
431 
            eth->rx.state = ETH_RXSTATE_IDLE;
432 
        }
433 
        break;
434 696 ivang 
    }
435 1372 nogj 
 
436 
    /* Reschedule */
437 1390 nogj 
    SCHED_ADD( eth_controller_rx_clock, dat, 1 );
438 696 ivang 
}
439 702 ivang 
 
440 696 ivang 
/* ========================================================================= */
441 702 ivang 
/* Move to next RX BD */
442 
void eth_rx_next_packet( struct eth_device *eth )
443 
{
444 
    /* Skip any possible leftovers */
445 
    if ( eth->rx.bytes_left )
446 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
447 
}
448 
/* "Skip" bytes in RX file */
449 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
450 
{
451 
    eth->rx.offset += count;
452 
}
453 696 ivang 
 
454 702 ivang 
/* Move RX file position back */
455 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
456 
{
457 
    eth->rx.offset -= count;
458 
}
459 
/*
460 
 * Utility function to read from the ethernet RX file
461 
 * This function moves the file pointer to the current place in the packet before reading
462 
 */
463 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
464 
{
465 
    ssize_t result;
466 
 
467 
    if ( eth->rx.fd <= 0 ) {
468 
        debug( 3,  "Ethernet: No RX file\n" );
469 
        return 0;
470 
    }
471 
 
472 
    if ( eth->rx.offset )
473 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
474 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
475 
            return 0;
476 
        }
477 696 ivang 
 
478 702 ivang 
    result = read( eth->rx.fd, buf, count );
479 836 ivang 
    debug (4, "Ethernet: read result = %d \n", result);
480 702 ivang 
    if ( eth->rx.offset && result >= 0 )
481 
        *(eth->rx.offset) += result;
482 
 
483 
    return result;
484 
}
485 
 
486 
/* ========================================================================= */
487 
 
488 696 ivang 
/*
489 702 ivang 
  Reset. Initializes all registers to default and places devices in
490 
         memory address space.
491 696 ivang 
*/
492 1372 nogj 
void eth_reset(void *dat)
493 696 ivang 
{
494 1372 nogj 
    struct eth_device *eth = dat;
495 1308 phoenix 
#if HAVE_ETH_PHY
496 702 ivang 
    int j;
497 
    struct sockaddr_ll sll;
498 849 markom 
#endif /* HAVE_ETH_PHY */
499 702 ivang 
 
500 
    if ( eth->baseaddr != 0 ) {
501 
        switch (eth->rtx_type) {
502 
        case ETH_RTX_FILE:
503 
            /* (Re-)open TX/RX files */
504 
            if ( eth->rxfd > 0 )
505 
                close( eth->rxfd );
506 
            if ( eth->txfd > 0 )
507 
                close( eth->txfd );
508 
            eth->rxfd = eth->txfd = -1;
509 
 
510 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
511 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
512 
            if ( (eth->txfd = open( eth->txfile,
513 1244 hpanther 
                                    O_RDWR | O_CREAT | O_APPEND
514 
 
515 
#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */
516 
                                                                        | O_SYNC
517 
#endif
518 
                                                                        ,
519 702 ivang 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
520 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
521 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
522 
 
523 
            break;
524 867 markom 
#if HAVE_ETH_PHY
525 702 ivang 
        case ETH_RTX_SOCK:
526 
            /* (Re-)open TX/RX sockets */
527 
            if (eth->rtx_sock != 0)
528 
                break;
529 
 
530 
            debug (3, "RTX oppening socket...\n");
531 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
532 
            if (eth->rtx_sock == -1) {
533 
                fprintf( stderr, "Cannot open rtx_sock.\n");
534 
                return;
535 
            }
536 
 
537 
            /* get interface index number */
538 
            debug (3, "RTX getting interface...\n");
539 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
540 1372 nogj 
            strncpy(eth->ifr.ifr_name, eth->sockif, IFNAMSIZ);
541 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
542 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
543 
                return;
544 
            }
545 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
546 
 
547 
            /* Bind to interface... */
548 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
549 
            memset(&sll, 0xff, sizeof(sll));
550 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
551 
            sll.sll_protocol = htons(ETH_P_ALL);
552 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
553 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
554 
                fprintf( stderr, "Error bind().\n");
555 
                return;
556 
            }
557 
 
558 
            /* first, flush all received packets. */
559 
            debug (3, "Flush");
560 
            do {
561 
                fd_set fds;
562 
                struct timeval t;
563 
 
564 
                debug( 3, ".");
565 
                FD_ZERO(&fds);
566 
                FD_SET(eth->rtx_sock, &fds);
567 
                memset(&t, 0, sizeof(t));
568 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
569 
                if (j > 0)
570 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
571 
            } while (j);
572 
            debug (3, "\n");
573 
 
574 
            break;
575 1372 nogj 
#else /* HAVE_ETH_PHY */
576 
        case ETH_RTX_SOCK:
577 
            fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
578 
            exit (1);
579 
            break;
580 849 markom 
#endif /* HAVE_ETH_PHY */
581 702 ivang 
        }
582 
 
583 
        /* Set registers to default values */
584 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
585 
        eth->regs.moder = 0x0000A000;
586 
        eth->regs.ipgt = 0x00000012;
587 
        eth->regs.ipgr1 = 0x0000000C;
588 
        eth->regs.ipgr2 = 0x00000012;
589 
        eth->regs.packetlen = 0x003C0600;
590 
        eth->regs.collconf = 0x000F003F;
591 
        eth->regs.miimoder = 0x00000064;
592 1018 simons 
        eth->regs.tx_bd_num = 0x00000040;
593 702 ivang 
 
594 
        /* Initialize TX/RX status */
595 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
596 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
597 1018 simons 
        eth->rx.bd_index = eth->regs.tx_bd_num << 1;
598 889 ivang 
 
599 
        /* Initialize VAPI */
600 1372 nogj 
        if (eth->base_vapi_id) {
601 
            vapi_install_multi_handler( eth->base_vapi_id, ETH_NUM_VAPI_IDS, eth_vapi_read, dat );
602 889 ivang 
        }
603 702 ivang 
    }
604 
}
605 
/* ========================================================================= */
606 
 
607 
 
608 696 ivang 
/*
609 
  Print register values on stdout
610 
*/
611 1372 nogj 
void eth_status( void *dat )
612 696 ivang 
{
613 1372 nogj 
    struct eth_device *eth = dat;
614 696 ivang 
 
615 1372 nogj 
    PRINTF( "\nEthernet MAC at 0x%"PRIxADDR":\n", eth->baseaddr );
616 
    PRINTF( "MODER        : 0x%08lX\n", eth->regs.moder );
617 
    PRINTF( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
618 
    PRINTF( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
619 
    PRINTF( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
620 
    PRINTF( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
621 
    PRINTF( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
622 
    PRINTF( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
623 
    PRINTF( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
624 
    PRINTF( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
625 
    PRINTF( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
626 
    PRINTF( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
627 
    PRINTF( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
628 
    PRINTF( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
629 
    PRINTF( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
630 
    PRINTF( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
631 
    PRINTF( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
632 
    PRINTF( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
633 
           eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
634 
           eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
635 
    PRINTF( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
636 
    PRINTF( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
637 696 ivang 
}
638 
/* ========================================================================= */
639 
 
640 
 
641 
/*
642 
  Read a register
643 
*/
644 1359 nogj 
uint32_t eth_read32( oraddr_t addr, void *dat )
645 696 ivang 
{
646 1372 nogj 
    struct eth_device *eth = dat;
647 
    addr -= eth->baseaddr;
648 696 ivang 
 
649 
    switch( addr ) {
650 
    case ETH_MODER: return eth->regs.moder;
651 
    case ETH_INT_SOURCE: return eth->regs.int_source;
652 
    case ETH_INT_MASK: return eth->regs.int_mask;
653 
    case ETH_IPGT: return eth->regs.ipgt;
654 
    case ETH_IPGR1: return eth->regs.ipgr1;
655 
    case ETH_IPGR2: return eth->regs.ipgr2;
656 
    case ETH_PACKETLEN: return eth->regs.packetlen;
657 
    case ETH_COLLCONF: return eth->regs.collconf;
658 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
659 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
660 
    case ETH_MIIMODER: return eth->regs.miimoder;
661 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
662 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
663 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
664 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
665 
    case ETH_MIISTATUS: return eth->regs.miistatus;
666 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
667 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
668 
                               (((unsigned long)eth->mac_address[1]) << 8) |
669 
                                 (unsigned long)eth->mac_address[0];
670 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
671 702 ivang 
                                 (unsigned long)eth->mac_address[4];
672 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
673 
    case ETH_HASH1: return eth->regs.hash1;
674 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
675 696 ivang 
    }
676 
 
677 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
678 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
679 696 ivang 
 
680 1350 nogj 
    PRINTF( "eth_read32( 0x%"PRIxADDR" ): Illegal address\n",
681 
            addr + eth->baseaddr );
682 884 markom 
    runtime.sim.cont_run = 0;
683 696 ivang 
    return 0;
684 
}
685 
/* ========================================================================= */
686 
 
687 
 
688 
/*
689 
  Write a register
690 
*/
691 1359 nogj 
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
692 696 ivang 
{
693 1372 nogj 
    struct eth_device *eth = dat;
694 
 
695 
    addr -= eth->baseaddr;
696 
 
697 696 ivang 
    switch( addr ) {
698 1372 nogj 
    case ETH_MODER:
699 
 
700 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
701 
             TEST_FLAG( value, ETH_MODER, RXEN) )
702 1390 nogj 
            SCHED_ADD( eth_controller_rx_clock, dat, 1 );
703 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, RXEN) )
704 
            SCHED_FIND_REMOVE( eth_controller_rx_clock, dat);
705 
 
706 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN) &&
707 
             TEST_FLAG( value, ETH_MODER, TXEN) )
708 1390 nogj 
            SCHED_ADD( eth_controller_tx_clock, dat, 1 );
709 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, TXEN) )
710 
            SCHED_FIND_REMOVE( eth_controller_tx_clock, dat);
711 
 
712 
        eth->regs.moder = value;
713 
 
714 
        if (TEST_FLAG(value, ETH_MODER, RST))
715 
            eth_reset( dat );
716 
        return;
717 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
718 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
719 
    case ETH_IPGT: eth->regs.ipgt = value; return;
720 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
721 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
722 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
723 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
724 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
725 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
726 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
727 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
728 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
729 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
730 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
731 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
732 
    case ETH_MAC_ADDR0:
733 702 ivang 
        eth->mac_address[0] = value & 0xFF;
734 
        eth->mac_address[1] = (value >> 8) & 0xFF;
735 
        eth->mac_address[2] = (value >> 16) & 0xFF;
736 
        eth->mac_address[3] = (value >> 24) & 0xFF;
737 
        return;
738 696 ivang 
    case ETH_MAC_ADDR1:
739 702 ivang 
        eth->mac_address[4] = value & 0xFF;
740 
        eth->mac_address[5] = (value >> 8) & 0xFF;
741 
        return;
742 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
743 
    case ETH_HASH1: eth->regs.hash1 = value; return;
744 702 ivang 
 
745 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
746 696 ivang 
    }
747 
 
748 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
749 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
750 
        return;
751 696 ivang 
    }
752 
 
753 1350 nogj 
    PRINTF( "eth_write32( 0x%"PRIxADDR" ): Illegal address\n",
754 
            addr + eth->baseaddr );
755 884 markom 
    runtime.sim.cont_run = 0;
756 696 ivang 
    return;
757 
}
758 
/* ========================================================================= */
759 
 
760 
 
761 889 ivang 
/*
762 
 *   VAPI connection to outside
763 
 */
764 1366 nogj 
static void eth_vapi_read (unsigned long id, unsigned long data, void *dat)
765 889 ivang 
{
766 
    unsigned long which;
767 1372 nogj 
    struct eth_device *eth = dat;
768 889 ivang 
 
769 1372 nogj 
    which = id - eth->base_vapi_id;
770 
 
771 1350 nogj 
    debug( 5, "ETH: id %08lx, data %08lx\n", id, data );
772 889 ivang 
 
773 
    if ( !eth ) {
774 1350 nogj 
        debug( 1, "ETH: VAPI ID %08lx is not ours!\n", id );
775 889 ivang 
        return;
776 
    }
777 
 
778 
    switch( which ) {
779 
    case ETH_VAPI_DATA:
780 
        break;
781 
    case ETH_VAPI_CTRL:
782 
        break;
783 
    }
784 
}
785 
/* ========================================================================= */
786 
 
787 
 
788 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
789 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
790 
{
791 1018 simons 
    eth->regs.tx_bd_num = value & 0xFF;
792 
    eth->rx.bd_index = eth->regs.tx_bd_num << 1;
793 702 ivang 
}
794 1372 nogj 
 
795 702 ivang 
/* ========================================================================= */
796 
 
797 1372 nogj 
/*-----------------------------------------------[ Ethernet configuration ]---*/
798 
void eth_baseaddr(union param_val val, void *dat)
799 696 ivang 
{
800 1372 nogj 
  struct eth_device *eth = dat;
801 
  eth->baseaddr = val.addr_val;
802 696 ivang 
}
803 889 ivang 
 
804 1372 nogj 
void eth_dma(union param_val val, void *dat)
805 889 ivang 
{
806 1372 nogj 
  struct eth_device *eth = dat;
807 
  eth->dma = val.addr_val;
808 889 ivang 
}
809 1358 nogj 
 
810 1372 nogj 
void eth_rtx_type(union param_val val, void *dat)
811 
{
812 
  struct eth_device *eth = dat;
813 
  eth->rtx_type = val.int_val;
814 1358 nogj 
}
815 
 
816 1372 nogj 
void eth_rx_channel(union param_val val, void *dat)
817 
{
818 
  struct eth_device *eth = dat;
819 
  eth->rx_channel = val.int_val;
820 1358 nogj 
}
821 
 
822 1372 nogj 
void eth_tx_channel(union param_val val, void *dat)
823 
{
824 
  struct eth_device *eth = dat;
825 
  eth->tx_channel = val.int_val;
826 1358 nogj 
}
827 
 
828 1372 nogj 
void eth_rxfile(union param_val val, void *dat)
829 
{
830 
  struct eth_device *eth = dat;
831 
  if(!(eth->rxfile = strdup(val.str_val))) {
832 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
833 
    exit(-1);
834 
  }
835 1358 nogj 
}
836 
 
837 
void eth_txfile(union param_val val, void *dat)
838 
{
839 1372 nogj 
  struct eth_device *eth = dat;
840 
  if(!(eth->txfile = strdup(val.str_val))) {
841 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
842 
    exit(-1);
843 
  }
844 1358 nogj 
}
845 
 
846 
void eth_sockif(union param_val val, void *dat)
847 
{
848 1372 nogj 
  struct eth_device *eth = dat;
849 
  if(!(eth->sockif = strdup(val.str_val))) {
850 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
851 
    exit(-1);
852 
  }
853 1358 nogj 
}
854 
 
855 
void eth_irq(union param_val val, void *dat)
856 
{
857 1372 nogj 
  struct eth_device *eth = dat;
858 
  eth->mac_int = val.int_val;
859 1358 nogj 
}
860 
 
861 
void eth_vapi_id(union param_val val, void *dat)
862 
{
863 1372 nogj 
  struct eth_device *eth = dat;
864 
  eth->base_vapi_id = val.int_val;
865 1358 nogj 
}
866 
 
867 1372 nogj 
void *eth_sec_start(void)
868 
{
869 
  struct eth_device *new = malloc(sizeof(struct eth_device));
870 
 
871 
  if(!new) {
872 
    fprintf(stderr, "Peripheral Eth: Run out of memory\n");
873 
    exit(-1);
874 
  }
875 
 
876 
  return new;
877 
}
878 
 
879 
void eth_sec_end(void *dat)
880 
{
881 
  struct eth_device *eth = dat;
882 
 
883 
  register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, 0, eth_read32, eth_write32, dat );
884 
  reg_sim_stat( eth_status, dat );
885 
  reg_sim_reset( eth_reset, dat );
886 
}
887 
 
888 1358 nogj 
void reg_ethernet_sec(void)
889 
{
890 1372 nogj 
  struct config_section *sec = reg_config_sec("ethernet", eth_sec_start, eth_sec_end);
891 1358 nogj 
 
892 
  reg_config_param(sec, "irq", paramt_int, eth_irq);
893 
  reg_config_param(sec, "baseaddr", paramt_int, eth_baseaddr);
894 
  reg_config_param(sec, "dma", paramt_int, eth_dma);
895 
  reg_config_param(sec, "rtx_type", paramt_int, eth_rtx_type);
896 
  reg_config_param(sec, "rx_channel", paramt_int, eth_rx_channel);
897 
  reg_config_param(sec, "tx_channel", paramt_int, eth_tx_channel);
898 
  reg_config_param(sec, "rxfile", paramt_str, eth_rxfile);
899 
  reg_config_param(sec, "txfile", paramt_str, eth_txfile);
900 
  reg_config_param(sec, "sockif", paramt_str, eth_sockif);
901 
  reg_config_param(sec, "vapi_id", paramt_int, eth_vapi_id);
902 
}

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