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1 1751 jeremybenn
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
It contains the default configuration and help about configuring
6
the simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41
 
42
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44
 
45
   Some section have subsections. One example of such a subsection is:
46
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54
 
55
/* MEMORY SECTION
56
 
57
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59
 
60
   type = random/unknown/pattern
61
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67
 
68
   random_seed = 
69
      random seed for randomizer, used if type = 'random'.
70
 
71
   pattern = 
72
      pattern to fill memory, used if type = 'pattern'.
73
 
74
   baseaddr = 
75
      memory start address
76
 
77
   size = 
78
      memory size
79
 
80
   name = ""
81
      memory block name
82
 
83
   ce = 
84
      chip enable index of the memory instance
85
 
86
   mc = 
87
      memory controller this memory is connected to
88
 
89
   delayr = 
90
      cycles, required for read access, -1 if instance does not support reading
91
 
92
   delayw = 
93
      cycles, required for write access, -1 if instance does not support
94
      writing
95
 
96
   log = ""
97
      filename, where to log memory accesses to. If log command is not
98
      specified, accesses are not logged.
99
*/
100
 
101
 
102
section memory
103
  name        = "RAM"
104
  random_seed = 12345
105
  type        = random
106
  ce          = 0
107
  mc          = 0
108
  baseaddr    = 0x00000000
109
  size        = 0x00400000
110
  delayr      = 1
111
  delayw      = 2
112
end
113
 
114
/* IMMU SECTION
115
 
116
    This section configures the Instruction Memory Manangement Unit
117
 
118
    enabled = 0/1
119
       '0': disabled
120
       '1': enabled
121
       (NOTE: UPR bit is set)
122
 
123
    nsets = 
124
       number of ITLB sets; must be power of two
125
 
126
    nways = 
127
       number of ITLB ways
128
 
129
    pagesize = 
130
       instruction page size; must be power of two
131
 
132
    entrysize = 
133
       instruction entry size in bytes
134
 
135
    ustates = 
136
       number of ITLB usage states (2, 3, 4 etc., max is 4)
137
 
138
    hitdelay = 
139
       number of cycles immu hit costs
140
 
141
    missdelay = 
142
       number of cycles immu miss costs
143
*/
144
 
145
section immu
146
  enabled = 0
147
  nsets = 64
148
  nways = 1
149
  pagesize = 8192
150
  hitdelay = 0
151
  missdelay = 0
152
end
153
 
154
 
155
/* DMMU SECTION
156
 
157
    This section configures the Data Memory Manangement Unit
158
 
159
    enabled = 0/1
160
       '0': disabled
161
       '1': enabled
162
       (NOTE: UPR bit is set)
163
 
164
    nsets = 
165
       number of DTLB sets; must be power of two
166
 
167
    nways = 
168
       number of DTLB ways
169
 
170
    pagesize = 
171
       data page size; must be power of two
172
 
173
    entrysize = 
174
       data entry size in bytes
175
 
176
    ustates = 
177
       number of DTLB usage states (2, 3, 4 etc., max is 4)
178
 
179
    hitdelay = 
180
       number of cycles dmmu hit costs
181
 
182
    missdelay = 
183
       number of cycles dmmu miss costs
184
*/
185
 
186
section dmmu
187
  enabled = 0
188
  nsets = 64
189
  nways = 1
190
  pagesize = 8192
191
  hitdelay = 0
192
  missdelay = 0
193
end
194
 
195
 
196
/* IC SECTION
197
 
198
   This section configures the Instruction Cache
199
 
200
   enabled = 0/1
201
       '0': disabled
202
       '1': enabled
203
      (NOTE: UPR bit is set)
204
 
205
   nsets = 
206
      number of IC sets; must be power of two
207
 
208
   nways = 
209
      number of IC ways
210
 
211
   blocksize = 
212
      IC block size in bytes; must be power of two
213
 
214
   ustates = 
215
      number of IC usage states (2, 3, 4 etc., max is 4)
216
 
217
   hitdelay = 
218
      number of cycles ic hit costs
219
 
220
    missdelay = 
221
      number of cycles ic miss costs
222
*/
223
 
224
section ic
225
  enabled = 0
226
  nsets = 256
227
  nways = 1
228
  blocksize = 16
229
  hitdelay = 0
230
  missdelay = 0
231
end
232
 
233
 
234
/* DC SECTION
235
 
236
   This section configures the Data Cache
237
 
238
   enabled = 0/1
239
       '0': disabled
240
       '1': enabled
241
      (NOTE: UPR bit is set)
242
 
243
   nsets = 
244
      number of DC sets; must be power of two
245
 
246
   nways = 
247
      number of DC ways
248
 
249
   blocksize = 
250
      DC block size in bytes; must be power of two
251
 
252
   ustates = 
253
      number of DC usage states (2, 3, 4 etc., max is 4)
254
 
255
   load_hitdelay = 
256
      number of cycles dc load hit costs
257
 
258
   load_missdelay = 
259
      number of cycles dc load miss costs
260
 
261
   store_hitdelay = 
262
      number of cycles dc store hit costs
263
 
264
   store_missdelay = 
265
      number of cycles dc store miss costs
266
*/
267
 
268
section dc
269
  enabled = 0
270
  nsets = 256
271
  nways = 1
272
  blocksize = 16
273
  load_hitdelay = 0
274
  load_missdelay = 0
275
  store_hitdelay = 0
276
  store_missdelay = 0
277
end
278
 
279
 
280
/* PIC SECTION
281
 
282
  This section specifies how the pic should behave
283
 
284
  enabled = 0/1
285
      '0': PIC is disabled
286
      '1': PIC is enabled
287
 
288
  edge_trigger = 0/1
289
      '0': Level triggered PIC
290
      '1': Edge triggered PIC
291
*/
292
 
293
section pic
294
  enabled = 1
295
  edge_trigger = 1
296
end
297
 
298
 
299
/* SIM SECTION
300
 
301
  This section specifies how or1ksim should behave.
302
 
303
  verbose = 0/1
304
       '0': don't print extra messages
305
       '1': print extra messages
306
 
307
  debug = 0-9
308
 
309
      1-9: debug message level.
310
           higher numbers produce more messages
311
 
312
  profile = 0/1
313
      '0': don't generate profiling file 'sim.profile'
314
      '1': don't generate profiling file 'sim.profile'
315
 
316
  prof_file = ""
317
      optional filename for the profiling file.
318
      valid only if 'profile' is set
319
 
320
  mprofile = 0/1
321
      '0': don't generate memory profiling file 'sim.mprofile'
322
      '1': generate memory profiling file 'sim.mprofile'
323
 
324
  mprof_file = ""
325
      optional filename for the memory profiling file.
326
      valid only if 'mprofile' is set
327
 
328
  history = 0/1
329
      '0': don't track execution flow
330
      '1': track execution flow
331
      Execution flow can be tracked for the simulator's
332
      'hist' command. Useful for back-trace debugging.
333
 
334
  iprompt = 0/1
335
     '0': start in  (so what do we start in ???)
336
     '1': start in interactive prompt.
337
 
338
  exe_log = 0/1
339
      '0': don't generate execution log.
340
      '1': generate execution log.
341
 
342
  exe_log_type = default/hardware/simple/software
343
      type of execution log, default is used when not specified
344
 
345
  exe_log_start = 
346
      index of first instruction to start logging, default = 0
347
 
348
  exe_log_end = 
349
      index of last instruction to end logging; not limited, if omitted
350
 
351
  exe_log_marker = 
352
       specifies number of instructions before horizontal marker is
353
      printed; if zero, markers are disabled (default)
354
 
355
  exe_log_file = ""
356
      filename for the exection log file.
357
      valid only if 'exe_log' is set
358
 
359
  clkcycle = [ps|ns|us|ms]
360
      specifies time measurement for one cycle
361
*/
362
 
363
section sim
364
  /* verbose = 1 */
365
  debug = 0
366
  profile = 0
367
  prof_file = "sim.profile"
368
 
369
  history = 0
370
  /* iprompt = 0 */
371
  exe_log = 0
372
  exe_log_type = software
373
  exe_log_start = 0
374
/*  exe_log_end = 20000000*/
375
  exe_log_marker = 10000
376
  exe_log_file = "executed.log"
377
 
378
  clkcycle = 100ns
379
end
380
 
381
 
382
/* SECTION VAPI
383
 
384
    This section configures the Verification API, used for Advanced
385
    Core Verification.
386
 
387
    enabled = 0/1
388
        '0': disbable VAPI server
389
        '1': enable/start VAPI server
390
 
391
    server_port = 
392
        TCP/IP port to start VAPI server on
393
 
394
    log_enabled = 0/1
395
       '0': disable VAPI requests logging
396
       '1': enable VAPI requests logging
397
 
398
    hide_device_id = 0/1
399
       '1': don't log device id (for compatability with old version)
400
       '0': log device id
401
 
402
 
403
    vapi_log_file = 
404
       filename for the log file.
405
       valid only if log_enabled is set
406
*/
407
 
408
section VAPI
409
  enabled = 0
410
  server_port = 50000
411
  log_enabled = 0
412
  vapi_log_file = "vapi.log"
413
end
414
 
415
 
416
/* CPU SECTION
417
 
418
   This section specifies various CPU parameters.
419
 
420
   ver = 
421
   cfg = 
422
   rev = 
423
      specifies version, configuration and revision fields of the CPU version
424
      register.
425
 
426
   upr = 
427
      changes the upr register
428
 
429
   cfgr = 
430
      changes the CPU configuration register
431
 
432
   sr = 
433
      sets the initial Supervision Register value
434
 
435
   superscalar = 0/1
436
      '0': CPU is scalar
437
      '1': CPU is superscalar
438
      (modify cpu/or32/execute.c to tune superscalar model)
439
 
440
   hazards = 0/1
441
      '0': don't track data hazards in superscalar CPU
442
      '1': track data hazards in superscalar CPU
443
      If tracked, data hazards can be displayed using the
444
      simulator's 'r' command.
445
 
446
   dependstats = 0/1
447
      '0': don't calculate inter-instruction dependencies.
448
      '1': calculate inter-instruction dependencies.
449
      If calculated, inter-instruction dependencies can be
450
      displayed using the simulator's 'stat' command.
451
 
452
   sbuf_len = 
453
      length of store buffer (<= 256), 0 = disabled
454
*/
455
 
456
section cpu
457
  ver = 0x12
458
  cfg = 0x00
459
  rev = 0x0001
460
  superscalar = 0
461
  hazards = 0
462
  dependstats = 0
463
  sbuf_len = 0
464
end
465
 
466
 
467
/* PM SECTION
468
 
469
   This section specifies Power Management parameters
470
 
471
   enabled = 0/1
472
      '0': disable power management
473
      '1': enable power management
474
*/
475
 
476
section pm
477
  enabled = 1
478
end
479
 
480
 
481
/* BPB SECTION
482
 
483
   This section specifies how branch prediction should behave.
484
 
485
   enabled = 0/1
486
     '0': disable branch prediction
487
     '1': enable branch prediction
488
 
489
   btic = 0/1
490
     '0': disable branch target instruction cache model
491
     '1': enable branch target instruction cache model
492
 
493
   sbp_bf_fwd = 0/1
494
     Static branch prediction for 'l.bf'
495
     '0': don't use forward prediction
496
     '1': use forward prediction
497
 
498
   sbp_bnf_fwd = 0/1
499
     Static branch prediction for 'l.bnf'
500
     '0': don't use forward prediction
501
     '1': use forward prediction
502
 
503
   hitdelay = 
504
       number of cycles bpb hit costs
505
 
506
   missdelay = 
507
       number of cycles bpb miss costs
508
*/
509
 
510
section bpb
511
  enabled = 1
512
  btic = 0
513
  sbp_bf_fwd = 0
514
  sbp_bnf_fwd = 0
515
  hitdelay = 0
516
  missdelay = 0
517
end
518
 
519
 
520
/* DEBUG SECTION
521
 
522
   This sections specifies how the debug unit should behave.
523
 
524
   enabled = 0/1
525
      '0': disable debug unit
526
      '1': enable debug unit
527
 
528
   gdb_enabled = 0/1
529
      '0': don't start gdb server
530
      '1': start gdb server at port 'server_port'
531
 
532
   server_port = 
533
      TCP/IP port to start gdb server on
534
      valid only if gdb_enabled is set
535
 
536
   vapi_id = 
537
      Used to create "fake" vapi log file containing the JTAG proxy messages.
538
*/
539
 
540
section debug
541
  enabled     = 1
542
  gdb_enabled = 0
543
  rsp_enabled = 1
544
  rsp_port    = 51000
545
end
546
 
547
 
548
/* MC SECTION
549
 
550
   This section configures the memory controller
551
 
552
   enabled = 0/1
553
     '0': disable memory controller
554
     '1': enable memory controller
555
 
556
   baseaddr = 
557
      address of first MC register
558
 
559
   POC = 
560
      Power On Configuration register
561
 
562
   index = 
563
      Index of this memory controller amongst all the memory controllers
564
*/
565
 
566
section mc
567
  enabled = 1
568
  baseaddr = 0x93000000
569
  POC = 0x0000000a                 /* 32 bit SSRAM */
570
  index = 0
571
end
572
 
573
 
574
/* UART SECTION
575
 
576
   This section configures the UARTs
577
 
578
     enabled = <0|1>
579
        Enable/disable the peripheral.  By default if it is enabled.
580
 
581
     baseaddr = 
582
        address of first UART register for this device
583
 
584
 
585
     channel = :
586
 
587
        The channel parameter indicates the source of received UART characters
588
        and the sink for transmitted UART characters.
589
 
590
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
591
        (without quotes).
592
 
593
          A) To send/receive characters from a pair of files, use a file
594
             channel:
595
 
596
               channel=file:,
597
 
598
          B) To create an interactive terminal window, use an xterm channel:
599
 
600
               channel=xterm:[]*
601
 
602
          C) To create a bidirectional tcp socket which one could, for example,
603
             access via telnet, use a tcp channel:
604
 
605
               channel=tcp:
606
 
607
          D) To cause the UART to read/write from existing numeric file
608
             descriptors, use an fd channel:
609
 
610
               channel=fd:,
611
 
612
          E) To connect the UART to a physical serial port, create a tty
613
             channel:
614
 
615
               channel=tty:device=/dev/ttyS0,baud=9600
616
 
617
     irq = 
618
        irq number for this device
619
 
620
     16550 = 0/1
621
        '0': this device is a UART16450
622
        '1': this device is a UART16550
623
 
624
     jitter = 
625
        in msecs... time to block, -1 to disable it
626
 
627
     vapi_id = 
628
        VAPI id of this instance
629
*/
630
 
631
section uart
632
  enabled = 1
633
  baseaddr = 0x90000000
634
  irq = 2
635
  channel = "file:uart0.rx,uart0.tx"
636
  jitter = -1                     /* async behaviour */
637
  16550 = 1
638
end
639
 
640
 
641
/* DMA SECTION
642
 
643
   This section configures the DMAs
644
 
645
     enabled = <0|1>
646
        Enable/disable the peripheral.  By default if it is enabled.
647
 
648
     baseaddr = 
649
        address of first DMA register for this device
650
 
651
     irq = 
652
        irq number for this device
653
 
654
     vapi_id = 
655
        VAPI id of this instance
656
*/
657
 
658
section dma
659
  enabled = 1
660
  baseaddr = 0x9a000000
661
  irq = 11
662
end
663
 
664
 
665
/* ETHERNET SECTION
666
 
667
   This section configures the ETHERNETs
668
 
669
     enabled = <0|1>
670
        Enable/disable the peripheral.  By default if it is enabled.
671
 
672
     baseaddr = 
673
        address of first ethernet register for this device
674
 
675
     dma = 
676
        which controller is this ethernet "connected" to
677
 
678
     irq = 
679
        ethernet mac IRQ level
680
 
681
     rtx_type = 
682
        use 0 - file interface, 1 - socket interface. Note the socket
683
        interface must be configured at build time.
684
 
685
     rx_channel = 
686
        DMA channel used for RX
687
 
688
     tx_channel = 
689
        DMA channel used for TX
690
 
691
     rxfile = ""
692
        filename, where to read data from
693
 
694
     txfile = ""
695
        filename, where to write data to
696
 
697
     sockif = ""
698
        interface name of ethernet socket
699
 
700
     vapi_id = 
701
        VAPI id of this instance
702
*/
703
 
704
section ethernet
705
  enabled = 1
706
  baseaddr = 0x92000000
707
  irq = 4
708
  rtx_type = 0
709
  rxfile = "eth0.rx"
710
  txfile = "eth0.tx"
711
  sockif = "eth0"
712
end
713
 
714
 
715
/* GPIO SECTION
716
 
717
   This section configures the GPIOs
718
 
719
     enabled = <0|1>
720
        Enable/disable the peripheral.  By default if it is enabled.
721
 
722
     baseaddr = 
723
        address of first GPIO register for this device
724
 
725
     irq = 
726
        irq number for this device
727
 
728
     base_vapi_id = 
729
        first VAPI id of this instance
730
        GPIO uses 8 consecutive VAPI IDs
731
*/
732
 
733
section gpio
734
  enabled = 1
735
  baseaddr = 0x91000000
736
  irq = 3
737
  base_vapi_id = 0x0200
738
end
739
 
740
/* VGA SECTION
741
 
742
    This section configures the VGA/LCD controller
743
 
744
      enabled = <0|1>
745
        Enable/disable the peripheral.  By default if it is enabled.
746
 
747
      baseaddr = 
748
        address of first VGA register
749
 
750
      irq = 
751
        irq number for this device
752
 
753
      refresh_rate = 
754
        number of cycles between screen dumps
755
 
756
      filename = ""
757
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
758
*/
759
 
760
section vga
761
  enabled = 1
762
  baseaddr = 0x97100000
763
  irq = 8
764
  refresh_rate = 100000
765
  filename = "primary"
766
end
767
 
768
 
769
/* FB SECTION
770
 
771
    This section configures the frame buffer
772
 
773
    enabled = <0|1>
774
      Enable/disable the peripheral.  By default if it is enabled.
775
 
776
    baseaddr = 
777
      base address of frame buffer
778
 
779
    refresh_rate = 
780
      number of cycles between screen dumps
781
 
782
    filename = ""
783
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
784
*/
785
 
786
section fb
787
  enabled = 1
788
  baseaddr = 0x97000000
789
  refresh_rate = 1000000
790
  filename = "primary"
791
end
792
 
793
 
794
/* KBD SECTION
795
 
796
    This section configures the PS/2 compatible keyboard
797
 
798
    enabled = <0|1>
799
      Enable/disable the peripheral.  By default if it is enabled.
800
 
801
    baseaddr = 
802
      base address of the keyboard device
803
 
804
    irq = 
805
      irq number for this device
806
 
807
    rxfile = ""
808
      filename, where to read data from
809
*/
810
 
811
section kbd
812
  enabled = 1
813
  baseaddr = 0x94000000
814
  irq = 5
815
  rxfile = "kbd.rx"
816
end
817
 
818
 
819
/* ATA SECTION
820
 
821
    This section configures the ATA/ATAPI host controller
822
 
823
      enabled = <0|1>
824
        Enable/disable the peripheral.  By default it is enabled.
825
 
826
      baseaddr = 
827
        address of first ATA register
828
 
829
      irq = 
830
        irq number for this device
831
 
832
      dev_id = 1/2/3
833
        Which OCIDEC version to imitate
834
 
835
      rev = 
836
        Revision of OCIDEC
837
 
838
      pio_mode0_t1 = <0-255>
839
        PIO T1 reset value
840
 
841
      pio_mode0_t2 = <0-255>
842
        PIO T2 reset value
843
 
844
      pio_mode0_t4 = <0-255>
845
        PIO T4 reset value
846
 
847
      pio_mode0_teoc = <0-255>
848
        PIO Teoc reset value
849
 
850
      dma_mode0_tm = <0-255>
851
        DMA Tm reset value
852
 
853
      dma_mode0_td = <0-255>
854
        DMA Td reset value
855
 
856
      dma_mode0_teoc = <0-255>
857
        DMA Teoc reset value
858
 
859
      Device specific
860
 
861
        type = 
862
          ata device 0 type
863
          0: NO_CONNECT: none (not connected)
864
          1: FILE      : simulated harddisk
865
          2: LOCAL     : local system harddisk
866
 
867
        file = ""
868
          filename for simulated ATA device
869
          valid only if dev_type0 == 1
870
 
871
        size = 
872
          size of simulated hard-disk (in MBytes)
873
          valid only if dev_type0 == 1
874
 
875
        packet = 
876
          0: simulated ATA device does NOT implement PACKET command feature set
877
          1: simulated ATA device does implement PACKET command feature set
878
 
879
        firmware = 
880
          Firmware to report in `Identify device command'
881
 
882
        heads = 
883
          Number of default heads (-1)
884
 
885
        sectors = 
886
          Number of default sectors per track
887
 
888
        mwdma = 
889
          The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
890
 
891
        pio = 
892
          The highest supported pio mode; 4, 3, 2, 1, 0
893
 
894
   FIXME: irq number
895
*/
896
 
897
section ata
898
  enabled = 1
899
  baseaddr = 0x9e000000
900
  irq = 15
901
  dev_id = 1
902
  rev = 0
903
 
904
  pio_mode0_t1 = 6
905
  pio_mode0_t2 = 28
906
  pio_mode0_t4 = 2
907
  pio_mode0_teoc = 23
908
 
909
  dma_mode0_tm = 4
910
  dma_mode0_td = 21
911
  dma_mode0_teoc = 21
912
 
913
  device 0
914
    type   = 1
915
    file   = "/tmp/sim_atadev0"
916
    size   = 1
917
    packet = 0
918
 
919
    heads  = 7
920
    sectors = 32
921
 
922
    firmware = "02207031"
923
    mwdma = 2
924
    pio = 4
925
  enddevice
926
 
927
  device 1
928
    type   = 0
929
    file   = ""
930
    size   = 0
931
    packet = 0
932
  enddevice
933
end
934
 
935
 
936
/* CUC SECTION
937
 
938
    This section configures the OpenRISC Custom Unit Compiler
939
 
940
    memory_order = none/weak/strong/exact
941
      none   different memory ordering, even if there are dependencies,
942
             burst can be made, width can change
943
      weak   different memory ordering, if there cannot be dependencies
944
             burst can be made, width can change
945
      strong same memory ordering, burst can be made, width can change
946
      exact  exacltly the same memory ordering and widths
947
 
948
    calling_convention = 0/1
949
      whether programs follow OpenRISC calling conventions
950
 
951
    enable_bursts = 0/1
952
      whether burst are detected
953
 
954
    no_multicycle = 0/1
955
      if selected no multicycle logic paths will be generated
956
 
957
    timings_fn = ""
958
*/
959
 
960
section cuc
961
  memory_order = weak
962
  calling_convention = 1
963
  enable_bursts = 1
964
  no_multicycle = 1
965
  timings_fn = "virtex.tim"
966
end
967
 

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