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[/] [or1k/] [trunk/] [or1ksim/] [sim.cfg] - Blame information for rev 1715

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/* sim.cfg -- Simulator configuration script file
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   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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It contains the default configuration and help about configuring
6
the simulator.
7 264 markom
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22 312 markom
 
23
/* INTRODUCTION
24
 
25 876 rherveille
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
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33 876 rherveille
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
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39 876 rherveille
   Configure files may be be included, using:
40 568 markom
   include "file_name_to_include"
41 312 markom
 
42 876 rherveille
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44 428 markom
 
45 876 rherveille
   Some section have subsections. One example of such a subsection is:
46 428 markom
 
47 312 markom
   device 
48
     instance specific parameters...
49
   enddevice
50 428 markom
 
51 312 markom
   which creates a device instance.
52
*/
53
 
54 876 rherveille
 
55 312 markom
/* MEMORY SECTION
56
 
57 876 rherveille
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59 428 markom
 
60 312 markom
   type = random/unknown/pattern
61 876 rherveille
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67 428 markom
 
68 312 markom
   random_seed = 
69 876 rherveille
      random seed for randomizer, used if type = 'random'.
70 428 markom
 
71 312 markom
   pattern = 
72 876 rherveille
      pattern to fill memory, used if type = 'pattern'.
73 428 markom
 
74 424 markom
   nmemories = 
75 428 markom
      number of memory instances connected
76
 
77 1486 nogj
   baseaddr = 
78
      memory start address
79 428 markom
 
80 1486 nogj
   size = 
81
      memory size
82 424 markom
 
83 1486 nogj
   name = ""
84
      memory block name
85 428 markom
 
86 1486 nogj
   ce = 
87
      chip enable index of the memory instance
88 424 markom
 
89 1486 nogj
   mc = 
90
      memory controller this memory is connected to
91 428 markom
 
92 1486 nogj
   delayr = 
93
      cycles, required for read access, -1 if instance does not support reading
94 428 markom
 
95 1486 nogj
   delayw = 
96
      cycles, required for write access, -1 if instance does not support writing
97
 
98
   log = ""
99
      filename, where to log memory accesses to, no log, if log command is not specified
100 312 markom
*/
101
 
102 1021 rherveille
 
103 262 markom
section memory
104 264 markom
  /*random_seed = 12345
105
  type = random*/
106 269 markom
  pattern = 0x00
107
  type = unknown /* Fastest */
108 428 markom
 
109 1486 nogj
  name = "FLASH"
110
  ce = 0
111
  mc = 0
112
  baseaddr = 0xf0000000
113
  size = 0x00800000
114
  delayr = 10
115
  delayw = -1
116
end
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118 1486 nogj
section memory
119
  /*random_seed = 12345
120
  type = random*/
121
  pattern = 0x00
122
  type = unknown /* Fastest */
123 428 markom
 
124 1486 nogj
  name = "RAM"
125
  ce = 1
126
  mc = 0
127
  baseaddr = 0x00000000
128
  size = 0x00400000
129
  delayr = 1
130
  delayw = 2
131
end
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133 1486 nogj
section memory
134
  /*random_seed = 12345
135
  type = random*/
136
  pattern = 0x00
137
  type = unknown /* Fastest */
138
 
139
  name = "SRAM"
140
  mc = 0
141
  ce = 2
142
  baseaddr = 0x08000000
143
  size = 0x00400000
144
  delayr = 1
145
  delayw = 2
146 262 markom
end
147
 
148 434 markom
 
149 427 markom
/* IMMU SECTION
150 312 markom
 
151 876 rherveille
    This section configures the Instruction Memory Manangement Unit
152 428 markom
 
153 427 markom
    enabled = 0/1
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       '0': disabled
155
       '1': enabled
156 428 markom
       (NOTE: UPR bit is set)
157
 
158 427 markom
    nsets = 
159 428 markom
       number of ITLB sets; must be power of two
160
 
161 427 markom
    nways = 
162
       number of ITLB ways
163 428 markom
 
164 427 markom
    pagesize = 
165
       instruction page size; must be power of two
166 428 markom
 
167 427 markom
    entrysize = 
168
       instruction entry size in bytes
169 428 markom
 
170 427 markom
    ustates = 
171
       number of ITLB usage states (2, 3, 4 etc., max is 4)
172 1021 rherveille
 
173 541 markom
    hitdelay = 
174
       number of cycles immu hit costs
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176 541 markom
    missdelay = 
177
       number of cycles immu miss costs
178 427 markom
*/
179
 
180
section immu
181 1021 rherveille
  enabled = 1
182
  nsets = 64
183 427 markom
  nways = 1
184 428 markom
  pagesize = 8192
185 541 markom
  hitdelay = 0
186
  missdelay = 0
187 427 markom
end
188 428 markom
 
189 434 markom
 
190 427 markom
/* DMMU SECTION
191
 
192 876 rherveille
    This section configures the Data Memory Manangement Unit
193 428 markom
 
194 427 markom
    enabled = 0/1
195 876 rherveille
       '0': disabled
196
       '1': enabled
197 428 markom
       (NOTE: UPR bit is set)
198
 
199 427 markom
    nsets = 
200
       number of DTLB sets; must be power of two
201 428 markom
 
202 427 markom
    nways = 
203
       number of DTLB ways
204 428 markom
 
205 427 markom
    pagesize = 
206
       data page size; must be power of two
207 428 markom
 
208 427 markom
    entrysize = 
209
       data entry size in bytes
210 428 markom
 
211 427 markom
    ustates = 
212
       number of DTLB usage states (2, 3, 4 etc., max is 4)
213 541 markom
 
214
    hitdelay = 
215 876 rherveille
       number of cycles dmmu hit costs
216
 
217 541 markom
    missdelay = 
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       number of cycles dmmu miss costs
219 427 markom
*/
220
 
221
section dmmu
222 1021 rherveille
  enabled = 1
223
  nsets = 64
224 427 markom
  nways = 1
225 428 markom
  pagesize = 8192
226 541 markom
  hitdelay = 0
227
  missdelay = 0
228 427 markom
end
229
 
230 428 markom
 
231
/* IC SECTION
232
 
233 876 rherveille
   This section configures the Instruction Cache
234 428 markom
 
235 541 markom
   enabled = 0/1
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       '0': disabled
237
       '1': enabled
238 541 markom
      (NOTE: UPR bit is set)
239 428 markom
 
240 541 markom
   nsets = 
241
      number of IC sets; must be power of two
242 428 markom
 
243 541 markom
   nways = 
244
      number of IC ways
245 428 markom
 
246 541 markom
   blocksize = 
247
      IC block size in bytes; must be power of two
248 428 markom
 
249 541 markom
   ustates = 
250
      number of IC usage states (2, 3, 4 etc., max is 4)
251
 
252
   hitdelay = 
253
      number of cycles ic hit costs
254 1021 rherveille
 
255 541 markom
    missdelay = 
256
      number of cycles ic miss costs
257 428 markom
*/
258
 
259
section ic
260 1021 rherveille
  enabled = 1
261
  nsets = 256
262 428 markom
  nways = 1
263
  blocksize = 16
264 541 markom
  hitdelay = 0
265
  missdelay = 0
266 428 markom
end
267
 
268 434 markom
 
269 428 markom
/* DC SECTION
270
 
271 876 rherveille
   This section configures the Data Cache
272 428 markom
 
273 541 markom
   enabled = 0/1
274 876 rherveille
       '0': disabled
275
       '1': enabled
276 541 markom
      (NOTE: UPR bit is set)
277 428 markom
 
278 541 markom
   nsets = 
279
      number of DC sets; must be power of two
280 428 markom
 
281 541 markom
   nways = 
282
      number of DC ways
283 428 markom
 
284 541 markom
   blocksize = 
285
      DC block size in bytes; must be power of two
286 428 markom
 
287 541 markom
   ustates = 
288
      number of DC usage states (2, 3, 4 etc., max is 4)
289
 
290
   load_hitdelay = 
291
      number of cycles dc load hit costs
292 1021 rherveille
 
293 541 markom
   load_missdelay = 
294
      number of cycles dc load miss costs
295 1021 rherveille
 
296 541 markom
   store_hitdelay = 
297
      number of cycles dc load hit costs
298 1021 rherveille
 
299 541 markom
   store_missdelay = 
300
      number of cycles dc load miss costs
301 428 markom
*/
302
 
303
section dc
304 1021 rherveille
  enabled = 1
305
  nsets = 256
306 428 markom
  nways = 1
307
  blocksize = 16
308 541 markom
  load_hitdelay = 0
309
  load_missdelay = 0
310
  store_hitdelay = 0
311
  store_missdelay = 0
312 428 markom
end
313
 
314 1021 rherveille
 
315 1715 nogj
/* PIC SECTION
316
 
317
  This section specifies how the pic should behave
318
 
319
  enabled = 0/1
320
      '0': PIC is disabled
321
      '1': PIC is enabled
322
 
323
  edge_trigger = 0/1
324
      '0': Level triggered PIC
325
      '1': Edge triggered PIC
326
*/
327
 
328
section pic
329
  enabled = 1
330
  edge_trigger = 1
331
end
332
 
333
 
334 312 markom
/* SIM SECTION
335
 
336 876 rherveille
  This section specifies how or1ksim should behave.
337 428 markom
 
338 312 markom
  verbose = 0/1
339 876 rherveille
       '0': don't print extra messages
340
       '1': print extra messages
341 428 markom
 
342 344 markom
  debug = 0-9
343 876 rherveille
 
344
      1-9: debug message level.
345
           higher numbers produce more messages
346 428 markom
 
347 312 markom
  profile = 0/1
348 876 rherveille
      '0': don't generate profiling file 'sim.profile'
349
      '1': don't generate profiling file 'sim.profile'
350 428 markom
 
351 312 markom
  prof_fn = ""
352 876 rherveille
      optional filename for the profiling file.
353
      valid only if 'profile' is set
354 1021 rherveille
 
355 547 markom
  mprofile = 0/1
356 876 rherveille
      '0': don't generate memory profiling file 'sim.mprofile'
357
      '1': generate memory profiling file 'sim.mprofile'
358 428 markom
 
359 547 markom
  mprof_fn = ""
360 876 rherveille
      optional filename for the memory profiling file.
361
      valid only if 'mprofile' is set
362 547 markom
 
363 394 markom
  history = 0/1
364 876 rherveille
      '0': don't track execution flow
365
      '1': track execution flow
366
      Execution flow can be tracked for the simulator's
367
      'hist' command. Useful for back-trace debugging.
368 428 markom
 
369 312 markom
  iprompt = 0/1
370 876 rherveille
     '0': start in  (so what do we start in ???)
371
     '1': start in interactive prompt.
372 312 markom
 
373
  exe_log = 0/1
374 876 rherveille
      '0': don't generate execution log.
375
      '1': generate execution log.
376 1021 rherveille
 
377 675 markom
  exe_log = default/hardware/simple/software
378 876 rherveille
      type of execution log, default is used when not specified
379 1021 rherveille
 
380 672 markom
  exe_log_start = 
381 876 rherveille
      index of first instruction to start logging, default = 0
382 1021 rherveille
 
383 672 markom
  exe_log_end = 
384 876 rherveille
      index of last instruction to end logging; not limited, if omitted
385 1021 rherveille
 
386 672 markom
  exe_log_marker = 
387
       specifies number of instructions before horizontal marker is
388
      printed; if zero, markers are disabled (default)
389 428 markom
 
390 312 markom
  exe_log_fn = ""
391 876 rherveille
      filename for the exection log file.
392
      valid only if 'exe_log' is set
393 624 ivang
 
394 433 markom
  clkcycle = [ps|ns|us|ms]
395
      specifies time measurement for one cycle
396 335 markom
*/
397
 
398 312 markom
section sim
399 335 markom
  /* verbose = 1 */
400 879 markom
  debug = 0
401 689 markom
  profile = 0
402 312 markom
  prof_fn = "sim.profile"
403 428 markom
 
404 394 markom
  history = 1
405 312 markom
  /* iprompt = 0 */
406
  exe_log = 0
407 1021 rherveille
  exe_log_type = software
408 672 markom
  exe_log_start = 0
409 1021 rherveille
/*  exe_log_end = 20000000*/
410
  exe_log_marker = 10000
411 312 markom
  exe_log_fn = "executed.log"
412 1021 rherveille
 
413 624 ivang
  clkcycle = 100ns
414 312 markom
end
415
 
416
 
417
/* SECTION VAPI
418
 
419 876 rherveille
    This section configures the Verification API, used for Advanced
420 312 markom
    Core Verification.
421 428 markom
 
422 312 markom
    enabled = 0/1
423 876 rherveille
        '0': disbable VAPI server
424
        '1': enable/start VAPI server
425 428 markom
 
426 312 markom
    server_port = 
427
        TCP/IP port to start VAPI server on
428 428 markom
 
429 355 markom
    log_enabled = 0/1
430 876 rherveille
       '0': disable VAPI requests logging
431
       '1': enable VAPI requests logging
432 428 markom
 
433 486 erez
    hide_device_id = 0/1
434 876 rherveille
       '0': don't log device id (for compatability with old version)
435
       '1': log device id
436 1021 rherveille
 
437 486 erez
 
438 355 markom
    vapi_fn = 
439 876 rherveille
       filename for the log file.
440
       valid only if log_enabled is set
441 312 markom
*/
442
 
443
section VAPI
444
  enabled = 0
445
  server_port = 9998
446 355 markom
  log_enabled = 0
447 427 markom
  vapi_log_fn = "vapi.log"
448 312 markom
end
449
 
450
 
451
/* CPU SECTION
452
 
453
   This section specifies various CPU parameters.
454 428 markom
 
455 312 markom
   ver = 
456
   rev = 
457
      specifies version and revision of the CPU used
458 428 markom
 
459 312 markom
   upr = 
460
      changes the upr register
461 1021 rherveille
 
462 556 markom
   sr = 
463
      sets the initial Supervision Register value
464 428 markom
 
465 312 markom
   superscalar = 0/1
466 876 rherveille
      '0': CPU is scalar
467
      '1': CPU is superscalar
468 388 lampret
      (modify cpu/or32/execute.c to tune superscalar model)
469
 
470 312 markom
   hazards = 0/1
471 876 rherveille
      '0': don't track data hazards in superscalar CPU
472
      '1': track data hazards in superscalar CPU
473
      If tracked, data hazards can be displayed using the
474
      simulator's 'r' command.
475 388 lampret
 
476 312 markom
   dependstats = 0/1
477 876 rherveille
      '0': don't calculate inter-instruction dependencies.
478
      '1': calculate inter-instruction dependencies.
479
      If calculated, inter-instruction dependencies can be
480
      displayed using the simulator's 'stat' command.
481 388 lampret
 
482 626 markom
   sbuf_len = 
483
      length of store buffer (<= 256), 0 = disabled
484 312 markom
*/
485
 
486 263 markom
section cpu
487
  ver = 0x1200
488
  rev = 0x0001
489
  /* upr = */
490
  superscalar = 0
491
  hazards = 0
492
  dependstats = 0
493 626 markom
  sbuf_len = 0
494 263 markom
end
495
 
496 312 markom
 
497 557 markom
/* PM SECTION
498
 
499 876 rherveille
   This section specifies Power Management parameters
500
 
501 557 markom
   enabled = 0/1
502 876 rherveille
      '0': disable power management
503
      '1': enable power management
504 557 markom
*/
505
 
506
section pm
507
  enabled = 0
508
end
509
 
510 1021 rherveille
 
511 541 markom
/* BPB SECTION
512
 
513
   This section specifies how branch prediction should behave.
514 1021 rherveille
 
515 541 markom
   enabled = 0/1
516 876 rherveille
     '0': disable branch prediction
517
     '1': enable branch prediction
518 1021 rherveille
 
519 541 markom
   btic = 0/1
520 876 rherveille
     '0': disable branch target instruction cache model
521
     '1': enable branch target instruction cache model
522 541 markom
 
523
   sbp_bf_fwd = 0/1
524 876 rherveille
     Static branch prediction for 'l.bf'
525
     '0': don't use forward prediction
526 1021 rherveille
     '1': use forward prediction
527
 
528 541 markom
   sbp_bnf_fwd = 0/1
529 876 rherveille
     Static branch prediction for 'l.bnf'
530
     '0': don't use forward prediction
531
     '1': use forward prediction
532 541 markom
 
533
   hitdelay = 
534
       number of cycles bpb hit costs
535 1021 rherveille
 
536 541 markom
   missdelay = 
537
       number of cycles bpb miss costs
538
*/
539
 
540
section bpb
541
  enabled = 0
542
  btic = 0
543
  sbp_bf_fwd = 0
544
  sbp_bnf_fwd = 0
545
  hitdelay = 0
546
  missdelay = 0
547
end
548
 
549
 
550 312 markom
/* DEBUG SECTION
551
 
552 876 rherveille
   This sections specifies how the debug unit should behave.
553 428 markom
 
554 312 markom
   enabled = 0/1
555 876 rherveille
      '0': disable debug unit
556
      '1': enable debug unit
557 428 markom
 
558 312 markom
   gdb_enabled = 0/1
559 876 rherveille
      '0': don't start gdb server
560
      '1': start gdb server at port 'server_port'
561 428 markom
 
562 312 markom
   server_port = 
563 876 rherveille
      TCP/IP port to start gdb server on
564
      valid only if gdb_enabled is set
565 486 erez
 
566
   vapi_id = 
567
      Used to create "fake" vapi log file containing the JTAG proxy messages.
568 479 markom
*/
569 428 markom
 
570 269 markom
section debug
571 1021 rherveille
  enabled = 0
572 312 markom
  gdb_enabled = 0
573 269 markom
  server_port = 9999
574
end
575
 
576 264 markom
 
577 312 markom
/* MC SECTION
578
 
579
   This section configures the memory controller
580
 
581
   enabled = 0/1
582 876 rherveille
     '0': disable memory controller
583
     '1': enable memory controller
584 428 markom
 
585 312 markom
   baseaddr = 
586
      address of first MC register
587 428 markom
 
588 312 markom
   POC = 
589
      Power On Configuration register
590 1486 nogj
 
591
   index = 
592
      Index of this memory controller amongst all the memory controllers
593 312 markom
*/
594
 
595 243 markom
section mc
596 1021 rherveille
  enabled = 1
597
  baseaddr = 0x93000000
598 261 markom
  POC = 0x00000008                 /* Power on configuration register */
599 1486 nogj
  index = 0
600 243 markom
end
601 261 markom
 
602 312 markom
 
603
/* UART SECTION
604
 
605 876 rherveille
   This section configures the UARTs
606 312 markom
 
607 1461 nogj
     enabled = <0|1>
608
        Enable/disable the peripheral.  By default if it is enabled.
609
 
610 312 markom
     baseaddr = 
611
        address of first UART register for this device
612 428 markom
 
613 1126 sfurman
 
614
     channel = :
615
 
616
        The channel parameter indicates the source of received UART characters
617
        and the sink for transmitted UART characters.
618 428 markom
 
619 1126 sfurman
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
620
        (without quotes).
621 332 markom
 
622 1126 sfurman
          A) To send/receive characters from a pair of files, use a file
623
             channel:
624
 
625
               channel=file:,
626
 
627
          B) To create an interactive terminal window, use an xterm channel:
628
 
629
               channel=xterm:[]*
630
 
631
          C) To create a bidirectional tcp socket which one could, for example,
632
             access via telnet, use a tcp channel:
633
 
634
               channel=tcp:
635
 
636
          D) To cause the UART to read/write from existing numeric file
637
             descriptors, use an fd channel:
638
 
639
               channel=fd:,
640
 
641
          E) To connect the UART to a physical serial port, create a tty
642
             channel:
643
 
644
               channel=tty:device=/dev/ttyS0,baud=9600
645
 
646 332 markom
     irq = 
647
        irq number for this device
648 428 markom
 
649 341 markom
     16550 = 0/1
650 876 rherveille
        '0': this device is a UART16450
651
        '1': this device is a UART16550
652 428 markom
 
653 312 markom
     jitter = 
654
        in msecs... time to block, -1 to disable it
655 428 markom
 
656 313 markom
     vapi_id = 
657
        VAPI id of this instance
658 312 markom
*/
659
 
660 261 markom
section uart
661 1461 nogj
  enabled = 1
662 1367 nogj
  baseaddr = 0x90000000
663
  irq = 2
664
  channel = "file:uart0.rx,uart0.tx"
665
  jitter = -1                     /* async behaviour */
666
  16550 = 1
667 261 markom
end
668
 
669 312 markom
 
670
/* DMA SECTION
671
 
672 876 rherveille
   This section configures the DMAs
673 312 markom
 
674 1461 nogj
     enabled = <0|1>
675
        Enable/disable the peripheral.  By default if it is enabled.
676
 
677 312 markom
     baseaddr = 
678
        address of first DMA register for this device
679
 
680
     irq = 
681
        irq number for this device
682 428 markom
 
683 313 markom
     vapi_id = 
684
        VAPI id of this instance
685 312 markom
*/
686
 
687 261 markom
section dma
688 1461 nogj
  enabled = 1
689 1370 nogj
  baseaddr = 0x9a000000
690
  irq = 11
691 261 markom
end
692 293 markom
 
693 304 markom
 
694 312 markom
/* ETHERNET SECTION
695
 
696 876 rherveille
   This section configures the ETHERNETs
697 312 markom
 
698 1461 nogj
     enabled = <0|1>
699
        Enable/disable the peripheral.  By default if it is enabled.
700
 
701 312 markom
     baseaddr = 
702
        address of first ethernet register for this device
703
 
704
     dma = 
705
        which controller is this ethernet "connected" to
706 428 markom
 
707 724 ivang
     irq = 
708
        ethernet mac IRQ level
709
 
710 725 ivang
     rtx_type = 
711
        use 0 - file interface, 1 - socket interface
712
 
713 312 markom
     rx_channel = 
714
        DMA channel used for RX
715 428 markom
 
716 312 markom
     tx_channel = 
717
        DMA channel used for TX
718
 
719 664 markom
     rxfile = ""
720 312 markom
        filename, where to read data from
721 428 markom
 
722 664 markom
     txfile = ""
723 312 markom
        filename, where to write data to
724 428 markom
 
725 724 ivang
     sockif = ""
726
        interface name of ethernet socket
727
 
728 313 markom
     vapi_id = 
729
        VAPI id of this instance
730 312 markom
*/
731
 
732 304 markom
section ethernet
733 1461 nogj
  enabled = 1
734 1372 nogj
  baseaddr = 0x92000000
735
  dma = 0
736
  irq = 4
737
  rtx_type = 1
738
  tx_channel = 0
739
  rx_channel = 1
740
  rxfile = "eth0.rx"
741
  txfile = "eth0.tx"
742
  sockif = "eth0"
743 304 markom
end
744 332 markom
 
745 1021 rherveille
 
746 486 erez
/* GPIO SECTION
747
 
748 876 rherveille
   This section configures the GPIOs
749 486 erez
 
750 1461 nogj
     enabled = <0|1>
751
        Enable/disable the peripheral.  By default if it is enabled.
752
 
753 486 erez
     baseaddr = 
754
        address of first GPIO register for this device
755
 
756
     irq = 
757
        irq number for this device
758
 
759
     base_vapi_id = 
760
        first VAPI id of this instance
761
        GPIO uses 8 consecutive VAPI IDs
762
*/
763
 
764
section gpio
765 1461 nogj
  enabled = 1
766 1374 nogj
  baseaddr = 0x91000000
767
  irq = 3
768
  base_vapi_id = 0x0200
769 486 erez
end
770
 
771 645 markom
/* VGA SECTION
772 1021 rherveille
 
773 876 rherveille
    This section configures the VGA/LCD controller
774 1021 rherveille
 
775 1461 nogj
      enabled = <0|1>
776
        Enable/disable the peripheral.  By default if it is enabled.
777
 
778 645 markom
      baseaddr = 
779
        address of first VGA register
780 1021 rherveille
 
781 645 markom
      irq = 
782
        irq number for this device
783 1021 rherveille
 
784 645 markom
      refresh_rate = 
785
        number of cycles between screen dumps
786 1021 rherveille
 
787 645 markom
      filename = ""
788
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
789
*/
790
 
791
section vga
792 1461 nogj
  enabled = 1
793 1368 nogj
  baseaddr = 0x97100000
794
  irq = 8
795
  refresh_rate = 100000
796
  filename = "primary"
797 645 markom
end
798
 
799 876 rherveille
 
800 1021 rherveille
/* TICK TIMER SECTION
801 876 rherveille
 
802 1021 rherveille
    This section configures tick timer
803
 
804 645 markom
    enabled = 0/1
805 1021 rherveille
      whether tick timer is enabled
806
 
807
    irq = 
808
      irq number
809
*/
810
/*
811
section tick
812
  enabled = 1
813
  irq = 0
814
end
815
*/
816
 
817
/* FB SECTION
818
 
819
    This section configures the frame buffer
820
 
821 1461 nogj
    enabled = <0|1>
822
      Enable/disable the peripheral.  By default if it is enabled.
823
 
824 664 markom
    baseaddr = 
825 645 markom
      base address of frame buffer
826 1021 rherveille
 
827 645 markom
    paladdr = 
828
      base address of first palette entry
829 1021 rherveille
 
830 645 markom
    refresh_rate = 
831
      number of cycles between screen dumps
832 1021 rherveille
 
833 645 markom
    filename = ""
834
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
835
*/
836
 
837
section fb
838 1461 nogj
  enabled = 1
839 1021 rherveille
  baseaddr = 0x97000000
840
  refresh_rate = 1000000
841 645 markom
  filename = "primary"
842
end
843 664 markom
 
844 1021 rherveille
 
845 664 markom
/* KBD SECTION
846
 
847 876 rherveille
    This section configures the PS/2 compatible keyboard
848 1021 rherveille
 
849 664 markom
    baseaddr = 
850
      base address of the keyboard device
851 1021 rherveille
 
852 664 markom
    rxfile = ""
853
      filename, where to read data from
854
*/
855
 
856
section kbd
857 1461 nogj
  enabled = 1
858 1021 rherveille
  irq = 5
859
  baseaddr = 0x94000000
860
  rxfile = "kbd.rx"
861 664 markom
end
862 876 rherveille
 
863
 
864
/* ATA SECTION
865 1021 rherveille
 
866 876 rherveille
    This section configures the ATA/ATAPI host controller
867 1021 rherveille
 
868 876 rherveille
      baseaddr = 
869
        address of first ATA register
870 1021 rherveille
 
871 1461 nogj
      enabled = <0|1>
872
        Enable/disable the peripheral.  By default if it is enabled.
873
 
874 876 rherveille
      irq = 
875
        irq number for this device
876
 
877 1701 nogj
      dev_id = 1/2/3
878
        Which OCIDEC version to imitate
879 876 rherveille
 
880 1701 nogj
      rev = 
881
        Revision of OCIDEC
882
 
883 1702 nogj
      pio_mode0_t1 = <0-255>
884
        PIO T1 reset value
885
 
886
      pio_mode0_t2 = <0-255>
887
        PIO T2 reset value
888
 
889
      pio_mode0_t4 = <0-255>
890
        PIO T4 reset value
891
 
892
      pio_mode0_teoc = <0-255>
893
        PIO Teoc reset value
894
 
895
      dma_mode0_tm = <0-255>
896
        DMA Tm reset value
897
 
898
      dma_mode0_td = <0-255>
899
        DMA Td reset value
900
 
901
      dma_mode0_teoc = <0-255>
902
        DMA Teoc reset value
903
 
904 1703 nogj
      Device specific
905 876 rherveille
 
906 1703 nogj
        type = 
907
          ata device 0 type
908
          0: NO_CONNECT: none (not connected)
909
          1: FILE      : simulated harddisk
910
          2: LOCAL     : local system harddisk
911 876 rherveille
 
912 1703 nogj
        file = ""
913
          filename for simulated ATA device
914
          valid only if dev_type0 == 1
915 876 rherveille
 
916 1703 nogj
        size = 
917
          size of simulated hard-disk (in MBytes)
918
          valid only if dev_type0 == 1
919 876 rherveille
 
920 1703 nogj
        packet = 
921
          0: simulated ATA device does NOT implement PACKET command feature set
922
          1: simulated ATA device does implement PACKET command feature set
923
 
924 1712 nogj
        firmware = 
925
          Firmware to report in `Identify device command'
926
 
927
        heads = 
928
          Number of default heads (-1)
929
 
930
        sectors = 
931
          Number of default sectors per track
932
 
933
        mwdma = 
934
          The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
935
 
936
        pio = 
937
          The highest supported pio mode; 4, 3, 2, 1, 0
938
 
939 876 rherveille
   FIXME: irq number
940
*/
941
 
942
section ata
943 1461 nogj
  enabled = 1
944 1364 nogj
  baseaddr = 0x9e000000
945
  irq = 15
946 1701 nogj
  dev_id = 1
947
  rev = 0
948 876 rherveille
 
949 1702 nogj
  pio_mode0_t1 = 6
950
  pio_mode0_t2 = 28
951
  pio_mode0_t4 = 2
952
  pio_mode0_teoc = 23
953
 
954
  dma_mode0_tm = 4
955
  dma_mode0_td = 21
956
  dma_mode0_teoc = 21
957
 
958 1703 nogj
  device 0
959
    type   = 1
960
    file   = "/tmp/sim_atadev0"
961
    size   = 1
962
    packet = 0
963 1712 nogj
 
964
    heads  = 7
965
    sectors = 32
966
 
967
    firmware = "02207031"
968
    mwdma = 2
969
    pio = 4
970 1703 nogj
  enddevice
971 876 rherveille
 
972 1703 nogj
  device 1
973
    type   = 0
974
    file   = ""
975
    size   = 0
976
    packet = 0
977
  enddevice
978 876 rherveille
end
979 897 markom
 
980
 
981
/* CUC SECTION
982
 
983
    This section configures the OpenRISC Custom Unit Compiler
984
 
985
    memory_order = none/weak/strong/exact
986
      none   different memory ordering, even if there are dependencies,
987
             burst can be made, width can change
988
      weak   different memory ordering, if there cannot be dependencies
989
             burst can be made, width can change
990
      strong same memory ordering, burst can be made, width can change
991
      exact  exacltly the same memory ordering and widths
992
 
993
    calling_convention = 0/1
994
      whether programs follow OpenRISC calling conventions
995
 
996
    enable_bursts = 0/1
997
      whether burst are detected
998
 
999
    no_multicycle = 0/1
1000
      if selected no multicycle logic paths will be generated
1001
 
1002
    timings_fn = ""
1003
*/
1004
 
1005
section cuc
1006
  memory_order = weak
1007
  calling_convention = 1
1008
  enable_bursts = 1
1009
  no_multicycle = 1
1010
  timings_fn = "virtex.tim"
1011
end
1012
 

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